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RT8159
12V Synchronous Buck PWM DC/DC and Linear Regulator
Controller
General Description
Features
The RT8159 is a dual-channel DC/DC regulator controller
specifically designed for dual outputs application in which
12V power source is available. This part consists of a
synchronous rectified buck PWM controller and a lowdropout linear regulator (LDO) controller. The buck PWM
controller utilizes voltage-mode control with external
compensation. The MOSFET gate drivers and bootstrap
diode are all integrated in the controller to minimize
external component count. The MOSFET gate drivers
provide 12V driving voltage for high-side and low-side
MOSFETs to achieve high efficiency power conversion.
The LDO controller drives an external N-MOSFET for low
power application. Other features include adjustable
oscillator frequency, internal soft start, fast transient
response, under voltage protection, enable/disable control,
and over current protection for PWM output. With the above
functions, RT8159 provides customers a compact, high
efficiency, and cost-effective solution.
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Applications
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Ordering Information
RT8159
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Package Type
S : SOP-14
Lead Plating System
G : Green (Halogen Free and Pb Free)
Single 12V Bias Supply
Support Dual Channel Power Conversion
` Synchronous Rectified Buck PWM Controller
` Linear Regulator Controller
Both Controllers Drive Low Cost N-MOSFETs
Adjustable Oscillator Frequency up to 1MHz with
230kHz Free-Running Frequency
Enable/ Disable Control
Integrated MOSFET Drivers and Bootstrap Diode
Internal Reference Voltage Accuracy
` PWM Controller : ±1%
` LDO Controller : ±2%
External Compensation for PWM Controller
Under Voltage Protection for Both Outputs
Low Side MOSFET RDS(ON) Current Sense
RoHS Compliant and Halogen Free
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Graphic Card GPU, Memory Core Power
Graphic Card Interface Power
Motherboard, Desktop and Servers Chipset and Memory
Core Power
IA Equipments
Telecomm Equipments
High Power DC/DC Regulators
Note :
Richtek products are :
`
Pin Configurations
RoHS compliant and compatible with the current require-
(TOP VIEW)
ments of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
BOOT
RT_DIS
COMP
FB
DRV
FBL
GND
14
2
13
3
12
4
11
5
10
6
9
7
8
UGATE
PHASE
PGND
LGATE
NC
NC
VCC
SOP-14
DS8159-02 April 2011
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1
RT8159
Typical Application Circuit
RBOOT
R6
12V
CVCC
VIN2
VOUT1 to 12V
CBOOT
RT8159
CIN2
Q3
ILOAD2
R4
VOUT2
COUT2
1 BOOT
8
VCC
5
DRV
6
FBL
R5
RRT
UGATE
PHASE
LGATE
PGND
2 RT_DIS
7 GND
EN
Q4
VIN1
3.3V to 12V
14
CIN1
RG
Q1
LOUT
ILOAD1
13
VOUT1
11
Q2
RSNB
CSNB
12
FB 4
3
COMP
C3
R3
COUT1
R1
C2
C1
R2
RF
Optional
Functional Pin Description
Pin No.
Pin Name
1
BOOT
2
RT_DIS
3
COMP
4
FB
5
DRV
6
FBL
7
GND
8
VCC
9, 10
11
Pin Function
Bootstrap Supply for the High Side MOSFET Gate Driver. Connect a bootstrap capacitor
from BOOT pin to PHASE pin. The bootstrap capacitor provides the charge to turn on the
high-side MOSFET.
This pin provides two functions : oscillator frequency setting and enable/disable control.
Connect a resistor from this pin to GND to set the internal oscillator frequency for PWM
switching regulator. The voltage at this pin is monitored for enable/disable control. If this
pin is externally pulled down below 0.4V, both switching regulator output and LDO output
will be disabled until it is released.
Error Amplifier Output Pin. Connect an R-C network between COMP pin and FB pin to
compensate the control loop of the buck converter.
This pin is the inverting input of the error amplifier of PWM controller. Connect this pin to
the buck converter output via resistor divider for output voltage sensing. The voltage at FB
pin is also monitored for under voltage protection. If FB voltage falls below 0.4V (50% of
VREF ), under voltage protection will be tripped to shutdown the controller.
Linear Regulator Controller Driver Output Pin. Connect this pin to the gate of an external
N-MOSFET.
This pin is the inverting input of the error amplifier of LDO controller. Connect this pin to the
LDO output via resistor divider for output voltage sensing. The voltage at FBL pin is also
monitored for under voltage protection. If FBL voltage falls below 0.4V (50% of VREF),
under voltage protection will be tripped to shutdown the controller.
Return Ground of the PWM and LDO Controller. Output voltage is regulated with respect
to this pin.
Controller Power Supply Pin. Connect this pin to a well-decoupled 12V bias supply. This
pin is also the power supply for the low-side MOSFET gate driver.
NC
No Internal Connection.
LGATE
Low Side MOSFET Gate Driver Output. Connect this pin to the gate of low-side
N-MOSFET. The voltage at this pin is monitored by the shoot-through protection circuitry
to prevent cross-conduction.
To be continued
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DS8159-02 April 2011
RT8159
Pin No.
Pin Name
12
PGND
13
PHASE
14
UGATE
Pin Function
Return Ground of the Low Side MOSFET Gate Driver.
Connect this pin to the switching node of the buck converter. This pin is also the return
ground of the high-side MOSFET gate driver. The voltage at this pin is monitored by the
shoot-through protection circuitry to prevent cross-conduction.
High Side MOSFET Gate Driver Output. Connect this pin to the gate of high-side
N-MOSFET.
Function Block Diagram
5VDD
Regulator
VCC
Voltage
Reference
5VDD
Power
On Reset
0.4V
VREF2
40µA
POR
-
FBL
OC
+
VCC
+
+
+
DRV
Inhibit
0.4V
-
Soft-Start
&
Fault Logic
-
+
ROCSET
20k
PH_M
-
SSE
1.5V
+
BOOT
UGATE
Shutdown
Inhibit
SSE
+
+ EA
-
VREF1
RT_DIS
+
PWM
CMP
Oscillator
LGATE
PGND
GND
FB
DS8159-02 April 2011
PHASE
Driver
Logic
COMP
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3
RT8159
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VCC -------------------------------------------------------------------------------------- 15V
BOOT to PHASE ------------------------------------------------------------------------------------------ 15V
z PHASE to GND
DC ------------------------------------------------------------------------------------------------------------- −0.3V to 32V
< 20ns ------------------------------------------------------------------------------------------------------- −8V to 38V
z UGATE to PHASE
DC ------------------------------------------------------------------------------------------------------------- −0.3V to 6V
< 20ns ------------------------------------------------------------------------------------------------------- −5V to 7.5V
z LGATE to GND
DC ------------------------------------------------------------------------------------------------------------- −0.3V to 6V
< 20ns ------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
z DRV ---------------------------------------------------------------------------------------------------------- GND − 0.3V to VCC + 0.3V
z Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND − 0.3V to 7V
z Power Dissipation, PD @ TA = 25°C
SOP-14 ------------------------------------------------------------------------------------------------------ 1.000W
z Package Thermal Resistance (Note 2)
SOP-14, θJA ------------------------------------------------------------------------------------------------- 100°C/W
z Junction Temperature ------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C
z Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
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Recommended Operating Conditions
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(Note 4)
Supply Voltage, VCC -------------------------------------------------------------------------------------- 12V ± 10%
Junction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 12V, TA = 25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
10.8
12
13.2
V
8.8
9.6
10.4
V
0.4
0.78
1.2
V
Supply Input
Power Supply Voltage
VCC
Power On Reset
VVCC_rth
Power On Reset Hysteresis
VVCC_hys
Power Supply Current
IVCC
UGATE, LGATE Open
--
3
--
mA
Free Running Frequency
fOSC, fr
RRT = NC
--
230
--
kHz
Switching Frequency
fOSC
RRT = 110kΩ
250
300
350
kHz
Ramp Amplitude
ΔVOSC
--
1.6
--
V
V CC Rising
Oscillator
To be continued
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DS8159-02 April 2011
RT8159
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
PWM Error Amplifier Reference VREF1
0.792
0.8
0.808
V
Linear Regulator Controller
Reference
0.784
0.8
0.816
V
70
88
--
dB
6
15
--
MHz
Reference Voltage
Error Amplifier
VREF2
(Note 5)
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
CLOAD = 5pF
3
6
--
V/μs
UGATE Drive Source
RUGATEsr
VBOOT − VPHASE = 12V,
VBOOT − VUGATE = 1V
--
4
8
Ω
UGATE Drive Sink
RUGATEsk
VUGATE = 1V
--
4
8
Ω
LGATE Drive Source
RLGATEsr
VCC – V LGATE = 1V
--
4
6
Ω
LGATE Drive Sink
RLGATEsk
VLGATE = 1V
--
2
4
Ω
Under Voltage Protection
VUVP
Measure FB Voltage
0.36
0.4
0.45
V
Soft-Start Time Interval
TSS
10% to 90% FB Voltage
2
3
4
ms
Over Current Threshold
VOC
Measure Phase Voltage
--
−400
--
mV
RT_DIS Shutdown Threshold
VSHDN_RT
0.35
0.4
--
V
Output High Voltage
VDRVH
9.5
10.3
--
V
Output Low Voltage
VDRVL
--
0.1
1
V
Source Current
IDRVSR
2
--
--
mA
Sink Current
IDRVSC
0.5
--
--
mA
MOSFET Gate Driver
Protection
Linear Regulator Controller
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity four layers test board of
JEDEC 51-7 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guarantee by design.
DS8159-02 April 2011
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5
RT8159
Typical Operating Characteristics
Power On
Power Off
ILOAD1 = 1A, ILOAD2 = 0.1A
ILOAD1 = ILOAD2 = 0.1A
V CC
(10V/Div)
V CC
(10V/Div)
VOUT1
(1V/Div)
VOUT2
(2V/Div)
VOUT1
(1V/Div)
VOUT2
(2V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
Time (2ms/Div)
Time (4ms/Div)
Enable from RT_DIS
Disable from RT_DIS
ILOAD1 = ILOAD2 = 0.1A
ILOAD1 = 0.2A, ILOAD2 = 0.3A
RT_DIS
(2V/Div)
RT_DIS
(2V/Div)
VOUT1
(1V/Div)
VOUT1
(1V/Div)
VOUT2
(2V/Div)
VOUT2
(2V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
Time (1ms/Div)
Time (4ms/Div)
LDO UVP
VOUT1 OCP
VOUT2
(100mV/Div)
inductor
current
(20A/Div)
VOUT1
(1V/Div)
VOUT1
(2V/Div)
UGATE
(20V/Div)
UGATE
(50V/Div)
LGATE
(10V/Div)
LGATE
(20V/Div)
VIN2 = 0V, ILOAD1 = 0.1A, power up
Time (10ms/Div)
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LSFET = IPD20N03L x 1
Time (2ms/Div)
DS8159-02 April 2011
RT8159
LDO Behavior while VOUT1 OCP
VOUT1 Short Circuit Protection
LSFET = IPD20N03L x 1
DRV
(5V/Div)
inductor
current
(20A/Div)
VOUT2
(2V/Div)
UGATE
(20V/Div)
inductor
current
(20A/Div)
LGATE
(20V/Div)
VOUT1
(200mV/Div)
VOUT1
(2V/Div)
short output then power up, LSFET = IPD20N03L x 1
Time (2ms/Div)
Time (2ms/Div)
LDO Behavior while VOUT1 Short Circuit
UGATE Rising Edge Dead Time
UGATE
inductor
current
(20A/Div)
LGATE
UGATE
(20V/Div)
DRV
(2V/Div)
VOUT2
(100mV/Div)
PHASE
UGATE−PHASE
(5V/Div)
ILOAD = 0A, RG = 0Ω
HSFET = LSFET = IPD09N03L x 1
short output then power up, LSFET = IPD20N03L x 1
Time (2ms/Div)
Time (20ns/Div)
UGATE Falling Edge Dead Time
PWM Regulator Transient Response
VIN1 = 12V, VOUT1 = 1.1V L = 1μH,
COUT1 = 820μF, ILOAD 1A to 20A
UGATE
I LOAD
(50A/Div)
PHASE
LGATE
VOUT1
(50mV/Div)
UGATE−PHASE
(5V/Div)
ILOAD = 0A, RG = 0Ω
HSFET = LSFET = IPD09N03L x 1
Time (20ns/Div)
DS8159-02 April 2011
UGATE
(20V/Div)
LGATE
(20V/Div)
Time (10μs/Div)
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RT8159
LDO Regulator Transient Response
PWM Regulator Transient Response
VIN1 = 12V, VOUT1 = 1.1V, L = 1μH,
COUT1 = 820μF, ILOAD = 1A to 20A
I LOAD
(50A/Div)
I LOAD
(0.5A/Div)
VOUT1
(50mV/Div)
VOUT2
(5mV/Div)
UGATE
(20V/Div)
LGATE
(20V/Div)
VIN2 = 3.3V, VOUT2 = 1.8V
COUT2 = 100μF, ILOAD = 0.1A to 1A
Time (100μs/Div)
Time (10μs/Div)
VREF1 vs. Temperature
0.808
VCC = 12V, No Load
0.806
VREF1 (V)
0.804
0.802
0.800
0.798
0.796
0.794
0.792
-50
-25
0
25
50
75
100
125
Temperature (°C)
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DS8159-02 April 2011
RT8159
Application Information
The RT8159 is a dual-channel DC/DC regulator controller
specifically designed for dual outputs application in which
12V power source is available. This part consists of a
synchronous rectified buck PWM controller and a lowdropout linear regulator (LDO) controller. The buck PWM
controller utilizes voltage-mode control with external
compensation. The MOSFET gate drivers and bootstrap
diode are all integrated in the controller to minimize
external component count. The MOSFET gate drivers
provide 12V driving voltage for high-side and low-side
MOSFETs to achieve high efficiency power conversion.
The LDO controller drives an external N-MOSFET for low
power application. Other features include adjustable
switching frequency, internal soft start, fast transient
response, under voltage protection, enable/disable control,
and low-side MOSFET RDS(ON) current sense.
If the RT_DIS pin is left open without any resistor connected,
the switching regulator will operate at the free-running
frequency, which is typically 230kHz. Figure 1 shows the
curve of the operating frequency vs. RRT value for quick
reference.
FSW vs. RRT
FSW (kHz)
Introduction
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
1
Frequency Setting and Enable/ Disable Control
The oscillator frequency of the switching regulator is
determined by the resistor RRT connected from RT_DIS
pin to GND pin. The oscillator frequency can be
approximately expressed as the function of RRT as follows:
6750
fSW ≅ 230 +
(kHz), RRT is in kΩ
RRT
DS8159-02 April 2011
100
1000
(kΩ)
RRRT
RT(kohm)
VCC, MOSFET Gate Driver and Bootstrap Diode
Connect a well-decoupled 12V power source to VCC pin
to power RT8159. VCC also powers the low side MOSFET
gate driver and the bootstrap circuit for the high -side
MOSFET gate driver. An internal linear regulator regulates
this 12V input to a 5VDD voltage as the power supply of
the internal control logic circuit. No external decoupling
capacitor is required for filtering this 5VDD voltage. The
RT8159 integrates the MOSFET gate driver and bootstrap
diode into the PWM controller. No external bootstrap diode
is required. This integration minimizes the external
component count for driving MOSFETs. The driving voltage
for both the high side and low-side MOSFET is 12V to
provide high efficiency at heavy load in low output voltage
application.
10
Figure 1. RRT vs. fSW
The voltage at RT_DIS pin is monitored for enable/disable
function, which provides the flexibility in power sequence
control. If RT_DIS pin is externally pulled down below 0.4V,
RT8159 will be disabled with UGATE, LGATE and DRV
go low. When RT_DIS pin is released, RT8159 initiates
the VIN1 detection followed by the soft start
operation.Connect a small-signal MOSFET from RT_DIS
pin to GND to implement the enable/disable control.
Power On Reset
The input voltage of RT8159 at VCC pin is continuously
monitored by the power on reset (POR) function. RT8159
begins to operate if VCC rises higher than the POR
threshold voltage. If VCC falls below the POR threshold,
RT8159 shuts down. There is hysteresis for the POR
threshold to avoid inadvertently shutdown.
PWM Switching Regulator Input Detection
The RT8159 has input voltage detection function for the
PWM switching regulator. After RT8159 is enabled and
VCC exceeds the POR threshold, a train of 10kHz pulse
with 1μs width is generated at UGATE to detect the
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9
RT8159
existence of input voltage of buck regulator. As shown in
Figure 2, the voltage at PHASE pin is monitored during
the detection. If the PHASE voltage crosses 1.5V (rising
and falling) for four times, the existence of V IN1 is
recognized ready. Once VIN1 is ready, RT8159 then
initializes the soft start operation as described in the
next section. Otherwise the 10kHz pulse at UGATE will
continue.
VIN1 POR_H
PHASE_M
PHASE
+
-
1.5V
ILOAD1 = ILOAD2 = 0.1A, power off VIN1
VIN1
(1V/Div)
VOUT1
(1V/Div)
DRV
(5V/Div)
UGATE
(20V/Div)
UGATE
Time (2ms/Div)
1st 2nd 3rd 4th PHASE
waveform
Figure 3. Power off VIN1 to Trip UVP
Internal counter will count (VPHASE > 1.5V)
four times (rising & falling) to recognize
VIN1 is ready.
Figure 2. Switching Regulator's Input Voltage Detection
Soft-Start
A built-in soft-start function is used to prevent surge current
from power supply input during start up (referring to the
Functional Block Diagram). The error amplifier EA is a
three-input device. SSE (internal soft start voltage) or VREF1
whichever is smaller dominates the non-inverting input.
The SSE linearly ramps up to about 4V after VIN1 existence
is recognized with about 2ms delay. Accordingly, the output
voltage ramps up smoothly to its target level. The rise
time of output voltage is about 3ms. VREF1 takes over the
non-inverting input of EA when SSE > VREF1. SSE is also
used for LDO soft-start. LDO input voltage VIN2 must be
ready before SSE starts to ramp up. Otherwise the UVP
function of LDO will be triggered to shut down the RT8159.
Under Voltage Protection
The voltages at FB and FBL pin are monitored for under
voltage protection (UVP) after the soft start is completed.
UVP is triggered if one of the feedback voltages is under
(50% x VREFx) with a 30μs delay. As shown in Figure 3,
the RT8159 PWM controller shuts down followed by VIN
detection pulses when VIN1 is powered off. In Figure 4,
the RT8159 shuts down after 4 times of UVP hiccups
triggered by FBL.
ILOAD1 = ILOAD2 = 0.1A, power off VIN2
VIN2
(5V/Div)
VOUT2
(1V/Div)
DRV
(10V/Div)
UGATE
(50V/Div)
Time (20ms/Div)
Figure 4. LDO UVP by Power off VIN2
Over Current Protection
The RT8159 utilizes low-side MOSFET RDS(ON) peak
current sensing technique. After low-side MOSFET is
turned on, the PHASE voltage is sensed for over current
protection (OCP). As shown in the Functional Block
Diagram, A 40μA internal current source flows through a
20kΩ internal resistor ROCSET, causing 0.8V voltage drop
across ROCSET. If the PHASE voltage (drop of lower
MOSFET VDS) is lower than 0.4V while low side MOSFET
is conducting, OCP will be tripped with UGATE and LGATE
go low as shown in Figure 5. Once OCP is triggered, the
RT8159 enters hiccup mode and soft-starts again. The
RT8159 shuts down after 4 times of OCP hiccups. The
inductor peak current, IOCSET, for OCP can be approximately
calculated using below equation :
40μ A × ROCSET − 0.4V
0.4V
IOCSET ≅
=
RDS(ON)
RDS(ON)
For example, if RDS(ON) =16mΩ, the OCP threshold is
about 25A.
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DS8159-02 April 2011
RT8159
LSFET = IPD20N3L x 1
VOUT1
(2V/Div)
inductor
current
(20A/Div)
The system open loop gain
has one pole at FLC
V̂COMP
and one zero at FESR. The frequency of FLC and FESR can
be calculated using the following expressions :
1
FLC =
2π x LOUT x COUT
FESR =
UGATE
(20V/Div)
LGATE
(20V/Div)
Time (4μs/Div)
Figure 5. Detailed Waveform of PWM OCP
PWM Feedback Loop Compensation
RT8159 operates with fixed frequency and uses voltage
mode control for output voltage regulation. The IC utilizes
voltage error amplifier with external compensation to provide
flexibility in feedback loop compensator design. Figure 6
shows the voltage mode control loop of a buck converter.
The control loop consists of the modulator, power stage
and the compensator.
LOUT
Q1
DCR VOUT
To Load
CIN
ESR
MOSFET
Driver
Q2
COUT
1
2π x COUT x ESR
In order to obtain an accurate output voltage regulation
and fast transient response, a compensator is necessary.
Depends on the inductor and output capacitor, different
type of compensator can be used to finish the feedback
loop compensation. By inserting a well designed
compensator into the feedback loop, the closed loop
control-to-output transfer function can be shaped to have
adequate crossover frequency and sufficient phase margin.
The design goals are:
z
z
z
VIN
V̂OUT
Obtain high gain at low frequency for DC regulation
accuracy
Obtain sufficient bandwidth for transient performance
(generally, 1/10 to 1/5 switching frequency)
Obtain sufficient phase margin for stability (generally
>45°)
Figure 7 shows the Type-III compensator, which is
composed of voltage error amplifier, impedance network
Z1 and Z2.
Z2
C2
Z2
PWM
Comparator
+
-
COMP
FB
EA
+
R2
C1
Z1
Z1
C3
VREF
RFB2
Ramp
COMP
FB
EA
+
R3
R1
VOUT
Figure 6. Voltage Mode Control Loop of Buck Converter
VREF
Output voltage of the converter is scaled by the divider
resistors and then compared to the reference voltage, which
is the regulation level seen by the controller. The error
amplifier output voltage VCOMP is compared to the sawtooth waveform from the oscillator to generate PWM signal.
The output voltage is then regulated according to the duty
cycle of the PWM signal.
RF
Figure 7. Type-III Compensator
The Type-III compensator introduces three poles and two
zeros to the system. The first pole is located in low
frequency to increase the DC gain for voltage regulation
accuracy and is usually referred to as the pole-at-zero.
The location of rest of the two poles and two zeros can be
determined as follows :
DS8159-02 April 2011
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11
RT8159
FP1 =
1
1
, FZ2 =
2π x R2 x C1
2π x (R3 + R1) x C3
1
1
, FP2 =
2π x R3 x C3
⎛ C1 x C2 ⎞
2π x R2 x ⎜
⎟
⎝ C1 + C2 ⎠
Figure 8 shows the system Bode plot. The close loop
gain is the sum of modulation gain and the compensation
gain. The modulation DC gain is determined by VIN/ΔVOSC,
where ΔVOSC is peak to peak voltage of the saw-tooth
ramp. In general, FZ1 is placed at half of FLC, and FZ2 is
placed at FLC to boost the large phase lag created by the
double pole especially when ESR is low. FP1 is typically
placed at FESR to obtain a −20dB/dec slope at crossover
frequency. FP2 is placed at half of the switching frequency
to increase the attenuation in high frequency.
After calculating the compensation values, draw the
system Bode plot to check the crossover frequency and
phase margin. Due to the circuit parasitic components
and the characteristic deviation in the inductor and output
capacitors, further tuning of the compensation value to
obtain the required crossover frequency and phase margin
is necessary.
(dB)
FLC
FESR
Compensation Gain
Freq.(Log)
0
Close Loop Gain
FZ1
FP1
FZ2
FP2
Modulation Gain
FCROSS
Figure 8. System Bode Plot
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
Where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8159, The maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For SOP-14 package, the thermal resistance
θJA is 100°C/W on the standard JEDEC 51-7 four layers
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula :
PD(MAX) = (125°C − 25°C) / (100°C/W) = 1.000W for
SOP-14 package
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. Figure 9 shows the derating curve of
maximum power dissipation of RT8159.
1.2
Maximum Power Dissipation (W)1
FZ1 =
Four Layers PCB
1.1
1.0
0.9
0.8
SOP-14
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 9. Derating Curve for RT8159 Package
Layout Considerations
PCB layout is critical to high-current high-frequency
switching converter design. A good layout can help the
controller to function properly and obtain better
performance. On the other hand, the circuit may have more
power loss, pool performance and even malfunction if
without a carefully layout. Figure 10 shows the
connections of the critical components in the buck
converter. In order to obtain better performance, the general
guidelines of PCB layout are listed as follows.
PD(MAX) = ( TJ(MAX) − TA ) / θJA
www.richtek.com
12
DS8159-02 April 2011
RT8159
`
Power stage components should be placed first. Place
the input bulk capacitors close to the high-side power
MOSFETs, and then locate the output inductor then
finally the output capacitors.
`
Providing enough copper area around power MOSFETs
to help heat dissipation. Using thick copper also
reduces the trace resistance and inductance to have
better performance.
`
Placing the ceramic capacitors physically close to the
drain of the high-side MOSFET. This can reduce the
input voltage drop when high-side MOSFET is turned
on.
`
The output capacitors should be placed physically close
to the load. This can minimize the trace parasitic
components and improve transient response.
`
All small signal components should be placed close to
the controller. The small signal components include the
feedback voltage divider resistors, compensator, function
setting components and high-frequency bypass
capacitors. The feedback voltage divider resistor and the
compensator must be placed close to FB pin and COMP
pin, because these pins are inherently noise-sensitive.
`
Voltage feedback path must be kept away from switching
nodes. The switching nodes, such as the
interconnection between high-side MOSFET, low-side
MOSFET and inductor, is extremely noisy. Feedback
path must be kept away from this kind of noisy node to
avoid noise pick-up.
`
A multi-layer PCB design is recommended. Use one
single layer as the ground and have separate layers for
power rail or signal.
`
`
Keep the high-current loops as short as possible. The
current transition between MOSFETs usually causes
di/dt voltage spike due to the parasitic components on
PCB trace and component lead. Therefore, making the
trace length between power MOSFETs and inductors
wide and short can reduce the voltage spike and also
reduce EMI.
Make MOSFET gate driver path as short as possible.
Since the gate driver uses high-current pulses to switch
on/off power MOSFET, the driver path must be short to
reduce the trace inductance. This is especially important
for low-side MOSFET because this can reduce the
possibility of shoot-through. Besides, also make the
width of gate driving path as wide as possible to reduce
the trace resistance. The PCB traces between the PWM
controller and the gate/source of MOSFET should be
sized to carry 2A peak currents.
Place RRT
close to IC
Place compensation
components close to IC.
Place CIN2 close
to MOSFET.
VIN2
VOUT2
Keep voltage feedback
trace away from noisy node.
Place CIN close
to MOSFET.
VIN1
MOSFET driver trace :
wide and short.
BOOT
RT_DIS
COMP
FB
DRV
FBL
GND
14
2
13
3
12
4
11
5
10
6
9
7
8
Enough copper area
to carry load current.
UGATE
PHASE
PGND
LGATE
NC
NC
VCC
LOAD
12V
Place voltage divider
resistors close to IC.
Place noise decoupling
MLCC close to IC.
Enough via to
inner ground layer.
VOUT1
LOAD
Place COUT
close to load.
Place snubber close
to low-side FET.
Figure 10. PCB Layout Guide
DS8159-02 April 2011
www.richtek.com
13
RT8159
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
8.534
8.738
0.336
0.344
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.178
0.254
0.007
0.010
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
M
0.406
1.270
0.016
0.050
14–Lead SOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
www.richtek.com
14
DS8159-02 April 2011
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