Data Sheet

Power System Sequencer
TRKF- 44D62ER
On Board Power System Controller
RoHS Compliant
•
Digital Signal Processor (DSP) Based with Bel Firmware
•
Provides Power Up and Power Down Sequencing Logic
•
Stand Alone or Command Based Feature Set
•
Fault Detection and Reporting
•
44 Pin 10mm x 10mm TQFP package
•
I2C, SMBus, or PMBus compatible serial interface options
•
Configurable through serial interface, Customizable through software
•
3V3 logic levels
•
Voltage Margining via Closed Loop Trim
•
Programmed parameters saved in non volatile memory
•
Intelligent configuration capability
Description
This on board power system controller provides a cost effective high performance solution for controlling,
monitoring, and sequencing multiple Point of Load (POL) converters on a system board. The sequencer uses a
digital signal processor (DSP) engine and Bel’s firmware to implement a portfolio of board level control features
typically required in a multiple voltage configuration. The solution can control and monitor up to four PoL
converters and monitor up to two analog inputs. The 44 pin TRKF-44D62ER is derived from Bel’s 64 pin TRKF64D82ER platform with less I/O offering a lower cost option for smaller boards.
Optional Feature Sets
SDA
I2C
SCL
Digital
Commands
EE^2 Data Logging
Input Inrush Control
Communication
and
Command Interface
Vin Monitor
A
B
C/Optional SS for SPI
Vout ADC Input
Vin
Vin
Digital Output
Enable
PoL 1 of n
Trim PWM
Vout
Vout 1of n
Trim
Rfilter
Rlimit
GND
Cfilter
Control Grouping 1 of n
Figure 1
Functional Block Diagram
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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Power System Sequencer
TRKF- 44D62ER
I/O Definitions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin Name
I2CDATA
POL_4_ENABLE
POL_3_ENABLE
POL_2_ENABLE
POL_1_ENABLE
VSS
VCAP/VDDCORE
IOPIF_ENABLE
RESET_OUT
POL_4_MGN_PWM
POL_3_MGN_PWM
PWR_GOOD
WARNING
POL_2_MGN_PWM
POL_1_MGN_PWM
AVSS
AVDD
MCLR*
REF_IN
REF_RETURN
POL_MONITOR_1
POL_MONITOR_2
POL_MONITOR_3
POL_MONITOR_4
VIN_MONITOR
ANALOG_MON_X
ANALOG_MON_Y
VDD
VSS
BOARD_SEATED
MFG_MODE
SPARE1
VID_INPUT_6
VID_INPUT_5
VID_INPUT_4
VID_INPUT_3
VID_INPUT_2
VID_INPUT_1
VSS
VDD
MGN_HI_N/ICD_SDA
MGN_LO_N/ICD_SCL
RESET_IN
I2CCLOCK
Type
I2C
Output
Output
Output
Output
Power
Power
Output
Output
PWM Margin out
PWM Margin out
Output
Output
PWM Margin out
PWM Margin out
Power
Power
Input/Power
Analog input
Analog input
Analog Input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog Input
Power
Power
Digital input
Digital input
I/O
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Power
Power
Digital input
Digital input
Digital input
I2C
Signal Description
I2C DATA
POL 4 Enable
POL 3 Enable
POL 2 Enable
POL 1 Enable
3.3V Power Input Return
Core Decoupling Capacitor
Reset signal
POL 4 PWM Trim
POL 3 PWM Trim
System power good signal
Warning signal
POL 2 PWM Trim
POL 1 PWM Trim
Analog Ground
Filtered VDD (analog VDD)
Master clear reset
Vref+
VrefPOL 1 Monitor
POL 2 Monitor
POL 3 Monitor
POL 4 Monitor
Vin Monitor
Vcc CMD Measure
PIF Output Measure
3.3V Power Input
3.3V Power Input Return
Indicates if board plugged in
Indicates if in manufacturing mode
Spare I/O
3.3V Power Input Return
3.3V Power Input
Mgn_hi / ICD debug port
Mgn_lo / ICD debug port
Reset input from SP
I2C CLOCK
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
2
Power System Sequencer
TRKF- 44D62ER
Powering the Sequencer
VDD Core
C8
2.2 uF
10v
X5R
D1
BAT54
+12Vin
In
R1
20 Ohm
1206
+12Vin Return
C1
1000uF
25V
C2
1uF
16v
X5R
Microchip P/N
MCP1702T-3302I/MB
or Equivalent
VDD
Out
3V3 Output LDO
C4
1uF
16v
X5R
GND
R2
4.64 Ohm
C5
1uF
16v
X5R
C6
1uF
16v
X5R
C7
1uF
16v
X5R
VSS
AVDD
C3
2.2 uF
10v
X5R
AVSS
R3
1 Ohm
FIGURE 2
VDD Interface
Figure 2 is a schematic of the typical VDD interface to the sequencer IC. A Microchip LDO, P/N MCP1702T3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most
applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V
source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors for the DSP and they should be located
directly across each pair of VDD and VSS pins on the DSP IC. The 44 pin device has a VDD core pin which is
used to decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the VDD
core which is not required with the 44 pin device. This decoupling capacitor should be a low ESR ceramic
capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog VDD (AVDD) and
it should be located directly across the AVDD and AVSS pins on the DSP IC. Resistor R2 in combination with C3
provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the
input decoupling capacitor for the LDO and it should be connected directly across the LDO’s input and ground
pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and
maintain a stable VDD for the DSP for a short period after the +12Vin source is removed. This would be desired if
a short communication stream is required during power down or if storing system data to EE memory is required
during power down. The Schottky diode D1 prevents C1 from being discharged after +12Vin is removed.
Resistor R1 is used to protect D1 during the inrush event associated with the application of the +12Vin. The
single pulse peak current rating for a typical BAT54 diode is approximately 600mA. If the rise time of the +12V
source is slow enough to limit the peak charging current into C1 it is possible to eliminate R1. Assuming a
40mA current draw by the DSP C1 will provide approximately 188 uS of hold up time per uF of capacitance.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
3
Power System Sequencer
TRKF- 44D62ER
Using the PWM Trim Outputs
+Sense
+Vin
Zf
Ry
TRIM
-
Zi
Rx
+Vout
Rz
PWM
E/A
+
Reference
Figure 3A.
+Sense
+Vin
Zf
-
Zi
+Vout
PWM
E/A
+
TRIM
Rx
Ry
Reference
Figure 3B.
+Sense
+Vin
Zf
-
Zi
+Vout
PWM
E/A
Reference
TRIM
+
uController
or Equivalent
Figure 3C.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
4
Power System Sequencer
TRKF- 44D62ER
The drawings in figure 3 show the three most common trim methods used in PoL converters. In all of these
schemes a power conversion stage contains a PWM device that receives a control voltage from an error
amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output
voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value.
The output voltage can be adjusted by changing this scaling factor (Figure 3A) or by modifying the reference
(Figures 3B, C).
The most common trim method is shown in figure 3A. The popularity of this method stems from the fact that
most highly integrated PWM control IC’s have an internal reference that is not accessible and cannot be
controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This
modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified
by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin
through a resistor. Either of these two approaches will move the output voltage to a new value. The common
characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher
output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease.
Some PoL converters incorporate the trim scheme shown in figure 3B. With this method the feedback ratio is
kept constant and the reference value is modified to move the output voltage. The common characteristic of
modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and
a larger voltage superimposed on the trim pin will cause Vout to increase.
The method shown in figure 3C is occasionally used. This is similar to the method in figure 3B except the
modification of the reference is mapped through a device such as a microcontroller. This is the least common of
the 3 methods and requires the vendor’s data sheet to determine the trim characteristic because the micro
controller can map the reference in many different ways.
PoL Vout
or
VDD
VTrim Ripple
VTrim Average
Margin PWM
PoL Trim Pin
Ra
3V3
Ca
Rb
Ca
0
Margin PWM
PoL Trim Pin
Ra
Rb
3V3
VTrim Average
0
VTrim Ripple
Figure 4B
Figure 4A
The power sequencer has the ability to do independent closed loop trim and closed loop margining of the output
voltage for each PoL controlled by the device. Each PoL’s output voltage is monitored and by an analog to
digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared
against the desired value and the PoL’s output is adjusted by delivering a trim value to the corresponding PoL’s
trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital
PWM is labeled <PoL “n” Margin PWM> where n indicates a specific converter which corresponds to the
monitoring channel labeled with the same “n” value. The external low pass filter creates a DC value from the
PWM signal which is then delivered to each PoL converter through a range limiting resistor.
Figure 4 shows the typical circuits used to interface the sequencers Margin PWM signals to PoL converters. In
each of the circuits shown Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The
effective trim voltage is equal to the Margin PWM duty cycle multiplied by VDD and is controllable in 1024 steps
from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim
voltage ripple. Typical values for Ra and Ca are 1K for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
5
Power System Sequencer
TRKF- 44D62ER
control range and should be selected based on the desired control range and the trim equation for the PoL.
This trim equation is usually available from the PoL manufactures data sheet. The sequencer learns the trim
direction by making a minor adjustment to the Margin PWM and then determining the direction that Vout moves
based on this stimulus. Once the trim direction is known it knows whether increment or decrement the TRIM
PWM value until the desired Vout is achieved. The accuracy of the active trim is a function of the ADC accuracy
which is mostly controlled by accuracy of the applied reference to the sequencers Vref pins.
Either circuit in Figure 4 will work with any of the trim methods shown in Figure 3. When interfacing to PoL
modules that use the trim method in Figure 3A the circuit in Figure 4B is the optimum interface configuration. By
connecting the filter capacitor Ca to the PoL’s Vout or to a positive voltage reference the effective of filtering the
Margin PWM signal remains intact. With this method there will not be a discharged capacitor connected to
ground that could cause the PoL’s output to overshoot during power up as this capacitor becomes charged. In
the case that the circuit in figure 4A is used with the trim configuration in Figure 3B the sequencer will precharge the capacitor before enabling the PoL converter and then decrement the Margin PWM to achieve the
desired Vout. This requires additional start up time during system initialization. When interfacing to PoL
converters of the type shown in Figure 3B the interface circuit in figure 4A is optimum.
Monitoring Via ADC Channels
The imbedded ADC channels are converted as 10 bit results with full scale equal to a chosen reference. The
device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC
reference or to use an externally provided reference. Closed loop margining and set point adjustments always
use the entire 10 bit result to trim the output voltages to loaded values. Monitored voltages are reported via I2C
communication using PMBus data formats as defined in the separate communication manual. The voltage
range reported is determined by the entered set points. Any monitored output that is greater than the ADC
reference or that can be margined above this reference should have a voltage divider to limit the maximum input
to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages below
the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the
ADC results. In most cases this will eliminate the need for external filtering.
The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value
less than the maximum value of the ADC reference.
Connecting the Control and Monitoring
The three primary control interface signals to the attached PoL converters are an enable signal, a voltage
monitoring signal, and trim control signal. The enable signals are labeled <PoL “n” Enable>. The Monitoring
signals are labeled <PoL Monitor “n”>. The trim signals are labeled <PoL “n” Margin PWM>. Each n’th PoL
converter is required to share the corresponding enable, monitor, and trim signals. For example the first PoL
converter attached to the controller is PoL 1. PoL 1 should use <PoL 1 Enable>, <PoL Monitor 1>, and PoL 1
Margin PWM, etc.. The installed firmware assumes that the connections are made this way when controlling
system.
Communicating to the Device
Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus
command set and is defined in a separate communications manual. The communications manual also defines
the protocol for device programming via embedded boot loader software.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
6
Power System Sequencer
TRKF- 44D62ER
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
7
Power System Sequencer
TRKF- 44D62ER
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V
Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ................................................................................................... ..........................250 mA
Maximum output current sunk by any I/O pin............................................................................................................4 mA
Maximum output current sourced by any I/O pin ......................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Electrical Specifications
Parameter
Input Voltage Range
Input Current
Logic Low Input Level
Logic High Input Level
Logic Low Output Level
Logic High Output Level
VDD Rise Rate
Capacitance I/O Pin to
GND
I2C Bus Capacitance
PWM Series Resistor
Margin PWM Frequency
Reference Input
Symbol
VDD
IDD
VIL
VIH
VOL
VOH
SVDD
Min
Typ
Max
3.0
3.30
58
3.6
VSS
0.2*VDD
0.8*VDD
VDD
0.4
2.4
0.05
CIO
CB
RPWM
FPWM
Vref
50
pF
400
pF
KΩ
KHz
VDC
1
10
AVDD
AVSS + 1.7
Units
VDC
mA
VDC
VDC
VDC
VDC
V/uS
Notes
+85C
VDD = 3.3V
VDD = 3.3V, IOH = -3.0mA
0 to 3.3V in 100mS
SCl and SDA
External Series Resistor
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
8
Power System Sequencer
TRKF- 44D62ER
Mechanical Outline
Bel 44-pin 10x10x1mm TQFP Sequencer
Figure 5A
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
9
Power System Sequencer
TRKF- 44D62ER
44-Lead Plastic Thin-Quad Flatpack, 10 x 10 x 1mm Body
Units
Millimeters
Dimension Units
Min
Nom
Number of Leads
N
44
Lead Pitch
e
0.80 BSC
Overall Height
A
Molded Package Thickness
A2
0.95
1.00
Standoff
A1
0.05
Foot Length
L
0.45
0.60
Footprint
L1
1.00 REF
Foot Angle
0˚
3.5˚
φ
Overall Width
E
12.00 BSC
Overall Length
D
12.00 BSC
Molded Package Width
E1
10.00 BSC
Molded Package Length
D1
10.00 BSC
Lead Thickness
c
0.09
Lead Width
b
0.30
0.37
Mold Draft Angle Top
11˚
12˚
α
Mold Draft Angle Bottom
11˚
12˚
β
Max
1.20
1.05
0.15
0.75
7˚
0.20
0.45
13˚
13˚
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Champers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Figure 5B
RoHS Compliance
Complies with the European Directive 2002/95/EC, calling for the elimination of lead and other hazardous
substances from electronic products.
© 2008 Bel Fuse Inc. Specifications subject to change without notice. 120808
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
10
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