GENERAL DESCRIPTION VS– VOCMA VOCMB 22 21 20 19 AD8133 VS– 2 17 VS+ –IN A 3 16 –IN C 15 +IN C 4 VS– 5 B A 14 VS– C 10 11 12 +OUT C VS+ 9 VS+ 8 –OUT B 7 +OUT B 13 –OUT C +OUT A –OUT A 6 04769-0-001 +IN A 18 VOCMC Figure 1. 0 ∆VOUT, dm = 2V p-p ∆VOUT, cm/∆VOUT, dm –10 –20 VS = ±5V –30 –40 –50 VS = +5V –60 –70 –80 –90 The AD8133 is a major advancement beyond using discrete op amps for driving differential RGB signals over twisted pair cable. The AD8133 is a triple, low cost differential or singleended input to differential output driver, and each amplifier has a fixed gain of 2 to compensate for the attenuation of line termination resistors. The AD8133 is specifically designed for RGB signals but can be used for any type of analog signals or high speed data transmission. The AD8133 is capable of driving either Category 5 unshielded twisted pair (UTP) cable or differential printed circuit board transmission lines with minimal signal degradation. The outputs of the AD8133 can be set to a low voltage state to be used with series diodes for line isolation, allowing easy differential multiplexing over the same twisted pair cable. The AD8133 driver can be used in conjunction with the AD8129 and AD8130 differential receivers. Rev. A 23 04769-0-034 KVM (keyboard-video-mouse) networking UTP (unshielded twisted pair) driving Differential signal multiplexing 24 OPD 1 OUTPUT BALANCE ERROR (dB) APPLICATIONS +IN B FUNCTIONAL BLOCK DIAGRAM Triple high speed fully differential driver 225 MHz −3 dB large signal bandwidth Easily drives 1.4 V p-p video signal into source-terminated 100 Ω UTP cable 1600 V/µs slew rate Fixed internal gain of 2 Internal common-mode feedback network Output balance error −60 dB @ 50 MHz Differential input and output Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Output pull-down feature for line isolation Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply, RL, dm = 200 Ω Low offset: 4 mV typical output referred on 5 V supply Low power: 26 mA @ 5 V for three drivers Wide supply voltage range: +5 V to ±5 V Available in space-saving packaging: 4 mm × 4 mm LFCSP –IN B FEATURES VS+ Data Sheet Triple Differential Driver with Output Pull-Down AD8133 –100 1 10 FREQUENCY (MHz) 100 500 Figure 2. Output Balance vs. Frequency Manufactured on Analog Devices’ next generation XFCB bipolar process, the AD8133 has a large signal bandwidth of 225 MHz and a slew rate of 1600 V/µs. The AD8133 has an internal common-mode feedback feature that provides output amplitude and phase matching that is balanced to −60 dB at 50 MHz, suppressing harmonics and minimizing radiated electromagnetic interference (EMI). The output common-mode level is easily adjustable by applying a voltage to the VOCM input pin. The VOCM input can also be used to transmit signals on the output common-mode voltages. The AD8133 is available in a 24-lead LFCSP package and can operate over the temperature range of −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8133 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Calculating an Application Circuit’s Input Impedance ......... 14 Applications ....................................................................................... 1 General Description ......................................................................... 1 Input Common-Mode Voltage Range in Single-Supply Applications .................................................................................. 14 Functional Block Diagram .............................................................. 1 Driving a Capacitive Load......................................................... 14 Revision History ............................................................................... 2 Output Pull-Down (OPD) ........................................................ 14 Specifications..................................................................................... 3 Output Common-Mode Control ............................................. 14 Absolute Maximum Ratings ............................................................ 5 Applications..................................................................................... 15 Thermal Resistance ...................................................................... 5 Driving RGB Video Signals Over Category-5 UTP Cable.... 15 ESD Caution .................................................................................. 5 Output Pull-Down ..................................................................... 16 Pin Configuration and Function Descriptions ............................. 6 KVM Networks........................................................................... 16 Typical Performance Characteristics ............................................. 7 Layout and Power Supply Decoupling Considerations .... 16 Test Circuit ...................................................................................... 12 Amplifier-to-Amplifier Isolation ............................................. 16 Theory of Operation ...................................................................... 13 Exposed Paddle (EP).................................................................. 16 Definition of Terms .................................................................... 13 Outline Dimensions ....................................................................... 17 Analyzing an Application Circuit............................................. 13 Ordering Guide .......................................................................... 17 Closed-Loop Gain ...................................................................... 13 REVISION HISTORY 3/16—Rev. 0 to Rev. A Changed CP-24 to CP-24-10 ............................................. Universal Changes to Figure 4 and Table 5 ..................................................... 6 Added Test Circuit Section............................................................ 12 Moved Figure 33; Renumbered Sequentially .............................. 12 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 7/04—Revision 0: Initial Version Rev. A | Page 2 of 17 Data Sheet AD8133 SPECIFICATIONS VS = ±5V, VOCM = 0 V @ 25°C, RL, dm = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +85°C. Table 1. Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Isolation between Amplifiers DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance DC CMRR DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain Output Voltage Swing Output Offset Voltage Output Offset Drift Output Balance Error Output Voltage Noise (RTO) Output Short-Circuit Current VOCM to VO, cm PERFORMANCE VOCM DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate DC Gain VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Offset Voltage Drift DC CMRR POWER SUPPLY Operating Range Quiescent Current PSRR OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage OPD Input High Voltage OPD Input Bias Current OPD Assert Time OPD De-Assert Time Output Voltage When OPD Asserted Conditions Min Typ Max Unit VO = 0.2 V p-p VO = 2 V p-p VO = 0.2 V p-p VO = 2 V p-p VO = 2 V p-p, 25% to 75% VO = 2 V Step f = 10 MHz, between Amplifiers A and B 450 225 60 55 1600 15 81 MHz MHz MHz MHz V/µs ns dB Differential Single-Ended Input Differential ΔVOUT, dm/ΔVIN, cm, ΔVIN, cm = ±1 V −5 to +5 1.5 1.13 1 −50 V kΩ kΩ pF dB ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±1 V Each Single-Ended Output 1.925 VS− + 1.9 −24 1.960 TMIN to TMAX ΔVOUT, cm/ΔVIN, dm, ΔVOUT, dm = 2 V p-p, f = 50 MHz DC f = 1 MHz +4 ±30 −60 −70 25 90 ΔVOCM = 100 mV p-p VOCM = −1 V to +1 V, 25% to 75% ΔVOCM = ±1 V 330 1000 0.995 0.980 −15 TMIN to TMAX ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V ±3.1 70 −6 ±50 −42 +4.5 ΔVOUT, dm/ΔVS; ΔVS = ±1 V 28 −84 Each Output, OPD Input @ VS+ VS− to VS+ − 4.15 VS+ − 3.15 to VS+ 67 100 100 VS− + 0.86 Rev. A | Page 3 of 17 2.000 VS+ – 1.6 +24 −58 1.005 V/V V mV µV/°C dB dB nV/√Hz mA MHz V/µs V/V +15 V kΩ mV µV/°C dB ±6 29 −76 V mA dB 90 VS− + 0.90 V V µA ns ns V AD8133 Data Sheet VS = 5 V, VOCM = 2.5 V @ 25°C, RL, dm = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +85°C. Table 2. Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Isolation Between Amplifiers DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance DC CMRR DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain Output Voltage Swing Output Offset Voltage Output Offset Drift Output Balance Error Output Voltage Noise (RTO) Output Short-Circuit Current VOCM PERFORMANCE VOCM DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate DC Gain VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Offset Voltage Drift DC CMRR POWER SUPPLY Operating Range Quiescent Current PSRR OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage OPD Input High Voltage OPD Input Bias Current OPD Assert Time OPD De-Assert Time Output Voltage When OPD Asserted Conditions Min Typ Max Unit VO = 0.2 V p-p VO = 2 V p-p VO = 0.2 V p-p VO = 2 V p-p, 25% to 75% VO = 2 V Step f = 10 MHz, between Amplifiers A and B 400 200 50 1400 14 75 MHz MHz MHz V/µs ns dB Differential Single-Ended Input Differential ΔVOUT, dm/ΔVIN, cm, ΔVIN, cm = ±1 V 0 to 5 1.5 1.13 1 −50 V kΩ kΩ pF dB ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±1 V Each Single-Ended Output 1.925 VS− + 1.25 −24 1.960 TMIN to TMAX ΔVOUT, cm/ΔVIN, dm, ΔVOUT, dm = 2 V p-p, f = 50 MHz DC f = 1 MHz +4 ±30 −60 −70 25 90 ΔVOCM = 100 mV p-p VOCM = −1 V to +1 V, 25% to 75% ΔVOCM = ±1 V, TMIN to TMAX 290 700 0.995 0.980 −15 TMIN to TMAX ΔVO, dm/ΔVOCM; ΔVOCM = ±1 V 1.25 to 3.85 70 +2 ±50 −42 +4.5 ΔVOUT, dm/ΔVS; ΔVS = ±1 V 26 −84 Each Output, OPD Input @ VS+ VS− to VS+ − 3.85 VS+ − 2.85 to VS+ 63 100 100 VS− + 0.79 Rev. A | Page 4 of 17 2.000 VS+ − 1.15 +24 −58 1.005 V mV µV/°C dB dB nV/√Hz mA MHz V/µs V/V +15 V kΩ mV µV/°C dB ±6 27 −76 V mA dB 80 VS− + 0.82 V V µA ns ns V Data Sheet AD8133 ABSOLUTE MAXIMUM RATINGS quiescent current (IS). The load current consists of differential and common-mode currents flowing to the loads, as well as currents flowing through the internal differential and commonmode feedback loops. The internal resistor tap used in the common-mode feedback loop places a 4 kΩ differential load on the output. RMS output voltages should be considered when dealing with ac signals. Parameter Supply Voltage All VOCM Power Dissipation Input Common-Mode Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 12 V ±VS See Figure 3 ±VS −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Airflow reduces θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane in order to achieve the specified θJA. Figure 3 shows the maximum safe power dissipation in the package versus ambient temperature for the 24-lead LFCSP (70°C/W) package on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a PCB plane. θJA values are approximations. 4.0 θJA is specified for the worst-case conditions, i.e., θJA is specified for the device soldered in a circuit board in still air. 3.5 MAXIMUM POWER DISSIPATION (W) THERMAL RESISTANCE Table 4. Thermal Resistance with the Underside Pad Connected to the Plane Package Type/PCB Type 24-Lead LFCSP/4-Layer θJA 70 Unit °C/W Maximum Power Dissipation The maximum safe power dissipation in the AD8133 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8133. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in the silicon devices potentially causing failure. 3.0 2.5 2.0 1.5 LFCSP 1.0 04769-0-024 Table 3. 0.5 0 –40 –20 0 20 40 AMBIENT TEMPERATURE (°C) 60 80 Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the Rev. A | Page 5 of 17 AD8133 Data Sheet 20 VOCMA 19 VOCMB 24 VS+ 23 –IN B 22 +IN B 21 VS– PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 18 VOCMC OPD 1 VS– 2 –IN A 3 AD8133 +IN A 4 VS– 5 TOP VIEW 17 VS+ 16 –IN C 15 +IN C 14 VS– –OUT A 6 NOTES 1. EXPOSED PAD. THE EXPOSED PADDLE MUST BE SOLDERED TO A PAD ON TOP OF THE BOARD THAT IS CONNECTED TO AN INNER PLANE WITH SEVERAL THERMAL VIAS. 04769-0-101 VS+ 11 +OUT C 12 –OUT B 10 +OUT B 9 VS+ 8 +OUT A 7 13 –OUT C Figure 4. 24-Lead LFCSP Table 5. Pin Function Descriptions Pin No. 1 2, 5, 14, 21 3 4 6 7 8, 11, 17, 24 9 10 12 13 15 16 18 19 20 22 23 Mnemonic OPD VS− −IN A +IN A −OUT A +OUT A VS+ +OUT B −OUT B +OUT C −OUT C +IN C −IN C VOCMC VOCMB VOCMA +IN B −IN B EPAD Description Output Pull-Down. Negative Power Supply Voltage. Inverting Input, Amplifier A. Noninverting Input, Amplifier A. Negative Output, Amplifier A. Positive Output, Amplifier A. Positive Power Supply Voltage. Positive Output, Amplifier B. Negative Output, Amplifier B. Positive Output, Amplifier C. Negative Output, Amplifier C. Noninverting Input, Amplifier C. Inverting Input, Amplifier C. Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier C. Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier B. Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier A. Noninverting Input, Amplifier B. Inverting Input, Amplifier B. Exposed Pad. The exposed paddle must be soldered to a pad on top of the board that is connected to an inner plane with several thermal vias. Rev. A | Page 6 of 17 Data Sheet AD8133 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, RL, dm = 200 Ω, VS = ±5 V, TA = 25°C, VOCMA = VOCMB = VOCMC = 0 V. Refer to the basic test circuit in Figure 33 for the definition of terms. 9 9 –40°C 85°C 25°C 25°C 6 6 –40°C GAIN (dB) 3 0 04769-0-010 0 VOUT, dm = 200mV p-p –3 1 10 100 FREQUENCY (MHz) VOUT, dm = 2V p-p –3 1 1000 Figure 5. Small Signal Frequency Response at Various Temperatures 1000 10 100 FREQUENCY (MHz) Figure 8. Large Signal Frequency Response at Various Temperatures 6.9 9 VS = ±5V 6.8 6.7 6 VOUT, dm = 2V p-p 6.6 VS = +5V 3 GAIN (dB) GAIN (dB) 3 04769-0-011 GAIN (dB) 85°C 0 6.5 VOUT, dm = 200mV p-p 6.4 6.3 6.2 04769-0-008 VOUT, dm = 2V p-p –6 1 10 100 FREQUENCY (MHz) 04769-0-009 6.1 –3 6.0 5.9 1 1000 Figure 6. Large Signal Frequency Response for Various Power Supplies –30 100 1000 Figure 9. 0.1 dB Flatness Response –30 VS = +5V VOUT, dm = 2V p-p –40 10 FREQUENCY (MHz) VS = +5V VOUT, dm = 2V p-p –40 –50 –60 DISTORTION (dBc) DISTORTION (dBc) –50 –70 –80 RL, dm = 200Ω –90 –100 –60 RL, dm = 200Ω –70 –80 RL, dm = 1000Ω RL, dm = 1000Ω –110 1 10 FREQUENCY (MHz) –100 0.1 100 Figure 7. Second Harmonic Distortion at VS = 5 V at Various Loads 04769-0-028 –130 0.1 –90 04769-0-027 –120 1 10 FREQUENCY (MHz) 100 Figure 10. Third Harmonic Distortion at VS = 5 V at Various Loads Rev. A | Page 7 of 17 AD8133 Data Sheet –30 VOUT, dm = 2V p-p VOUT, dm = 2V p-p –40 –40 –50 –50 DISTORTION (dBc) –60 RL, dm = 200Ω –70 –80 –90 RL, dm = 1000Ω RL, dm = 200Ω –60 –70 –80 –90 –100 RL, dm = 1000Ω –100 –110 –120 0.1 1 –120 –130 0.1 100 10 FREQUENCY (MHz) 04769-0-030 04769-0-029 –110 Figure 11. Second Harmonic Distortion at VS = ±5 V at Various Loads 1 Figure 14. Third Harmonic Distortion at VS = ±5 V at Various Loads 200 VOUT, dm = 200mV p-p VS = +5V 1.0 VS = ±5V VS = ±5V 0.5 VO, dm (V) 50 VO, dm (mV) VOUT, dm = 2V p-p VS = +5V 100 0 0 –0.5 –50 5ns/DIV –200 04769-0-007 –1.0 –100 5ns/DIV Figure 15. Large Signal Transient Response for Various Power Supply Voltages Figure 12. Small Signal Transient Response for Various Power Supply Voltages 10 100 10 FREQUENCY (MHz) 04769-0-006 DISTORTION (dBc) –30 2 × VIN, dm VIN, dm 250mV/DIV 8 6 VOUT, dm +0.1% 2 0 SETTLING TIME ERROR 2mV/DIV –2 –0.1% –6 –8 100ns/DIV –10 10ns/DIV t=0 Figure 13. Overdrive Recovery Figure 16. Settling Time (0.1%) Rev. A | Page 8 of 17 04769-0-016 –4 04769-0-018 VOLTAGE (V) 4 Data Sheet AD8133 –30 RL, dm = ∞ SINGLE-ENDED OUTPUT VOUT, dm/VIN, dm WITH 0 –1 –3 +5 –4 –5 100ns/DIV 04769-0-017 OUTPUT PULL-DOWN –2 VON –5 –32 OUTPUT PULL-DOWN –34 –36 –38 VI, dm = 2V p-p –40 –42 –44 –46 –48 –50 0.1 t=0 Figure 17. Output Pull-Down Response 10 FREQUENCY (MHz) 1000 100 0 ∆VOUT, dm = 2V p-p ∆VOUT, cm/∆VOUT, dm 10 10 04769-0-023 100 100 1k 10k 100k FREQUENCY (Hz) 1M 10M –20 VS = ±5V –30 –40 –50 VS = +5V –60 –70 –80 04769-0-034 OUTPUT BALANCE ERROR (dB) –10 –90 –100 100M 1 10 FREQUENCY (MHz) Figure 18. Output-Referred Voltage Noise vs. Frequency 100 500 Figure 21. Output Balance vs. Frequency –30 10 ∆VIN, cm = 200mV p-p 0 ∆VOUT, dm/∆VS –35 –10 –20 –40 PSRR– PSRR (dB) –30 –45 ∆VOUT, dm/∆VIN, cm –50 –40 PSRR– –50 –60 –55 –70 –80 04769-0-020 –60 –65 1 10 100 FREQUENCY (MHz) 04769-0-022 NOISE (nV√Hz) 1 Figure 20. Output Pull-Down Isolation vs. Frequency 1000 COMMON-MODE REJECTION (dB) 04769-0-021 OPD INPUT VOLTAGE (V) 1 OUTPUT PULL-DOWN ISOLATION (dB) SINGLE-ENDED OUTPUT VOLTAGE (V) 2 –90 –100 0.1 1000 Figure 19. Common-Mode Rejection Ratio vs. Frequency 1 10 FREQUENCY (MHz) 100 Figure 22. Power Supply Rejection Ratio vs. Frequency Rev. A | Page 9 of 17 1000 AD8133 Data Sheet –40 30 AMPLIFIER A TO VIN, dm = 200mV p-p AMPLIFIER B –50 ∆VOUT, dm B/∆VIN, dm A VIN, dm = 2V p-p –80 –90 04769-0-015 –100 –110 27 26 VS = +5V 25 24 23 22 21 20 –40 –30 1000 10 100 FREQUENCY (MHz) 1 28 04769-0-025 POWER SUPPLY CURRENT (mA) ISOLATION (dB) –60 –70 VS = ±5V 29 Figure 23. Amplifier-to-Amplifier Isolation vs. Frequency –10 10 30 TEMPERATURE (°C) 50 70 85 Figure 26. Power Supply Current vs. Temperature 1.5 –20 ∆VOCM = 200mV p-p VS = +5V –30 1.0 –40 0.5 VOUT, cm = 2V p-p ∆VOUT, dm/∆VOCM 0 –60 –0.5 –70 –1.0 –80 10 100 FREQUENCY (MHz) 1 5ns/DIV –1.5 1000 Figure 27. VOCM Large Signal Transient Response for Various Power Supply Voltages Figure 24 VOCM CMRR vs. Frequency 1.0 2 ∆VOUT, cm/∆VOCM 1 0.8 VS = ±5V 0 VOCM BIAS CURRENT (mA) 0.6 –1 –2 VS = +5V –3 –4 –5 –6 –7 0.4 0.2 0 –0.2 –0.4 VOUT, cm = 100mV p-p VOUT, cm TAKEN SINGLE ENDED –9 –10 1 10 100 FREQUENCY (MHz) 04769-0-012 –0.6 –8 04769-0-013 GAIN (dB) 04769-0-005 VOCM (V) –50 04769-0-019 VOCM CMRR (dB) VS = ±5V –0.8 –1.0 –5 1000 Figure 25. VOCM Frequency Response for Various Power Supply Voltages –4 –3 –2 –1 0 1 2 VOCM INPUT VOLTAGE 3 Figure 28. VOCM Bias Current vs. VOCM Input Voltage Rev. A | Page 10 of 17 4 5 AD8133 4 0.5 3 VS = +5V VS = ±5V –0.5 2 –1.5 1 –2.5 0 –3.5 –4.5 100 1000 LOAD (Ω) 5.0 2.0 4.5 VS = +5V 4.0 1.5 –5 15 35 TEMPERATURE (°C) 55 75 3.5 85 ±5V SINGLE-ENDED OUTPUT VOLTAGE (V) 2.5 100 1 10 FREQUENCY (MHz) 1000 –1.0 04769-0-032 VS = ±5V 3.0 0.1 Figure 31. Single-Ended Output Impedance Magnitude vs. Frequency +5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) ±5V SINGLE-ENDED OUTPUT VOLTAGE (V) 3.5 VS = ±5V VS = +5V 10000 4.0 –25 1 0.1 0.01 Figure 29. Output Saturation Voltage vs. Single-Ended Output Load 1.0 –40 10 04769-0-026 1.5 1.5 –1.5 1.0 VS = +5V –2.0 0.5 –2.5 0 VS = ±5V –3.0 –3.5 –40 –25 –5 15 35 TEMPERATURE (°C) 55 75 85 Figure 32. Negative Output Saturation Voltage vs. Temperature Figure 30. Positive Output Saturation Voltage vs. Temperature Rev. A | Page 11 of 17 04769-0-033 5 +5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) 2.5 OUTPUT IMPEDANCE (Ω) 3.5 100 04769-0-031 4.5 +5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) ±5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) Data Sheet AD8133 Data Sheet TEST CIRCUIT +5V VS+ AD8133 50 750 53.6 VTEST 1.5k – + RL, dm 200 VOUT, dm VOCM – 53.6 + 50 750 1.5k MIDSUPPLY VS– –5V Figure 33. Basic Test Circuit Rev. A | Page 12 of 17 0.1F ON ALL VS– PINS 04769-0-035 TEST SIGNAL SOURCE 0.1F ON ALL VS+ PINS Data Sheet AD8133 THEORY OF OPERATION Each differential driver in the AD8133 differs from a conventional op amp in that it has two outputs whose voltages move in opposite directions. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The AD8133 drivers make it easy to perform single-ended-to-differential conversion, commonmode level shifting, and amplification of differential signals. Previous differential drivers, both discrete and integrated designs, have been based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. When these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. Achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks. DC common-mode level shifting has also been difficult with previous differential drivers. Level shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. Sometimes, the third amplifier has also been used to attempt to correct an inherently unbalanced circuit. Excellent performance over a wide frequency range has proven difficult with this approach. Each of the AD8133 drivers uses two feedback loops to separately control the differential and common-mode output voltages. The differential feedback, set by the internal resistors, controls only the differential output voltage. The internal common-mode feedback loop controls only the common-mode output voltage. This architecture makes it easy to arbitrarily set the output common-mode level by simply applying a voltage to the VOCM input. The output common-mode voltage is forced, by internal common-mode feedback, to equal the voltage applied to the VOCM input, without affecting the differential output voltage. The AD8133 architecture results in outputs that are highly balanced over a wide frequency range without requiring external components or adjustments. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude that are exactly 180° apart in phase. Common-mode voltage refers to the average of two node voltages with respect to a common reference. The output common-mode voltage is defined as VOUT , cm = (VOP + VON ) 2 Output Balance Output balance is a measure of how well the differential output signals are matched in amplitude and how close they are to exactly 180° apart in phase. Balance is most easily determined by placing a well-matched resistor divider between the differential output voltage nodes and comparing the magnitude of the signal at the divider’s midpoint with the magnitude of the differential signal. By this definition, output balance error is the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differentialmode voltage in response to a differential input signal. Output Balance Error = ANALYZING AN APPLICATION CIRCUIT The AD8133 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages to minimize the differential and common-mode input error voltages. The differential input error voltage is defined as the voltage between the differential inputs labeled VAP and VAN in Figure 34. For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed. CLOSED-LOOP GAIN The differential mode gain of the circuit in Figure 34 can be described by the following equation. VOUT,dm R = F =2 VIN,dm RG where RF = 1.5 kΩ and RG = 750 Ω nominally. Differential Voltage Differential voltage refers to the difference between two node voltages that are balanced with respect to each other. For example, in Figure 34 the output differential voltage (or equivalently output differential mode voltage) is defined as ( ) Rev. A | Page 13 of 17 VIP + VIN, dm VOCM VIN – RG VAP RL, dm RG VAN RF Figure 34. VON VOUT, dm VOP 04769-0-003 RF DEFINITION OF TERMS VOUT , dm = VOP − VON ∆VOUT , cm ∆VOUT , dm AD8133 Data Sheet The effective input impedance of a circuit such as that in Figure 34 at VIP and VIN depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, the differential input impedance, RIN, dm, between the inputs VIP and VIN is simply RIN, dm 2 RG 1.5 kΩ In the case of a single-ended input signal (for example, if VIN is grounded and the input signal is applied to VIP), the input impedance becomes: RIN,dm RG 1.125 kΩ RF 1 2 R R F G The circuit’s input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG. DRIVING A CAPACITIVE LOAD A purely capacitive load can react with the output impedance of the AD8133 to reduce phase margin, resulting in high frequency ringing in the pulse response. The best way to minimize this effect is to place a small resistor in series with each of the amplifier’s outputs to buffer the load capacitance. OUTPUT PULL-DOWN (OPD) The AD8133 has an OPD pin that when pulled high significantly reduces the power consumed while simultaneously pulling the outputs to within less than 1 V of VS− when used with series diodes (see the Applications section). The equivalent schematic of the output pull-down circuit is shown in Figure 35. (The ESD diodes shown in Figure 35 are for ESD protection and are distinct from the series diodes used with the output pulldown feature.) See Figure 17 and Figure 20 for the output pull-down transient and isolation performance plots. The threshold levels for the OPD pin are referenced to the positive power supply voltage and are presented in the Specifications tables. When the OPD pin is pulled high, the AD8133 enters the output low disable state. VS+ VCC INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-SUPPLY APPLICATIONS The inputs of the AD8133 are designed to facilitate levelshifting of ground referenced input signals on a single power supply. For a single-ended input, this would imply, for example, that the voltage at VIN in Figure 34 would be 0 V when the amplifier’s negative power supply voltage was also set to 0 V. It is important to ensure that the common-mode voltage at the amplifier inputs, VAP and VAN, stays within its specified range. Since voltages VAP and VAN are driven to be essentially equal by negative feedback, the amplifier’s input common-mode voltage can be expressed as a single term, VACM. VACM can be calculated as follows VACM VOCM 2VICM 3 where VICM is the common-mode voltage of the input signal, VIP VIN i.e., VICM . 2 ESD DIODE VOUT PULLDOWN (OUTPUT IS PULLED DOWN WHEN SWITCH IS CLOSED) ESD DIODE VS– 04769-0-004 CALCULATING AN APPLICATION CIRCUIT’S INPUT IMPEDANCE Figure 35. Output Pull-Down Equivalent Circuit OUTPUT COMMON-MODE CONTROL The AD8133 allows the user to control each of the three common-mode output levels independently through the three VOCM input pins. The VOCM pins pass a signal to the commonmode output level of each of their respective amplifiers with 330 MHz of small signal bandwidth and an internally fixed gain of one. In this way, additional control and communication signals can be embedded on the common-mode levels as the user sees fit. With no external circuitry, the level at the VOCM input of each amplifier defaults to approximately midsupply. An internal resistive divider with an impedance of approximately 100 kΩ sets this level. To limit common-mode noise in dc commonmode applications, external bypass capacitors should be connected from each of the VOCM input pins to ground. Rev. A | Page 14 of 17 Data Sheet AD8133 APPLICATIONS DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5 UTP CABLE The foremost application of the AD8133 is driving RGB video signals over UTP cable in KVM networks. Single-ended video signals are easily converted to differential signals for transmission over the cable, and the internally fixed gain of 2 automatically compensates for the losses incurred by the source and load terminations. The common topologies used in KVM networks, such as daisy-chained, star, and point-to-point, are supported by the AD8133. Figure 36 shows the AD8133 in a triple single-ended-to-differential application when driven from a 75 Ω source, which is typical of how RGB video is driven over an UTP cable. In applications that use the OPD feature, the Schottky diodes are placed in series with each of the 49.9 Ω resistors in the outputs. +5V 0.1F ON ALL VS+ PINS VS+ AD8133 1.5k 75 750 80.6 +2.5V VIDEO SOURCE A 750 49.9 VOCM A 49.9 – OUT A + 38.3 1.5k 1.5k 75 750 80.6 +2.5V VIDEO SOURCE B 750 49.9 VOCM B 49.9 – OUT B + 38.3 1.5k 1.5k 75 750 80.6 +2.5V VIDEO SOURCE C 750 VOCM C 49.9 – OUT C + 38.3 1.5k OPD VS– Figure 36. AD8133 in Single-Ended-to-Differential Application Rev. A | Page 15 of 17 04769-0-002 OUTPUT PULLDOWN 49.9 AD8133 Data Sheet OUTPUT PULL-DOWN The output pull-down feature, when used in conjunction with series Schottky diodes, offers a convenient means to connect a number of AD8133 outputs together to form a video network. The OPD pin is a binary input that controls the state of the AD8133 outputs. Its binary input level is referenced to the most positive power supply (see the Specifications tables for the logic levels). When the OPD input is driven to its low state, the AD8133 output is enabled and operates in its normal fashion. In this state, the VOCM input can be used to provide a positive bias on the series diodes, allowing the AD8133 to transmit signals over the network. When the OPD input is driven to its high state, the outputs of the AD8133 are forced to a low voltage, irrespective of the level on the VOCM input, reverse-biasing the series diodes and thus presenting high impedance to the network. This feature allows a three-state output to be realized that maintains its high impedance state even when the AD8133 is not powered. This condition can occur in KVM networks where the AD8133s do not all reside in the same module, and some modules in the network are not powered. It is recommended that the output pull-down feature only be used in conjunction with series diodes in such a way as to ensure that the diodes are reverse-biased when the output pulldown feature is asserted, since some loading conditions can prevent the output voltage from being pulled all the way down. KVM NETWORKS In daisy-chained KVM networks, the drivers are distributed along one cable and a triple receiver is located at one end. Schottky diodes in series with the driver outputs are biased such that the one driver that is transmitting video signals has its diodes forward-biased and the disabled drivers have their diodes reverse-biased. The output common-mode voltage, set by the VOCM input, supplies the forward-biased voltage. When the output pull-down feature is asserted, the differential outputs are pulled to a low voltage, reverse-biasing the diodes. In star networks, all cables radiate out from a central hub, which contains a triple receiver. The series diodes are all located at the receiver in the star network. Only one ray of the star is transmitting at a given time, and all others are isolated by the reverse-biased diodes. Diode biasing is controlled in the same way as in the daisy-chained network. In the daisy-chained and star networks that use diodes for isolation, return paths are required for the common-mode currents that flow through the series diodes. A common-mode tap can be implemented at each receiver by splitting the100 Ω termination resistor into two 50 Ω resistors in series. The diode currents are routed from the tap between the 50 Ω resistors back to the respective transmitters over one of the wires of the fourth twisted pair in the UTP cable. Series resistors in the common-mode return path are generally required to set the desired diode current. In point-to-point networks, there is one transmitter and one receiver per cable, and the switching is generally implemented with a crosspoint switch. In this case, there is no need to use diodes or the output pull-down feature. Diode and crosspoint switching are by no means the only type of switching that can be used with the AD8133. Many other types of mechanical, electromechanical, and electronic switches can be used. LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS Standard high speed PCB layout practices should be adhered to when designing with the AD8133. A solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. AMPLIFIER-TO-AMPLIFIER ISOLATION The least amount of isolation between the three amplifiers exists between Amplifier A and Amplifier B. This is therefore viewed as the worst-case isolation and is what is reflected in the Specifications tables and Typical Performance Characteristics. Refer to the Basic Test Circuit shown in Figure 33 for the test conditions. EXPOSED PADDLE (EP) The LFCSP-24 package has an exposed paddle on the underside of its body. In order to achieve the specified thermal resistance, it must have a good thermal connection to one of the PCB planes. The exposed paddle must be soldered to a pad on the top of the board that is connected to an inner plane with several thermal vias. Rev. A | Page 16 of 17 Data Sheet AD8133 OUTLINE DIMENSIONS 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 2.20 2.10 SQ 2.00 6 7 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. 06-11-2012-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8133ACPZ-R2 AD8133ACPZ-REEL AD8133ACPZ-REEL7 1 Temperature Package −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead LFCSP 24-Lead LFCSP 24-Lead LFCSP Z = RoHS Compliant Part. ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04769-0-3/16(A) Rev. A | Page 17 of 17 Package Outline CP-24-10 CP-24-10 CP-24-10