DS8237CD 06

®
RT8237C/D
High Efficiency Single Synchronous Buck PWM Controller
General Description
Features
The RT8237C/D PWM controller provides high efficiency,
excellent transient response, and high DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers.

Wide Input Voltage Range : 4.5V to 26V

Output Voltage Range : 0.7V to 3.3V
Built-in 0.5% 0.7V Reference Voltage
Quick Load-Step Response within 100ns
4700ppm/°°C Programmable Current Limit by Low
Side RDS(ON) Sensing
4 Selectable Frequency Setting
Soft-Start Control
Drives Large Synchronous-Rectifier FETs
Integrated Boot Switch
Built-in OVP/OCP/UVP
Thermal Shutdown
Power Good Indicator
RoHS Compliant and Halogen Free






Applications




Notebook Computers
CPU Core Supply
Chipset/RAM Supply as Low as 0.7V
Generic DC/DC Power Regulator
Pin Configurations
(TOP VIEW)
PGOOD
CS
EN
FB
RF
C : WDFN-10L 3x3
D : WQFN-12L 2x2
Note :
Richtek products are :

RoHS compliant and compatible with the current require-

Suitable for use in SnPb or Pb-free soldering processes.
ments of IPC/JEDEC J-STD-020.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8237C/D-06
February 2014
10
9
4
5
8
7
6
11
BOOT
UGATE
PHASE
VCC
LGATE
WDFN-10L 3x3
Package Type
QW : WDFN-10L 3x3 (W-Type)
QW : WQFN-12L 2x2 (W-Type)
RT8237C
LGATE
1
VCC
PHASE
2
RF
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
1
2
3
12
11
10
GND
13
3
4
5
6
PGOOD
Pin 1 Orientation
(2) : Quadrant 2, Follow EIA-481-D

GND
(2)

NC
RT8237

GND
Ordering Information

BOOT
The RT8237C/D achieves high efficiency at a reduced cost
by eliminating the current sense resistor found in
traditional current mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFETs and enter diode emulation mode at
light load condition. The buck conversion allows this device
to directly step down high voltage batteries at the highest
possible efficiency. The pre-set frequency selections
minimize design effort required for new designs. The
RT8237C/D is intended for CPU core, chipset, DRAM, or
other low voltage supplies as low as 0.7V. The RT8237C
is available in a WDFN-10L 3x3 package, The RT8237D is
available in a WQFN-12L 2x2 package.
UGATE
The constant on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
a relatively constant switching frequency.

9
FB
8
EN
CS
7
WQFN-12L 2x2
RT8237D
is a registered trademark of Richtek Technology Corporation.
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1
RT8237C/D
Marking Information
RT8237CZQW
RT8237DZQW
Z3 : Product Code
72 : Product Code
YMDNN : Date Code
Z3 YM
DNN
W : Date Code
72W
Typical Application Circuit
VCC
R1
0
RT8237C/D
VCC
BOOT
C1
1µF
16V
R5
100k
CBOOT
0.1µF
50V
RBOOT
0
RUGATE
UGATE
VIN
C2
10µF x 3
50V
0
PGOOD
VOUT
1.05V
LOUT
0.45µH
Chip Enable
EN
PHASE
LGATE
RF
RRF
470k
RLGATE
0
C3*
CS
ROC_SET
30k
RFB1
5.1k
R3*
COUT
330µF x 2
16V
C4*
C5*
FB
GND
C6
10µF x 2
16V
R2*
RFB2
10k
* : Optional
Functional Pin Description
Pin No.
Pin Name
Pin Function
RT8237C
RT8237D
1
6
PGOOD
2
7
CS
3
8
EN
4
9
FB
5
10
RF
6
1
LGATE
Gate Drive Output for Low Side External MOSFET.
7
2
VCC
Control Voltage Input. This pin provides the power for the buck
controller, the low side driver and the bootstrap circuit for high side
driver. Bypass to GND with a 1F ceramic capacitor.
Open Drain Power Good Indicator. High impedance indicates
power is good.
Current Limit Threshold Setting Input. Connect a setting resistor to
GND and the current limit threshold is equal to 1/8 of the voltage
at this pin.
PWM Enable. Pull low to GND to disable the PWM.
VOUT Feedback Input. Connect FB to a resistor voltage divider
from VOUT to GND to adjust the output from 0.7V to 3.3V
Switching Frequency Selection. Connect a resistance to select
switching frequency as shown in Electrical Characteristics.
The switching frequency is detected and latched after startup. This
pin also controls Diode emulation mode or forced CCM selection.
Pull down to GND with resistor : Diode Emulation Mode.
Connect to PGOOD with resistor : forced CCM after PGOOD
becomes high.
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is a registered trademark of Richtek Technology Corporation.
DS8237C/D-06
February 2014
RT8237C/D
Pin No.
Pin Name
RT8237C
RT8237D
8
3
PHASE
9
4
UGATE
10
5
BOOT
---
11
NC
11
12, 13
(Exposed Pad) (Exposed Pad)
Pin Function
External Inductor Connection Pin for PWM Converter. It behaves
as the current sense comparator input for low side MOSFET
RDS(ON) sensing and reference voltage for on time generation.
Gate Drive Output for High Side External MOSFET.
Supply Input for High Side Driver. Connect through a capacitor to
the floating node (PHASE) pin.
No Internal Connection.
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
GND
Function Block Diagram
VCC
TRIG
On-time
Compute
1-SHOT
RF
PHASE
BOOT
R
- COMP
S
+
FB
70%
VREF
+
OV
Latch
S1
Q
UV
Latch
S1
Q
+
PWM
DRV
UGATE
PHASE
VREF
125%
VREF
Q
Min. tOFF
Q
TRIG
1-SHOT
DRV
LGATE
GND
-
DEM/FCCM
125% VREF
-
PGOOD
+
VCC
POR
SS
Timer
EN
-
90% VREF
+
Thermal
Shutdown
+
X(1/8)
+
10µA
X(-1/8)
CS
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8237C/D-06
February 2014
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3
RT8237C/D
Absolute Maximum Ratings
(Note 1)
VCC, FB, PGOOD, EN, CS, RF to GND ---------------------------------------------------------------------------BOOT to PHASE --------------------------------------------------------------------------------------------------------- PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------------------<20ns ----------------------------------------------------------------------------------------------------------------------- UGATE to PHASE -------------------------------------------------------------------------------------------------------DC ----------------------------------------------------------------------------------------------------------------------------<20ns ----------------------------------------------------------------------------------------------------------------------- LGATE to GND ------------------------------------------------------------------------------------------------------------DC ----------------------------------------------------------------------------------------------------------------------------<20ns ----------------------------------------------------------------------------------------------------------------------- Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------WQFN-12L 2x2 ----------------------------------------------------------------------------------------------------------- Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------WQFN-12L 2x2, θJA ------------------------------------------------------------------------------------------------------ Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------ Junction Temperature ---------------------------------------------------------------------------------------------------- Storage Temperature Range ------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------

Recommended Operating Conditions




−0.3V to 6V
−0.3V to 6V
−0.3V to 32V
−8V to 38V
−0.3V to 6V
−0.3V to 6V
−5V to 7.5V
−0.3V to 6V
−0.3V to 6V
−2.5V to 7.5V
0.952W
0.606W
105°C/W
8.2°C/W
165°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
(Note 4)
Input Voltage, VIN ---------------------------------------------------------------------------------------------------------Control Voltage, VCC -----------------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------
4.5V to 26V
4.5V to 5.5V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Power Supply
VCC Quiescent Supply
Current
IQ
FB forced above the regulation
point, V EN = 5V,
--
500
1250
A
VCC Shutdown Current
ISHDN
VCC current, VEN = 0V
--
--
1
A
CS pull to GND
--
--
1
A
0.7005
0.704
0.7075
0.697
0.704
0.711
1
0.01
1
CS Shutdown Current
FB Error Comparator
Threshold
FB Input Bias Current
VREF
DEM
DEM, TA = 40 to 85C
VFB = 0.735V
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(Note 5)
V
A
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DS8237C/D-06
February 2014
RT8237C/D
Parameter
Symbol
Test Conditions
VOUT Voltage Range
Switching Frequency
fSW
Min
Typ
Max
Unit
0.7
--
3.3
V
RRF = 470k
(Note 6)
--
290
--
RRF = 200k
(Note 6)
--
340
--
RRF = 100k
(Note 6)
--
380
--
--
430
--
250
400
550
ns
9
10
11
A
--
4700
--
ppm/C
DEM
10
--
5
mV
GND PHASE, VCS = 2.4V
280
300
320
GND PHASE, VCS = 1.6V
185
200
215
GND PHASE, VCS = 0.4V
40
50
60
PHASE GND, VCS = 2.4V
--
300
--
PHASE GND, VCS = 1.6V
--
200
--
PHASE GND, VCS = 0.4V
--
50
--
65
70
75
%
120
125
130
%
--
5
--
s
3.7
3.9
4.1
V
RRF = 39k
(Note 6)
Minimum Off-Time
kHz
Current Sensing
CS Source Current
ICS
CS Source Current TC
Zero Crossing Threshold
Current Limit Threshold
VLIMIT
Negative Current Limit
Threshold
mV
mV
Protection Function
With respect to error
comparator threshold
With respect to error
comparator threshold
Output UV Threshold
OVP Threshold
OV Fault Delay
FB forced above OV threshold
VCC Under Voltage Lockout
Threshold
UVLO
Falling edge,
hysteresis = 100mV, PW M
disabled below this level
VOUT Soft-Start
From EN = high to VOUT = 95%
--
1300
--
s
UV Blank Time
From EN signal going high
--
3
--
ms
--
150
--
C
Thermal Shutdown
TSD
Driver On Resistance
UGATE Drive Source
RUGATEsr
BOOT  PHASE forced to 5V
--
1.8
3.6

UGATE Drive Sink
RUGATEsk
BOOT PHASE forced to 5V
--
1.2
2.4

LGATE Drive Source
RLGATEsr
LGATE, High State
--
1.8
3.6

LGATE Drive Sink
RLGATEsk
LGATE, Low State
--
0.8
1.6

LGATE Rising (VPHASE = 1.5V)
--
30
--
UGATE Rising
--
30
--
VCC to BOOT, 10mA
--
--
80
Dead Time
Internal Boost Charging Switch
On Resistance
EN Threshold
EN Input
Threshold Voltage
Logic-High
VIH
1.8
--
--
Logic-Low
VIL
--
--
0.5
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8237C/D-06
February 2014
ns

V
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5
RT8237C/D
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
0.5
V
1.8
--
--
V
87
90
93
%
120
125
130
%
--
2.5
--
s
Mode Decision
VRF Threshold for DEM
VRF Threshold for FCCM
PGOOD
Trip Threshold (falling,
leaving PGOOD)
Trip Threshold (rising,
leaving PGOOD)
Fault Propagation Delay
Measured at FB, with respect to
reference, Hysteresis = 3%
Measured at FB, with respect to
reference, Hysteresis = 3%
Falling Edge, FB forced below
PGOOD trip threshold
Output Low Voltage
ISINK = 1mA
--
--
0.4
V
Leakage Current
High State, forced to 5V
--
--
1
A
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a low effective thermal conductivity single-layer test board per JEDEC 51-3. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design. Not production tested.
Note 6. Not production tested. Test condition is VIN = 8V, VOUT = 1.1V, IOUT = 10A using application circuit.
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DS8237C/D-06
February 2014
RT8237C/D
Typical Operating Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
100
100
90
90
DEM
DEM
80
70
Efficiency (%)
Efficiency (%)
80
60
50
40
30
70
60
50
40
30
CCM
20
CCM
20
10
10
VIN = 8V, VOUT = 1.05V, RRF = 470kΩ
0
0.001
0.01
0.1
1
10
VIN = 12V, VOUT = 1.05V, RRF = 470kΩ
0
0.001
100
0.01
Load Current (A)
Efficiency vs. Load Current
10
100
1000
80
Switching Frequency (kHz)1
90
Efficiency (%)
1
Switching Frequency vs. Load Current
100
DEM
70
60
50
40
30
CCM
20
10
CCM
100
10
DEM
1
VIN = 20V, VOUT = 1.05V, RRF = 470kΩ
0
0.001
0.01
0.1
1
10
VIN = 12V, VOUT = 1.05V, RRF = 470kΩ
0.1
0.001
100
0.01
Load Current (A)
Switching Frequency vs. Load Current
10
100
Switching Frequency vs. Load Current
Switching Frequency (kHz)1
CCM
10
DEM
1
CCM
100
10
DEM
1
VIN = 12V, VOUT = 1.05V, RRF = 200kΩ
0.01
0.1
1
10
Load Current (A)
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DS8237C/D-06
1
1000
100
0.1
0.001
0.1
Load Current (A)
1000
Switching Frequency (kHz)1
0.1
Load Current (A)
February 2014
100
VIN = 12V, VOUT = 1.05V, RRF = 100kΩ
0.1
0.001
0.01
0.1
1
10
100
Load Current (A)
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RT8237C/D
Switching Frequency vs. Load Current
Load Regulation vs. Temperature
Switching Frequency (kHz)1
1000
1.0
CCM
0.8
Load Regulation (%)
CCM
100
10
DEM
1
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
VIN = 12V, VOUT = 1.05V, RRF = 39kΩ
0.1
0.001
VIN = 12V, VOUT = 1.05V, IOUT = 10A, RRF = 470kΩ
-1.0
0.01
0.1
1
10
100
-50
-25
0
Load Current (A)
100
125
Switching Frequency vs. Input Voltage
DEM
Switching Frequency (kHz)1
Line Regulation (%)
75
500
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
50
Temperature (C)
Line Regulation vs. Temperature
1.0
25
VIN = 12V, VOUT = 1.05V, RRF = 470kΩ, No Load
475
RRF = 39k
450
425
RRF = 100k
400
375
RRF = 200k
350
325
RRF = 470k
300
275
250
225
IOUT = 10A
200
-1.0
-50
-25
0
25
50
75
100
4
125
6
8
10
12
14
16
18
20
22
Temperature (C)
Input Voltage (V)
CS Source Current vs. Temperature
Load Transient Response
24
26
20
CS Source Current (µA)
18
VOUT
(50mV/Div)
16
14
12
IOUT
(10A/Div)
UGATE
(20V/Div)
10
8
6
4
2
VCC = 5V
0
-50
-25
0
25
50
75
100
125
LGATE
(5V/Div)
VIN = 12V, IOUT = 0A to 20A, VOUT = 1.05V
Time (40μs/Div)
Temperature (C)
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February 2014
RT8237C/D
OVP
UVP
VOUT
(1V/Div)
VOUT
(500mV/Div)
LGATE
(5V/Div)
PGOOD
(5V/Div)
UGATE
(20V/Div)
PGOOD
(5V/Div)
LGATE
(5V/Div)
DEM, VIN = 12V, No Load
VIN = 12V, VOUT = 1.05V
Time (40μs/Div)
Time (40μs/Div)
Power On from EN
Power On from EN
EN
(5V/Div)
EN
(5V/Div)
VOUT
(500mV/Div)
PGOOD
(5V/Div)
VOUT
(500mV/Div)
PGOOD
(5V/Div)
UGATE
(10V/Div)
UGATE
(10V/Div)
DEM, VIN = 12V, No Load
Time (1ms/Div)
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DS8237C/D-06
February 2014
CCM, VIN = 12V, No Load
Time (1ms/Div)
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RT8237C/D
Application Information
The RT8237C/D PWM controller provides high efficiency,
excellent transient response, and high DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers. Richtek Mach
Response TM technology is specifically designed for
providing 100ns“instant-on” response to load steps while
maintaining a relatively constant operating frequency and
inductor operating point over a wide range of input voltages.
The topology circumvents the poor load transient timing
problems of fixed frequency current mode PWMs, while
avoiding the problems caused by widely varying switching
frequencies in conventional constant on-time and constant
off-time PWM schemes. The DRV TM mode PWM
modulator is specifically designed to have better noise
immunity for such a single output application.
The EN pin allows for power sequencing between the
controller bias voltage and another voltage rail. The
RT8237C/D remains in shutdown if the EN pin is lower
than 500mV. When the EN pin rises above the VEN trip
point, the RT8237C/D will begin a new initialization and
soft-start cycle.
PWM Operation
POR, UVLO and Soft-Start
TM
TM
The Mach Response DRV mode controller relies on
the output filter capacitor's effective series resistance
(ESR) to act as a current sense resistor, so the output
ripple voltage provides the PWM ramp signal. Referring to
the function block diagram, the synchronous UGATE driver
is turned on at the beginning of each cycle. After the
internal one-shot timer expires, the UGATE driver will be
turned off. The pulse width of this one shot is determined
by the converter's input voltage and the output voltage to
keep the frequency fairly constant over the input voltage
range. Another one-shot sets a minimum off-time (400ns
typ.).
On-Time Control (TON/MODE)
The on-time one-shot comparator has two inputs. One
input monitors the output voltage from the PHASE pin,
while the other input samples the input voltage and converts
it to a current. This input voltage proportional current is
used to charge an internal on-time capacitor. The on-time
is the time required for the voltage on this capacitor to
charge from zero volts to VOUT, thereby making the ontime of the high side switch directly proportional to output
voltage and inversely proportional to input voltage.
The on-time is given by :
tON = (VOUT / VIN) / fSW
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Table 1. RF Connection and Switching Frequency
RRF (k)
Switching Frequency (kHz)
470k
200k
100k
39k
290
340
380
430
Note : For DEM, connect RRF to GND; for CCM, connect
RRF to PGOOD.
Enable and Disable
Power-on reset (POR) occurs when VCC rises above
approximately 4.1V, in which the RT8237C/D resets the
fault latch and prepares the PWM for operation. Below
3.7V (min), the VCC Under Voltage Lockout (UVLO)
circuitry inhibits switching by keeping UGATE and LGATE
low. A built-in soft-start is used to prevent the power supply
input from surge currents after PWM is enabled. A ramping
up current limit threshold eliminates the VOUT folded-back
current during the soft-start duration.
Mode Selection (RF) Operation
To select the operation mode, connect a resistor from the
RF pin to either GND or PGOOD. When the resistor is
connected to GND, the controller operates in diode
emulation mode. When the resistor is connected to
PGOOD, the controller operates in CCM mode.
Diode-Emulation Mode (RRF Connected to GND)
In diode-emulation mode, the RT8237C/D automatically
reduces switching frequency at light load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly without increasing VOUT ripple or load
regulation. As the output current decreases from heavy
load condition, the inductor current is reduced and
eventually comes to the point where its valley touches
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DS8237C/D-06
February 2014
RT8237C/D
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulating the behavior of diodes, the low side MOSFET
allows only partial negative current to flow when the
inductor freewheeling current reaches negative. As the load
current is further decreased, it takes longer and longer to
discharge the output capacitor to the level that requires
the next “ON” cycle. The on-time is kept the same as
that in heavy load condition. On the contrary, when the
output current increases from light load to heavy load, the
switching frequency increases to the preset value as the
inductor current reaches the continuous condition. This
is shown in Figure 1. The transition load point to the light
load operation is calculated as follows :
 V  VOUT 
 tON
ILOAD  IN
2L
where tON is the on-time.
IL
Slope = (VIN -VOUT) / L
IL, PEAK
ILOAD = IL, PEAK / 2
0
Current Limit Setting (CS)
The RT8237C/D has a cycle-by-cycle current limiting
control. The current limit circuit employs a unique “valley”
current sensing algorithm. If the magnitude of the current
sense signal at PHASE is above the current limit
threshold, the PWM is not allowed to initiate a new cycle
(see Figure 2). In order to provide both good accuracy and
a cost effective solution, the RT8237C/D supports
temperature compensated MOSFET RDS(ON) sensing.
The CS pin of the RT8237C/D is a multiplexed pin for
PWM enable/disable control and current limit threshold
setting. Connect a setting resistor from this pin to GND
via an N-MOSFET. When the N-MOSFET is turned off, the
PWM is disabled. When the N-MOSFET is turned on, the
PWM is enabled and the current limit threshold is equal
to 1/8 of the voltage at this pin.
t
tON
Figure 1. Boundary Condition of CCM/DCM
The switching waveforms may appear noisy and
asynchronous when light loading causes diode-emulation
operation, but this is a normal operating condition that
results in high light load efficiency. Trade-offs in DEM noise
vs. light load efficiency is made by varying the inductor
value. Generally, low inductor values produce a broader
efficiency vs. load curve, while higher values result in higher
full load efficiency (assuming that the coil resistance
remains fixed) and less output voltage ripple. The
disadvantages for using higher inductor values include
larger physical size and degraded load transient response
(especially at low input voltage levels).
Forced-CCM Mode (FCCM)
The low noise, forced-CCM mode disables the zerocrossing comparator, which controls the low side switch
on-time. This causes the low side gate drive waveform to
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DS8237C/D-06
become the complement of the high side gate drive
waveform. This in turn causes the inductor current to
reverse at light loads as the PWM loop to maintain duty
ratio VOUT/VIN. A fairly constant switching frequency is
the benefit of forced-CCM mode, but this comes at a cost.
The no load battery current can be up to 10mA to 40mA,
depending on the external MOSFETs.
February 2014
Choose a current limit resistor by following below equation:
I


I
 RIPPLE   8  RDS(ON)
VCS_OC  LOAD_OC
2 
ROC_SET 

ICS
ICS
Inductor current is monitored by the voltage between the
GND pin and the PHASE pin, so the PHASE pin should
be connected to the drain terminal of the low side
MOSFET. ICS has a temperature coefficient to compensate
the temperature dependency of the RDS(ON). GND is used
as the positive current sensing node, so GND should be
connected to the source terminal of the low side MOSFET.
As the comparison is being done during the OFF state,
VLIMIT (current limit threshold) sets the valley level of the
inductor current. Thus, the load current at over current
threshold, ILOAD_OC, can be calculated as follows :
VCS_OC
I
ILOAD_OC =
+ RIPPLE
8  RDS(ON)
2
=
VCS_OC
8  RDS(ON)
+
(VIN  VOUT )  VOUT
1

2L  f
VIN
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RT8237C/D
In an over current condition, the current to the load exceeds
the current to the output capacitor. Thus, the output voltage
falls and eventually crosses the under voltage protection
threshold, inducing IC shutdown.
VIN
BOOT
R
UGATE
IL
PHASE
IL, PEAK
ILOAD_OC
ILIMIT
t
0
Figure 2. “Valley” Current Limit
When the device is operating in the FCCM, the negative
current limit protects the external component. The negative
current limit detect threshold is set as the same value as
positive current limit but negative polarity. The threshold
still is the valley value of the inductor current.
MOSFET Gate Driver
The high side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating
driver, 5V bias voltage is delivered from the VCC supply.
The average drive current is proportional to the gate charge
at VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOT and PHASE pins. To prevent shoot through, a
dead time is internally generated between high side
MOSFET off to low side MOSFET on, and low side
MOSFET off to high side MOSFET on. The low side driver
is designed to drive high current, low R DS(ON)
N-MOSFET(s). The internal pull-down transistor that drives
LGATE low is robust, with a 0.5Ω typical on-resistance.
A 5V bias voltage is delivered from the VCC supply. The
instantaneous drive current is supplied by the flying
capacitor between VCC and GND.
For high current applications, certain combinations of high
and low side MOSFETs may cause excessive gate-drain
coupling, which can lead to efficiency-killing, EMIproducing shoot-through currents. This is often remedied
by adding a resistor in series with BOOT, which increases
the turn-on time of the high side MOSFET without degrading
the turn-off time (see Figure 3).
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Figure 3. Reducing the UGATE Rise Time
Power Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull-up resistor. When the output voltage is 20% above
or 10% below its set voltage, PGOOD gets pulled low. It
is held low until the output voltage returns to within these
tolerances once more. During soft-start, PGOOD is actively
held low and is allowed to transition high only after softstart is over and the output reaches 90% of its set voltage.
There is a 2.5μs delay built into the PGOOD circuitry to
prevent false transitions.
Output Over Voltage Protection (OVP)
The output voltage is continuously monitored for over
voltage protection. When the output voltage exceeds 25%
of its set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
capacitor. The RT8237C/D is latched once OVP is
triggered and can only be released by VCC or EN power
on reset. There is a 5μs delay built into the over voltage
protection circuit to prevent false transitions.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of its set voltage threshold, under voltage protection
is triggered and then both UGATE and LGATE gate drivers
are forced low. There is a 2.5μs delay built into the under
voltage protection circuit to prevent false transitions. During
soft-start, the UVP blanking time is 3ms.
Thermal Shutdown (OTP)
The device implements an internal thermal shutdown to
protect itself if junction temperature exceeds 150°C. When
the junction temperature exceeds the thermal shutdown
threshold that the OTP function will be triggered and the
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February 2014
RT8237C/D
RT8237C/D will shut down and entry Latch-Off Mode. In
Latch-Off Mode, the RT8237C/D can be reset by EN or
power input VCC.
where k is the ratio between inductor ripple current and
rated output current.
Input Capacitor Selection
Output Voltage Setting (FB)
The output voltage can be adjusted from 0.7V to 3.3V by
setting the feedback resistors, R1 and R2 (see Figure 4).
Choose R2 to be approximately 10kΩ and solve for R1
using the equation below :
 R1 
VOUT = VREF   1+

 R2 
where VREF is 0.704V (typ.).
Voltage rating and current rating are the key parameters
in selecting an input capacitor. For a conservatively safe
design, an input capacitor should generally have a voltage
rating 1.5 times greater than the maximum input voltage.
The input capacitor is used to supply the input RMS
current, which is approximately calculated using the
following equation :
IRMS  IOUT 
VOUT
R1
FB
R2
Figure 4. Setting VOUT with a Resistive Voltage Divider
VOUT
VIN
 V

  1 OUT 
V

IN 
The next step is to select a proper capacitor for RMS
current rating. Placing more than one capacitor with low
Equivalent Series Resistance (ESR) in parallel to form a
capacitor bank is a good design. Also, placing ceramic
capacitor close to the drain of the high side MOSFET is
helpful in reducing the input voltage ripple at heavy load.
Inductor Selection
The inductor plays an important role in step-down
converters because it stores the energy from the input
power rail and then releases the energy to the load. From
the viewpoint of efficiency, the dc resistance (DCR) of the
inductor should be as small as possible to minimize the
conduction loss. In addition, because the inductor takes
up a significant portion of the board space, its size is also
important. Low profile inductors can save board space
especially when there is a height limitation. However, low
DCR and low profile inductors are usually cost ineffective.
Additionally, larger inductance results in lower ripple
current, which means lower power loss. However, the
inductor current rising time increases with inductance value.
This means the transient response will be slower. Therefore,
the inductor design is a compromise between
performance, size and cost.
In general, the inductance is designed such that the ripple
current ranges between 20% to 40% of the full load current.
The inductance can be calculated using the following
equation :
VIN  VOUT
V
 OUT
LMIN 
fSW  k  IOUT_rated
VIN
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February 2014
Output Capacitor Selection
The output capacitor and the inductor form a low-pass filter
in the buck topology. In steady-state condition, the ripple
current that flows into or out of the capacitor results in
ripple voltage. The output voltage ripples contains two
components, ΔVOUT_ESR and ΔVOUT_C.
VOUT_ESR  IL  ESR
VOUT_C  IL 
1
8  COUT  fSW
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage sag can be
calculated using the following equation :
VOUT_sag  ESR  IOUT
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). A rapid
change in load current results in di/dt during transient.
Therefore, ESL contributes to part of the voltage sag. Use
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RT8237C/D
a capacitor that has low ESL to obtain better transient
performance. Generally, using several capacitors in parallel
will have better transient performance than using single
capacitor for the same total ESR.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
Unlike the electrolytic capacitor, the ceramic capacitor has
relative low ESR and can reduce the voltage deviation during
load transient. However, the ceramic capacitor can only
provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
for better transient performance.
WDFN-10L 3x3 package, the thermal resistance, θJA, is
105°C/W on a standard JEDEC 51-3 single-layer thermal
test board. For WQFN-12L 2x2 package, the thermal
resistance, θJA, is 165°C/W on a standard JEDEC 51-3
single-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formula :
MOSFET Selection
PD(MAX) = (125°C − 25°C) / (105°C/W) = 0.952W for
WDFN-10L 3x3 package
However, the small duty cycle means the low side MOSFET
is on for most of the switching cycle. Therefore, the
conduction loss tends to dominate the total power loss of
the converter. To improve the overall efficiency, MOSFETs
with low RDS(ON) are preferred in circuit design. In some
cases, more than one MOSFET are connected in parallel
to further decrease the on-state resistance. However, this
depends on the low side MOSFET driver capability and
the budget.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606W for
WQFN-12L 2x2 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. For the RT8237C/D packages, the derating
curves in Figure 5 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Maximum Power Dissipation (W)1
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFETs. For
low voltage high current applications, the duty cycle of
the high side MOSFET is small. Therefore, the switching
loss of the high side MOSFET is of concern. Power
MOSFETs with lower total gate charge are preferred in
such applications.
1.00
Single-Layer PCB
0.90
0.80
0.70
WDFN-10L 3x3
0.60
0.50
0.40
WQFN-12L 2x2
0.30
0.20
0.10
0.00
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curve of Maximum Power Dissipation
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
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DS8237C/D-06
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RT8237C/D
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB may
radiate excessive noise and contribute to converter
instability. Certain points must be considered before
starting a layout for the RT8237C/D.

Connect an RC low pass filter for VCC; 1μF and 10Ω
are recommended. Place the filter capacitor close to
the IC.

Keep current limit setting network as close to the IC as
possible. Routing of the network should avoid coupling
to high voltage switching node.

Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.

All sensitive analog traces and components such as
FB, GND, EN, CS, PGOOD, VCC, and RF should be
placed away from high voltage switching nodes such as
PHASE, LGATE, UGATE, or BOOT nodes to avoid
coupling. Use internal layer(s) as ground plane(s) and
shield the feedback trace from power traces and
components.

Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.

Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed close to the IC to
minimize loops and reduce losses.
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February 2014
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RT8237C/D
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
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DS8237C/D-06
February 2014
RT8237C/D
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
1.900
2.100
0.075
0.083
E
1.900
2.100
0.075
0.083
e
0.400
0.016
D2
0.850
0.950
0.033
0.037
E2
0.850
0.950
0.033
0.037
L
0.250
0.350
0.010
0.014
W-Type 12L QFN 2x2 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8237C/D-06
February 2014
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