8 6 7 THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. 2 3 4 5 1 REVISIONS JUMPER TABLE REV JP# THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY ANALOG DEVICES. ON DESCRIPTION DATE APPROVED OFF 1 2 3 RELAY CONTROL CHART D D 4 CONTROL CODE DEVICE FUNCTION CONNECTOR 5 * SEE ASSEMBLY INSTRUCTIONS C C B B TEMPLATE ENGINEER DATE <HARDWARE_SERVICES> <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> HARDWARE SYSTEMS <HARDWARE_SYSTEMS> TEST ENGINEER <TEST_ENGINEER> A <DRAWING_TITLE1> <DRAWING_TITLE2> COMPONENT ENGINEER <COMPONENT_ENGINEER> TEST PROCESS <HARDWARE_RELEASE> DESIGNER MASTER PROJECT PTD ENGINEER UNLESS <DESIGNER> BK/BD SPEC. SOCKET OEM OEM PART# HANDLER 7 6 5 4 OTHERWISE SPECIFIED TESTER TEMPLATE <TESTER> DIMENSIONS ARE IN INCHES TOLERANCES DECIMALS X.XX +-0.010 X.XXX +-0.005 CHECKER <CHECKER> 8 TEMPLATE <DRAWING_TITLE6> <PTD_ENGINEER> SPEC. A <DRAWING_TITLE3> <DRAWING_TITLE4> <DRAWING_TITLE5> <TEST_PROCESS> HARDWARE RELEASE P.O A N A L OG DEV CE S SCHEMATIC <TEMPLATE_ENGINEER> HARDWARE SERVICES 3 FRACTIONS +-1/32 ANGLES +-2 2 REV. DRAWING NO. B 9649EE01 SIZE DD SCALE - CODE ID - NO. SHEET 1 1 OF 9 8 6 7 4 5 2 3 1 REVISIONS 1 1 2 3 F101 C101 10UF PJ-002AH-SMT APPROVED CR104 S2A-TP DATE VIN ~+5.3V A DESCRIPTION C A C ~+4.6V 4 6 5 3 A LNJ308G8TRA C (GREEN) CR103 BNX012-01 PGND D FL101 2 1 2 1.1A S2A-TP INPUT INPUT A C CR101 P101 +6VDC CR102 S2A-TP REV VREG POWER SUPPLY GND D R101 249 GND BENCH POWER SUPPLY INPUTS VIN ~+4.6V VREG SUPPLIES P102 1 2 3 4 5 6 ADP1706ARDZ-3.3-R7 EN U102 SENSE OUT OUT2 SS GND1 PAD 5 6 1 C106 IN2 E102 2 PAD 3.3V_AMPVDD 2 INSTALL TO EVALUATE SHARING OF AMP/CLK OUT OUT2 SS GND1 PAD 1 1.8V_DUT_AVDD C151 0.1UF C133 10UF GND C TP102 BLK 3.3V_CLK 2 GND C144 IN2 GND E114 5 6 2 PAD 100MHZ 4.7UF IN .01UF 4.7UF C143 C146 SENSE GND 2 VREG TP101 BLK U106 EN C150 0.1UF GND ADP1706ARDZ-3.3-R7 1 7 3 4 8 C132 10UF 100MHZ 2 100MHZ 1 E101 GND 3.3V_AMPVDD E110 1 GND C 2 100MHZ Z5.531.3625.0 100MHZ 4.7UF IN .01UF 4.7UF C105 C104 1 7 3 4 8 E109 1 E111 1.8V 1 TO 3.3V 2 MUST MATCH AUX_DVDD DUT_DRVDD GND CR106 S2A-TP ~+3.2V 1 7 3 4 8 C B EN U103 SENSE IN .01UF A 4.7UF C125 C C134 10UF C152 0.1UF GND E112 1 1.8V GND TO 3.3V 2 Z5.531.3625.0 C124 A ADP1706ARDZ-1.8-R7 OUT IN2 OUT2 SS GND1 PAD E103 5 6 1 100MHZ 2 PAD 100MHZ GND 2 100MHZ GND C153 0.1UF GND E113 1 MUST MATCH DUT_DRVDD AUX_DVDD C135 10UF 1.8V_DUT_AVDD 2 GND 4.7UF ~+3.9V 100MHZ 1 2 3 4 5 6 C126 CR105 S2A-TP P103 3.3V_CLK C136 10UF CR108 S2A-TP ~+3.2V A 1 7 3 4 8 C E104 100MHZ BYPASS DIODES FOR 3.3VREG .01UF ~+4.6V 4.7UF C128 2 C127 1 EN U104 SENSE IN OUT IN2 OUT2 SS GND1 PAD E105 1.8V 5 6 2 PAD 1 DUT_DRVDD 2 100MHZ 4.7UF ~+3.9V C GND ADP1706ARDZ-1.8-R7 C129 CR107 S2A-TP GND A B C154 0.1UF OPERATION C ~+3.2V A 1 7 3 4 8 C E106 BYPASS 100MHZ DIODES FOR 3.3VREG .01UF ~+4.6V 4.7UF C131 2 C102 1 100MHZ W/E105 EVALUATE OR E107 SHARING TO SELECT OF DUT_DRVDD 1.8V OR 3.3V AND AUX_DVDD DRVDD VREG A U105 EN SENSE IN OUT IN2 OUT2 SS GND1 PAD 2 PAD E107 3.3V 5 6 4.7UF A INSTALL ADP1706ARDZ-3.3-R7 ~+3.9V C130 A CR110 S2A-TP CR109 S2A-TP 1 E108 2 GND 1 2 AUX_DVDD <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> OPERATION THIS GND DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 7 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE 8 SCHEMATIC A N A L OG DE V CE S 100MHZ BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 2 1 OF 9 8 6 7 2 3 4 5 1 REVISIONS REV EXTERNAL DESCRIPTION DATE APPROVED VREF 3.3V_AMPVDD D D R201 2K C201 0.1UF 1.8V_DUT_AVDD BYPASS GND A201 R202 10K 1 2 DUT AVDD PIN 1.8V_DUT_AVDD EXT_REF 3 CW AD1580ARTZ CR201 2 1 2 3 1.8V_DUT_AVDD C208 0.1UF AD822BRZ C202 0.1UF 1 3 OTR LED CIRCUIT C213 0.1UF DNI GND GND 3.3V_CLK GND C206 GND 0.1UF DUT AVDD PIN 1.8V_DUT_AVDD U202 5 R206 VCC 1 A1 Y1 6 3 A2 Y2 4 R207 0 200 CR202 A C SML-LXT0805IW-TR 24 C209 0.1UF 3.3V_AMPVDD C214 0.1UF DNI GND 2 GND 6 V+ C 7 5 4 GND GND GND CLK+ PLACE NEAR DUT CLK1.8V_DUT_AVDD 1.8V_DUT_AVDD 1 2 3 INT 1 2 3 2V SPAN 2-3 GND R205 TBD0402 TBD0402 1V SPAN 2-1 D0 D1 VREF EXTERNAL REF IN AVDD PIN 32 1.8V_DUT_AVDD C211 0.1UF C216 0.1UF DNI GND GND GND U201 24 23 22 21 20 19 18 17 1.8V_DUT_AVDD MODE_OR DCO D13 D12 D11 B D10 D9 2-3 EXT_REF D2 D3 D4 D5 R204 SDIO_DUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SENSE INT CSB_DUT SCLK_DUT J202 EXT REF 2-1 GND SG-MLF32A-7004 D6 D7 D8 VREF SELECT DNI GND GND DUT_VREF R208 10K GND C215 0.1UF 10K PAD 32 1.8V_DUT_AVDD 31 AIN30 AIN+ 29 1.8V_DUT_AVDD 28 27 VCM_DUT 26 DUT_SENSE 25 DUT_DRVDD SAMTECTSW10608GS3PIN J203 1UF C203 OUTPUT MODE C210 0.1UF TP201 WHT R203 GND MODE_OR 1.1K FOR "OR" 1 2 3 R209 JUMPER 1-2 B 29 VCM_DUT AD822BRZ 1 J201 DUT AVDD PIN 1.8V_DUT_AVDD DUT_RBIAS 0.1UF V- GND GND 1UF C204 AD822BRZ GND NC7WZ16P6X C205 C A201 8 GND A201 GND INSTALL FOR PROGRAMMABLE REF DUT_DRVDD C207 0.1UF C212 0.1UF DNI GND DUT_VREF DUT_SENSE AD9649 ADC A A SCHEMATIC A N A L OG DE V CE S THIS DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 7 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 3 1 OF 9 8 6 7 2 3 4 5 1 REVISIONS REV J301 D SPI 1 2 3 4 5 6 7 8 SCLK CSB SDI SDO DESCRIPTION DATE APPROVED D CIRCUITRY TSW-104-08-T-D GND AUX_DVDD C301 GND AUX_DVDD 0.1UF NC7WZ07P6X U301 5 R310 1K R314 100K VCC SDI 1 A1 Y1 6 R311 3 A2 Y2 4 1K R309 10K GND J302 1 2 3 4 5 6 7 8 9 SDIO_DUT R313 100K 2 GND GND C SDO GND CSB_DUT USB_SCLK USB_CSB USB_SDO R301 SDI 0 R302 SPI MODE SDIO_DUT PIN MODE PDWN 4-5 SPI MODE SCLK_DUT 5-6 PIN MODE DFS 8-9 SPI MODE CSB_DUT C TSW-103-08-G-T R312 1K USB_SDI 1-2 2-3 SCLK_DUT 3.3V_CLK SCLK 0 R303 0 R304 R315 100K C302 CSB AUX_DVDD SCLK R316 10K SDO 0 GND GND 0.1UF U302 5 VCC 1 A1 Y1 6 Y2 4 GND 3 A2 FPGA_SDI FPGA_SCLK FPGA_CSB B FPGA_SDO R305 GND SDI 2 0 R306 0 R307 GND R317 10K CSB 0 R308 NC7WZ16P6X CSB SCLK B SDO GND 0 A A SCHEMATIC A N A L OG DE V CE S THIS DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 7 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 4 1 OF 9 8 6 7 2 3 4 5 1 REVISIONS REV ANALOG INPUT CIRCUITRY DEFAULT DESCRIPTION DATE APPROVED PATH D D T501 5 1 1 GND 49.9 3 0.1UF 6 T503 1 JP502 2 2 VCM JPR0402 C505 0.1UF J502 R503 130 49.9 R502 L505 C510 5PF 120NH L504 R509 0 33 C AIN- C511 5PF GND 0 2 3 4 5 AIN+ C508 5PF 0.1UF L502 1 33 0 ADT1-1WT R507 0.1UF INPUT+ 0 4 C507 C R508 0.1UF C504 1 L503 49.9 C503 GND FOOTPRINT C509 5PF C506 R506 R501 0 2 3 4 5 TO 0402 0 L501 0 OHM RESISTORS AMPIN- R505 5 3 ETC1-1-13 4 CHANGE ALL 0 J501 1 VCM JPR0402 C502 INPUT- 1 JP501 2 T502 3 ETC1-1-13 SEC 4 0 PRI C501 GND SEC GND PRI R504 130 GND AMPIN+ GND 1 JP503 2 VCM_DUT JPR0402 VCM C526 0.1UF VCM 3.3V_AMPVDD 5 PRI 0.1UF R512 66.5 0 0 GND C522 C513 R511 INPUT+ 0 0.1UF 0.1UF R515 5 6 7 8 0.1UF R520 +VS 9 2 3 12 PAD VOCM +IN -IN PD_N PAD 0.1UF U501 1 11 -OUT 10 +OUT 4 FB-OUT PLACE CORRECT VALUES L508 L510 120NH 120NH & COMPONENTS... FB+OUT -VS R523 1.00K 0 R522 1.00K R521 L522 GND C519 5PF 82NH C520 5PF C518 1 JP505 2 L521 R524 1.00K 0 16 15 14 13 ETC1-1-13 270 3 HOLDERS... AMPIN- 270 SEC 4 THESE RLCS ARE PLACE C517 R514 R518 T505 1 R519 0 0.1UF 270 R510 INPUT- B GND GND R516 C512 R517 C521 0.1UF C516 B 10UF CIRCUITRY C515 INPUT C514 AMPLIFIER 1 JP504 2 JPR0402 OPTIONAL GND L509 L520 120NH 120NH VCM JPR0402 82NH 270 AMPIN+ R513 66.5 AMP_PD_N GND GND GND 0.1UF ADA4937-1YCPZ-R7 PLACEHOLDER FOR ADA4930-1 A A 1-2 = AMP PDWN 1 2 3 A N A L OG DE V CE S J503 THIS DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 7 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE 8 SCHEMATIC 3.3V_AMPVDD GND BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 5 1 OF 9 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED CLKIN+ JPR0402 0.1UF 0.1UF GND GND 0 R601 49.9 CLOCK INPUT CLKOUT+ R609 R611 0 0 6 T601 3 GND D CLKIN- CR601 2 C602 R606 1 0 TP601 BLK 1 2 3 4 OPTIONAL TERMINATION NEAR DUT ADT1-1WT+ 0 R602 49.9 R604 0.1UF 2 3 4 5 1 CLK+ 0.1UF HSMS-2812BLK XSTAL_IN J602 C606 100 R605 C603 1 JP601 2 1 2 R613 C601 1 2 3 4 5 J603 0 J601 BALUN CLK CIRCUITRY R607 D 0 R603 XFMR / R610 R612 0 0 C607 CLK- 0.1UF T602 1 CLKINPRI 4 C C604 SEC CLKOUT- 0 R608 5 GND 3 ETC1-1-13 C CLKIN+ 1000PF GND C609 3.3V_CLK GND 0.1UF J605 1 2 3 Y601 C610 VCC TRISTATE CTRL GND OUT XSTAL_IN 0.1UF 80MHZ GND B B A A SCHEMATIC A N A L OG DE V CE S THIS DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 7 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 6 1 OF 9 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED C719 3.3V_CLK GND 0.1UF U703 WHT 5 3.3V_CLK 1 48 47 C702 CLKIN+ 0.1UF BYPASS_LDO 9 LF 8 3.3V_CLK J701 11 12 9517_CLK 1 2 3 4 5 6 7 8 R705 1.00K R706 1.00K R707 1.00K C721 CPRSET REFIN_REF1 4 CP BYPASS 42 41 39 38 19 20 22 23 35 34 33 32 26 27 28 29 OUT0 OUT0_N CLK OUT1 CLK_N OUT1_N OUT2 GND OUT2_N 0.1UF OUT3 18 PD_N 7 SYNC_N 17 OUT3_N OUT4_OUT4A RESET_N OUT4_N_OUT4B OUT5_OUT5A 3.3V_CLK OUT5_N_OUT5B TSW-104-08-T-D OUT6_OUT6A R709 1.00K C OUT6_N_OUT6B 13 16 14 SCLK SDI R708 AD9517_CSB GND OUT7_OUT7A SCLK OUT7_N_OUT7B SDIO CS_N 15 SDO 0 CP NC7WZ16P6X GND GND C703 PECL_OUT1 PECL_OUT1_N R719 49.9 DNI R720 49.9 16 15 1 2 PAD R715 49.9 GND VREF C704 SW_FREQ 33 C725 0.1UF TP704 SDO R734 130 U702 ADCLK905BCPZ-WP VCC VT R736 130 R721 12 11 Q_N D PAD R722 VEE CLKOUT- 0 R735 82.5 GND R737 82.5 GND 0.1UF CLKOUT+ 0 Q D_N R716 200 R741 3.3V_CLK 3.3V_CLK 0.1UF C726 0.1UF R714 200 GND PAD D GND 2 R743 0 DNI C R742 0 DNI 1 GND A C SML-LXT0805IW-TR 5 STATUS LF 200 CR701 GND 2 LD REFIN_N_REF2 4 GND 44 1 46 REFMON Y2 R710 49.9 VCP RSET 3 A2 R730 13 8 0.1UF VS REF_SEL 6 TP703 U701 R711 49.9 10 24 25 30 31 36 37 43 45 21 40 VS_LVPECL 6 C701 CLKIN- Y1 0 TP702 1 R704 1.00K 1 A1 14 7 3.3V_CLK D WHT 1 VCC R729 TP701 WHT CLK CIRCUITRY 3 PECL/CML/LVDS DNI GND WHT AD9517-4BCPZ R740 100 BYPASS_LDO GND J702 TP705 C720 1 9517_CLK 1 C722 .22UF WHT GND 0.1UF 49.9 R733 2 3 4 5 GND CHARGE PUMP FILTER GND 0.1UF C709 C707 C710 C715 0.1UF C711 0.1UF C716 0.1UF C712 0.1UF C717 LF .033UF 1500PF R725 49.9 C706 C705 B 1500PF 0 0.1UF C713 0.1UF C718 0.1UF C714 0.1UF C723 PECL_OUT1 0.1UF GND C724 PECL_OUT1_N 0.1UF 5 4 3 2 200 R739 J704 1 GND 0.1UF GND GND B 5 4 3 2 GND BYPASS_LDO C708 J703 1 200 R728 R738 R727 49.9 R726 49.9 CP R723 49.9 3.3V_CLK GND 0.1UF GND A A SCHEMATIC A N A L OG DE V CE S THIS DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 7 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 7 1 OF 9 8 6 7 2 3 4 5 1 REVISIONS REV SERIES D DESCRIPTION DATE APPROVED RESISTORS CHANGE TO ~220 OHM SERIES D R'S OUTPUT BUFFERS DCO RN801 3 6 I19 22 MODE_OR RN801 4 5 I18 22 D13 RN808 1 8 D12 22 RN808 2 7 I16 D11 22 RN808 3 6 I15 D10 22 RN808 4 5 D9 RN805 1 8 D8 22 RN805 2 7 I17 C805 0.1UF D7 22 RN805 3 6 I14 D6 I4 GND I5 I13 I6 I7 I8 I12 I9 I10 I11 I11 I12 22 RN805 4 5 I13 I14 I10 I15 22 I16 I17 I18 I9 D4 22 RN809 2 7 D3 22 RN809 3 6 I7 D2 22 RN809 4 5 I6 B I19 I8 TP802 BLK VCC I0 O0 I1 O1 I2 O2 I3 O3 I4 O4 I5 O5 I6 O6 I7 O7 I8 O8 I9 O9 I10 O10 I11 O11 I12 O12 I13 O13 I14 O14 I15 O15 I16 O16 I17 O17 I18 O18 C808 0.1UF GND I19 O19 R802 10K 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 C O_D0 O_D1 O_D2 O_D3 O_D4 O_D5 O_D6 O_D7 O_D8 O_D9 O_D10 O_D11 O_D12 O_D13 O_OR O_CLK OE1_N OE2_N OE3_N OE4_N GND 4 11 18 25 32 39 46 53 D5 RN809 1 8 C807 0.1UF U802 50 35 22 7 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 1 56 29 28 22 C C806 0.1UF AUX_DVDD 74VCX162827MTDX GND GND 22 D1 RN804 1 8 I5 D0 22 RN804 2 7 I4 B 22 A A SCHEMATIC A N A L OG DE V CE S THIS DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 7 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 8 1 OF 9 8 6 7 2 3 4 5 1 REVISIONS REV O_D9 O_D11 O_D13 O_CLK O_D4 O_D6 O_D8 O_D10 O_D12 O_OR 6469169-1 6469169-1 6469169-1 FIFO B 6469169-1 6469169-1 GND P902 P902 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 GND D PLUG HEADER PLUG HEADER PLUG HEADER P902 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 APPROVED P901 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 6469169-1 GND DATE DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 6469169-1 GND 6469169-1 C PLUG HEADER O_D7 O_D2 6469169-1 P902 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 P901 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 PLUG HEADER O_D5 6469169-1 P902 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 PLUG HEADER O_D3 USB_SCLK 6469169-1 O_D0 PLUG HEADER O_D1 USB_SDI FPGA_SDI P902 C USB_SDO FPGA_SCLK 6469169-1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 FPGA_SDO P901 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 PLUG HEADER FPGA_CSB P901 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 PLUG HEADER USB_CSB PLUG HEADER AD9517_CSB PLUG HEADER D C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 PLUG HEADER P901 P901 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 DESCRIPTION 5 CONNECTIONS B A A SCHEMATIC A N A L OG DE V CE S THIS DRAWING IT IS IN PART, IS THE PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG THE 7 6 5 4 3 DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN PTD SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. VIEW DRAWING <DESIGN_VIEW> REV NO. B 9649EE01 INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 OF ANALOG OR COPIED, FURNISHING OR FOR ANY OTHER PURPOSE <DRAWING_TITLE_HEADER> AD9649 <PRODUCT_1> BY PATENTS SIZE ENGINEER <PTD_ENGINEER> 2 DD SCALE - SHEET 9 1 OF 9