PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µPD780016Y, 780018Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD780016Y and 780018Y are members of the µ PD780018Y subseries of the 78K/0 series microcontrollers. Besides a high-speed, high-performance CPU, these microcontrollers have on-chip ROM, RAM, I/O ports, timer, serial interface, real-time output port, interrupt control, and various other peripheral hardware. The µ PD78P0018Y devices including a one-time PROM version and an EPROM version, both of which can operate in the same power supply voltage range as a mask ROM version, and various development tools are available. The details of the functions are described in the following user’s manuals. Be sure to read it before starting design. µPD780018,780018Y Subseries User’s Manual: U11754E 78K/0 Series User’s Manual – Instructions : IEU-1372 FEATURES • Internal high capacity ROM and RAM Item Part Number Program Memory (ROM) µPD780016Y 48K bytes µPD780018Y 60K bytes Data Memory Internal High-Speed RAM Buffer RAM Internal Extended RAM 1024 bytes 32 bytes 1024 bytes • External memory expansion space: 64K bytes • Instruction execution time can be changed from high-speed (0.4 µs) to ultra-low-speed (122 µs) • I/O ports: 88 • 8-bit resolution A/D converter: 8 channels • Timer: 7 channels Package 100-pin plastic QFP (14 × 20 mm) • Serial interface: 3 channels • 3-wire serial I/O mode (with automatic data transmit/receive function): 1 channel • 3-wire serial I/O mode (with time division transfer function): 1 channel • I2C bus mode (supporting multi-task): 1 channel • Supply voltage : VDD = 2.7 to 5.5 V APPLICATION FIELD Cellular phones, cordless phones, AV equipment, etc. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Document No. U11810EJ1V0PM00 (1st edition) Date Published December 1996 N Printed in Japan © 1996 µPD780016Y, 780018Y ORDERING INFORMATION Part Number Package µPD780016YGF-XXX-3BA 100-pin plastic QFP (14 × 20 mm) µPD780018YGF-XXX-3BA 100-pin plastic QFP (14 × 20 mm) Remark XXX indicates ROM code suffix. 78K/0 SERIES DEVELOPMENT These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names. Under mass production Under development Y subseries supports I2C bus. For control 100-pin µ PD78078 µ PD78078Y Timer added to the µPD78054, external interface functions enhanced 100-pin µ PD78070A µ PD78070AY ROM-less product for the µPD78078 100-pin µ PD780018Note µ PD780018YNote Enhanced serial I/O of the µPD78078, functions limited 80-pin µ PD78058F µ PD78058FY Reduced EMI noise product of the µPD78054 80-pin µ PD78054 µ PD78054Y UART and D/A added to the µPD78014, enhanced I/O 64-pin µ PD780034 µ PD780034Y Enhanced A/D of the µ PD780024 64-pin µ PD780024 µ PD780024Y Enhanced serial I/O of the µ PD78018F. Reduced EMI noise product. 64-pin 64-pin µ PD780964 µ PD780924 64-pin µ PD78014H 64-pin µ PD78018F µ PD78018FY Reduced EMI noise of the µ PD78018F. Low-voltage (1.8 V) operation product of the µ PD78014, ROM, RAM variations enhanced 64-pin µ PD78014 µ PD78014Y A/D, 16-bit timer added to the µPD78002 64-pin 64-pin µ PD780001 µ PD78002 µ PD78002Y 42/44-pin µ PD78083 Enhanced A/D of the µ PD780924 Internal inverter control circuit and UART. Reduced EMI noise product. A/D added to the µPD78002 Basic subseries for control Internal UART, low-voltage (1.8 V) operation possible For driving FIPTM 78K/0 series 100-pin µ PD780208 I/O, FIP C/D of the µPD78044F enhanced, display output total: 53 80-pin µ PD78044F 6-bit U/D counter added to the µPD78024, display output total: 34 64-pin µ PD78024 Basic subseries for FIP driving, display output total: 26 For driving LCD 100-pin µ PD780308 100-pin µ PD78064B 100-pin µ PD78064 µPD780308Y Enhanced SIO of the µPD78064, ROM, RAM extended Reduced EMI noise product of the µPD78064 µ PD78064Y Basic subseries for LCD driving, internal UART Supporting IEBusTM 80-pin µ PD78098 IEBus controller added to the µPD78054 For LV 64-pin µPD78P0914 Note Under planning 2 PWM output, internal LV digital code decoder, Hsync counter µPD780016Y, 780018Y The major functional differences among the subseries are shown below. Function Subseries Name For Control µPD78078 ROM Capacity Timer 8-bit 16-bit Watch WDT 32 K-60 K 4ch µPD78070A 1ch 1ch 1ch 8ch — I/O VDD External MIN. Eexpansion Value 2ch 3ch (UART: 1ch) 88 1.8 V 61 2.7 V — µPD780018 48 K-60 K µPD78058F µPD78054 Serial Interface 8-bit 10-bit 8-bit A/D A/D D/A — 2ch 2ch 2ch 88 3ch (UART: 1ch) 69 16 K-60 K 2.0 V µPD780034 8 K-32 K µPD780024 µPD780964 3ch Note — µPD780924 µPD78014H 2ch — 8ch 8ch — — 8ch 8ch — — 51 1.8 V 2ch (UART: 2ch) 47 2.7 V 1.8 V 1ch 1ch 2ch 53 — — 1ch 39 µPD78018F 8 K-60 K µPD78014 8 K-32 K 2.7 V µPD780001 8 K µPD78002 8 K-16 K µPD78083 1ch — — 8ch 53 1ch (UART: 1ch) 33 1.8 V — 74 2.7 V — 1.8 V — For FIP µPD780208 32 K-60 K 2ch driving µPD78044F 16 K-40 K 68 µPD78024 54 1ch 1ch 8ch — — 2ch 24 K-32 K For LCD µPD780308 48 K-60 K 2ch driving µPD78064B 32 K 1ch 1ch 1ch 8ch — — 3ch (UART: 1ch) 57 2ch (UART: 1ch) µPD78064 16 K-32 K For IEBus µPD78098 32 K-60 K 2ch For LV µPD78P0914 32 K Note 1ch 6ch — 1ch 1ch 1ch 8ch — 2ch — — 1ch 8ch — — 2.0 V 3ch (UART: 1ch) 69 2.7 V 2ch 54 4.5 V 10-bit timer: 1 channel 3 µPD780016Y, 780018Y OVERVIEW OF FUNCTION Part Number µPD780016Y µPD780018Y 60K bytes Item Internal ROM 48K bytes memory Internal high-speed RAM 1024 bytes Buffer RAM 32 butes Internal expansion RAM 1024 bytes Memory space 64K bytes General registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction cycle On-chip instruction execution time selective function When main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 5.0 MHz) When subsystem clock selected 122 µs (at 32.768 kHz) Instruction set • • • • I/O ports 16-bit operation Multiplcation/division (8 bits × 8 bits,16 bits ÷ 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD adjustment, etc. Total • CMOS input • CMOS I/O 4 : 88 : 9 : 79 A/D converter • 8-bit resolution × 8 channels Serial interface • 3-wire serial I/O mode (with automatic data transmit/receive function): 1 channel • 3-wire serial I/O mode (with time division transfer function) : 1 channel • I2C bus mode (supporting multi-task) : 1 channel Timer • • • • Timer output 5 (14-bit PWM output × 1, 8-bit PWM output × 2) Clock output 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (at main system clock of 5.0 MHz) 32.768 kHz (at subsystem clock of 32.768 kHz) Buzzer output 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: at 5.0 MHz) Vectored interrupt sources Maskable Internal : 12 External : 7 Non-maskable Internal : 1 Software 1 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Test input Internal : 1 External : 1 Supply voltage VDD = 2.7 to 5.5 V Package • 100-pin plastic QFP (14 × 20 mm) µPD780016Y, 780018Y CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 6 2. BLOCK DIAGRAM .............................................................................................................................. 8 3. PIN FUNCTIONS ................................................................................................................................. 9 3.1 Port Pins ...................................................................................................................................................... 9 3.2 Non-port Pins ............................................................................................................................................ 11 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 13 4. MEMORY SPACE .............................................................................................................................. 16 5. PERIPHERAL HARDWARE FUNCTIONS ....................................................................................... 17 5.1 Ports ........................................................................................................................................................... 17 5.2 Clock Generator ........................................................................................................................................ 18 5.3 Timer/Event Counter ................................................................................................................................ 18 5.4 Clock Output Control Circuit .................................................................................................................. 22 5.5 Buzzer Output Control Circuit ................................................................................................................ 22 5.6 A/D Converter ........................................................................................................................................... 23 5.7 Serial Interfaces ........................................................................................................................................ 24 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ....................................................................... 26 6.1 Interrupt Functions .................................................................................................................................. 26 6.2 Test Functions .......................................................................................................................................... 29 7. EXTERNAL DEVICE EXPANSION FUNCTIONS ............................................................................. 30 8. STANDBY FUNCTION ...................................................................................................................... 30 9. RESET FUNCTION ............................................................................................................................ 31 10. INSTRUCTION SET ........................................................................................................................... 32 11. PACKAGE DRAWINGS ..................................................................................................................... 34 APPENDIX A. DEVELOPMENT TOOLS................................................................................................ 35 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 37 5 µPD780016Y, 780018Y 1. PIN CONFIGURATION (TOP VIEW) • 100-pin plastic QFP (14 × 20 mm) P156 P155 P154 P153 P152 P151 P150 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103 P102 P101/TI6/TO6 P100/TI5/TO5 P67/ASTB µPD780016YGF-XXX-3BA, 780018YGF-XXX-3BA P80/A0 P81/A1 P82/A2 P83/A3 P84/A4 P85/A5 P86/A6 P87/A7 IC X2 X1 VDD1 XT2 XT1 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14 VSS0 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P117/SCL P116/SDA P115 P114 P113 P112/SCK4C P16/ANI6 P17/ANI7 AVSS P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25 VSS1 P26 P27 P90/SI4A P91/SO4A P92/SCK4A P93/SI4B P94/SO4B P95/SCK4B P110/SI4C P111/SO4C P05/INTP5 P06/INTP6 VDD0 AVREF P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 Cautions 1. Connect IC (internally connected) pin directly to VSS0. 2. AVSS pin should be connected to VSS0. Remark When the circuit is used in an application where the noise generated from the inside of the microcontroller needs to be reduced, take countermeasures against noise such as supplying power to VDD0 and VDD1 separately and connecting VSS0 and VSS1 to the ground line separately. 6 µPD780016Y, 780018Y A0-A15 : Address Bus PCL AD0-AD7 : Address/Data Bus RD : Read Strobe ANI0-ANI7 : Analog Input RESET : Reset ASTB : Address Strobe SCK1 : Serial Clock AVREF : Analog Reference Voltage SCK4A, SCK4B, SCK4C : Serial Clock AVSS : Analog Ground SCL : Serial Clock BUSY : Busy SDA : Serial Data BUZ : Buzzer Clock SI1 : Serial Input IC : Internally Connected SI4A, SI4B, SI4C : Serial Input INTP0-INTP6 : Interrupt from Peripherals SO1 : Serial Output P00-P06 : Port0 SO4A, SO4B, SO4C : Serial Output P10-P17 : Port1 STB : Strobe P20-P27 : Port2 TI00, TI01 : Timer Input P30-P37 : Port3 TI1, TI2, TI5, TI6 : Timer Input P40-P47 : Port4 TO0-TO2, TO5, TO6 : Timer Output P50-P57 : Port5 VDD0, VDD1 : Power Supply P60-P67 : Port6 VSS0, VSS1 : Ground P80-P87 : Port8 WAIT : Wait P90-P96 : Port9 WR : Write Strobe P100-P103 : Port10 X1, X2 : Crystal (Main System Clock) P110-P117 : Port11 XT, XT2 : Crystal (Subsystem Clock) P150-P156 : Port15 : Programmable Clock 7 µPD780016Y, 780018Y 2. BLOCK DIAGRAM 16-bit timer/ event counter Port 0 P00 P01_P06 TO1/P31 TI1/P33 8-bit timer/ event counter 1 Port 1 P10_P17 8-bit timer/ event counter 2 Port 2 P20_P27 TO2/P32 TI2/P34 Port 3 P30_P37 Port 4 P40_P47 Port 5 P50_P57 Port 6 P60_P67 Port 8 P80_P87 Port 9 P90_P95 TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TI5/TO5/P100 TI6/TO6/P101 8-bit timer/ event counter 5 8-bit timer/ event counter 6 Watchdog timer Watch timer SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 Serial interface 4 SDA/P116 SCL/P117 Serial interface 5 AVSS AVREF INTP0/P00_ INTP6/P06 ROM Serial interface 1 SI4A/P90 SO4A/P91 SCK4A/P92 SI4B/P93 SO4B/P94 SCK4B/P95 SI4C/P110 SO4C/P111 SCK4C/P112 ANI0/P10_ ANI7/P17 78K/0 CPU Core RAM Port 10 P100_P103 Port 11 P110_P117 Port 15 P150_P156 AD0/P40_ AD7/P47 A0/P80_ External access RD/P64 A/D converter WR/P65 WAIT/P66 ASTB/P67 Interrupt control RESET System control BUZ/P36 Buzzer output PCL/P35 Clock output control VDD0, VDD1 VSS0, VSS1 IC Remark The internal ROM capacity depends on the product. 8 A7/P87 A8/P50_ A15/P57 X1 X2 XT1 XT2 µPD780016Y, 780018Y 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name I/O P00 Input P01 Input/ output P02 Function Port 0 7-bit I/O port Input only After Reset Alternate Function Pin Input INTP0/TI00 Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. INTP1/TI01 INTP2 INTP3 P03 Input P04 INTP4 P05 INTP5 P06 INTP6 P10 to P17 Input Port 1 8-bit input port Input ANI7 On-chip pull-up resistor can be used by software.Note P20 Input/ output P21 P22 Port 2 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. P23 ANI0 to SI1 SO1 SCK1 Input STB P24 BUSY P25-P27 — P30 Input/ output P31 P32 TO0 Port 3 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. TO1 TO2 TI1 P33 Input P34 TI2 P35 PCL P36 BUZ P37 — P40 to P47 Note Input/ output Port 4 8-bit input/output port Input/output can be specified in 8-bit units. When used as an input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input AD0 to AD7 When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, on-chip pull-up resistor is automatically disconnected. 9 µPD780016Y, 780018Y 3.1 Port Pins (2/2) Pin Name I/O P50 to P57 Input/ output P60 Input/ output P61 P62 After Reset Alternate Function Pin Port 5 8-bit input/output port LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input A8 to A15 Port 6 8-bit input/ output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input — Function P63 P64 RD P65 WR P66 WAIT P67 ASTB P80 to P87 Input/ output Port 8 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input A0 to A7 P90 Input/ output Port 9 6-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input SI4A P91 P92 SO4A SCK4A P93 SI4B P94 SO4B P95 SCK4B P100 P101 Input/ output P102, P103 P110 P111 Input/ output P112 Port 10 4-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input Port 11 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input TI5/TO5 TI6/TO6 — SI4C SO4C SCK4C P113-P115 — P116 SDA P117 SCL P150-P156 10 Input/ output Port 15 7-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input — µPD780016Y, 780018Y 3.2 Non-port Pins (1/2) Pin Name INTP0 I/O Input INTP1 Function External interrupt request input by which the active edge (rising edge, falling edge, or both rising and falling edges) can be specified. After Reset Alternate Function Pin Input P00/TI00 P01/TI01 INTP2 P02 INTP3 P03 INTP4 P04 INTP5 P05 INTP6 P06 SI1 Input Serial interface serial data input. Input P20 SI4A P90 SI4B P93 SI4C P110 SO1 Output Serial interface serial data output. Input P21 SO4A P91 SO4B P94 SO4C P111 SDA Input/output Input/output of serial data of serial interface. Input P116 SCK1 Input /output Serial interface serial clock input/output. Input P22 SCK4A P92 SCK4B P95 SCK4C P112 SCL P117 Output Serial interface automatic transmit/receive strobe output. Input P23 BUSY Input Serial interface automatic transmit/receive busy input. Input P24 TI00 Input External count clock input to 16-bit timer (TM0). Input P00/INTP0 STB P01/INTP1 TI01 Capture trigger signal input to capture register (CR00). TI1 External count clock input to 8-bit timer (TM1). P33 TI2 External count clock input to 8-bit timer (TM2). P34 TI5 External count clock input to 8-bit timer (TM5). P100/TO5 TI6 External count clock input to 8-bit timer (TM6). P100/TO6 TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output). Input P30 TO1 8-bit timer (TM1) output. P31 TO2 8-bit timer (TM2) output. P32 TO5 8-bit timer (TM5) output (also used for 8-bit PWM output). P100/TI5 TO6 8-bit timer (TM6) output (also used for 8-bit PWM output). P101/TI6 PCL Output Clock output (for main system clock, subsystem clock trimming). Input P35 BUZ Output Buzzer output. Input P36 AD0 to AD7 Input /output Low-order address/data bus at external memory expansion. Input P40 to P47 11 µPD780016Y, 780018Y 3.2 Non-port Pins (2/2) After Reset Alternate Function Pin Low-order address bus at external memory expansion. Input P80 to P87 Output High-order address bus at external memory expansion. Input P50 to P57 Output External memory read operation strobe signal output. Pin Name I/O A0 to A7 Output A8 to A15 RD WR Function P64 Input P65 External memory write operation strobe signal output. WAIT Input ASTB Output Wait insertion at external memory access. Strobe output which externally latches the address information output to Input Input P66 P67 ports 4, 5 and 8 to access external memory. ANI0 to ANI7 Input A/D converter analog input. AVREF Input AVSS — RESET 12 Input P10 to P17 A/D converter reference voltage input (shared with analog power supply). — — A/D converter ground potential. Same potential as VSS0. — — Input System reset input. — — X1 Input Main system clock oscillation crystal connection. — — X2 — — — XT1 Input Input — XT2 — — — VDD0 — Port block positive power supply. — — VSS0 — Port block ground potential. — — VDD1 — Positive power supply (except for port and analog blocks) — — VSS1 — Ground potential (except for port and analog blocks) — — IC — Internal connection. Connect directly to VSS0. — — Subsystem clock oscillation crystal connection. µPD780016Y, 780018Y 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits (1/2) Input/Output Circuit Type I/O P00/INTP0/TI00 2 Input P01/INTP1/TI01 8-C Input/output P10/ANI0-P17/ANI7 9-B Input P20/SI1 8-C Input/output P21/SO1 5-H P22/SCK1 8-C P23/STB 5-H P24/BUSY 8-C P25-P27 5-H Pin Name Recommended Connection for Unused Pins Connect to VSS0. Connect to VSS0 via a resistor individually. P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 Connect to VDD0 or VSS0 via a resistor individually. P30/TO0-P32/TO2 P33/TI1 8-C P34/TI2 P35/PCL 5-H P36/BUZ P37 P40/AD0-P47/AD7 5-N Input/output Connect to VDD0 via a resistor individually. P50/A8-P57/A15 5-H Input/output Connect to VDD0 or VSS0 via a resistor individually. P60-P63 P64/RD P65/WR P66/WAIT P67/ASTB P80/A0-P87/A7 P90/SI4A 8-C P91/SO4A 5-H P92/SCK4A 8-C P93/SI4B P94/SO4B 5-H P95/SCK4B 8-C 13 µPD780016Y, 780018Y Table 3-1. Types of Pin Input/Output Circuits (2/2) Pin Name P100/TI5/TO5 Input/Output Circuit Type 8-C I/O Input/output Recommended Connection for Unused Pins Connect to VDD0 or VSS0 via a resistor individually. P101/TI6/TO6 P102, P103 5-H P110/SI4C 8-C P111/SO4C 5-H P112/SCK4C 8-C P113-P115 5-H P116/SDA 10-B P117/SCL P150-P156 5-H RESET 2 Input XT1 16 — XT2 AVREF — Connect to VDD0. Leave open. — Connect to VSS0. AVSS IC 14 Connect to VSS0. µPD780016Y, 780018Y Figure 3-1. Pin Input/Output Circuits Type 2 Type 9-B VDD0 pullup enable P-ch IN comparator P-ch N-ch IN + _ VSS0 Schmitt-triggered input with hysteresis characteristic VREF threshold voltage input enable VDD0 Type 5-H pullup enable Type 10-B VDD0 pullup enable P-ch P-ch VDD0 data VDD0 data P-ch P-ch IN/OUT output disable IN/OUT open drain output disable N-ch N-ch VSS0 VSS0 input enable Type 5-N Type 16 VDD0 pullup enable feedback cut-off P-ch VDD0 P-ch data P-ch IN/OUT output disable N-ch VSS0 XT1 Type 8-C XT2 VDD0 pullup enable P-ch VDD0 data P-ch IN/OUT output disable N-ch VSS0 15 µPD780016Y, 780018Y 4. MEMORY SPACE The memory map of the µPD780016Y and 780018Y is shown in Figure 4-1. Figure 4-1. Memory Map FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits FB00H FAFFH Use prohibited FAE0H Data memory space FADFH FAC0H nnnnH Buffer RAM 32 × 8 bits Program area 1000H 0FFFH FABFH Use prohibited CALLF entry area F800H F7FFH 0800H Internal extended RAM F400H F3FFH Program nnnnH+1 memory nnnnH space 07FFH 1024 × 8 bits Program area 0080H Use prohibited Note 1 007FH CALLT table area 0040H 003FH Internal ROM Note 2 Vector table area 0000H 0000H Notes 1. If external device expansion functions are to be employed for the µPD780018Y, set the size of the internal ROM to below 56K bytes using the memory size switching register (IMS). 2. The internal ROM capacity depends on the product. (See the following table.) Part Number 16 Internal ROM Last Address nnnnH µPD780016Y BFFFH µPD780018Y EFFFH µPD780016Y, 780018Y 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 Ports Input/output ports are classified into two types. • CMOS input (P00, Port 1) : 9 • CMOS input/output (P01 to P06, Port 2 to 6, Port 8 to 11, Port 15) Total : 79 : 88 Table 5-1. Functions of Ports Port Name Pin Name Port 0 P00 Function Input only. P01 to P06 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 1 P10 to P17 Input only. On-chip pull-up resistor can be used by software. Port 2 P20 to P27 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 3 P30 to P37 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 4 P40 to P47 Input/output port. Input/output can be specified in 8-bit units. When used as an input port, on-chip pull-up resistor can be used by software. The test input flag (KRIF) is set to 1 by falling edge detection. Port 5 P50 to P57 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. LED can be driven directly. Port 6 P60 to P67 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 8 P80 to P87 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 9 P90 to P95 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 10 P100 to P103 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 11 P110 to P117 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 15 P150 to P156 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. 17 µPD780016Y, 780018Y 5.2 Clock Generator There are two kinds of clock generators: main system and subsystem clock generators. It is possible to change the instruction execution time. • 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at main system clock frequency of 5.0 MHz) • 122 µs (at subsystem clock frequency of 32.768 kHz) Figure 5-1. Clock Generator Block Diagram XT1 Subsystem clock oscillator XT2 fXT Watch timer, Clock output function X1 Main system fX clock oscillator X2 Division circuit Selector Prescaler fXX fXX 2 fX 2 Prescaler 1 fXX 22 fXX 23 fXX 24 Clock to peripheral hardware 2 fXT 2 Selector STOP MCSNote Oscillation mode select register Wait control circuit Standby control circuit CPU clock (fCPU) To INTP0 sampling clock Note Be sure to set 1 to MCS. 5.3 Timer/Event Counter There are the following seven timer/event counter channels: • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter : 4 channels • Watch timer : 1 channel • Watchdog timer : 1 channel Table 5-2. Types and Functions of Timer/Event Counters 16-bit Timer/Event 8-bit Timer/Event Counter Counters 1, 2 8-bit Timer/Event Counters 5, 6 Watch Timer Watchdog Timer Interval timer 1 channel 2 channels 2 channels 1 channel 1 channel External event counter 1 channel 2 channels 2 channels — — Timer output 1 output 2 outputs 2 outputs — — PWM output 1 output — 2 outputs — — Pulse width measurement 2 inputs — — — — Square wave output 1 output 2 outputs 2 outputs — — One-shot pulse output 1 output — — — — Interrupt request 2 2 2 1 1 Test input — — — 1 input — Type Function 18 µPD780016Y, 780018Y Figure 5-2. 16-Bit Timer/Event Counter Block Diagram Internal bus INTP1 Selector TI01/P01/ INTP1 16-bit capture/ compare register (CR00) INTTM00 PWM pulse output control circuit Match Watch timer output Selector fXX fXX/2 fXX/22 TO0/P30 16-bit timer register (TM0) Clear TI00/P00/ INTP0 Output control circuit Edge detector Selector Match INTTM01 INTP0 16-bit capture/ compare register (CR01) Internal bus Figure 5-3. 8-Bit Timer/Event Counter 1, 2 Block Diagram Internal bus 8-bit compare register (CR10) 8-bit compare register (CR20) Match fXX/211 TI1/P33 8-bit timer register 1 (TM1) Clear fXX/211 TI2/P34 TO2/P32 8-bit timer register 2 (TM2) Clear Selector fXX/2fXX/29 Output control circuit INTTM2 Selector fXX/2fXX/29 Selector Match Selector INTTM1 Selector Output control circuit TO1/P31 Internal bus 19 µPD780016Y, 780018Y Figure 5-4. 8-Bit Timer/Event Counter 5, 6 Block Diagram Internal bus 8-bit compare register (CRn0) fXX - fXX/29 fXX/211 Selector Match 8-bit timer register n (TMn) TI5/P100/TO5, TI6/P101/TO6 20 OVF Clear Internal bus n = 5, 6 INTTMn Output control circuit TO5/P100/TI5, TO6/P101/TI6 µPD780016Y, 780018Y fXT fW Prescaler fW 25 fW 26 fW 27 fW 28 INTWT fW 213 fW 29 Selector fW 24 5-bit counter fW 214 Selector Selector fXX/27 Selector Figure 5-5. Watch Timer Block Diagram INTTM3 To 16-bit timer/ event counter Figure 5-6. Watchdog Timer Block Diagram fXX 23 Prescaler fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 INTWDT maskable interrupt request 8-bit counter Control circuit fXX 25 Selector fXX 24 RESET INTWDT non-maskable interrupt request 21 µPD780016Y, 780018Y 5.4 Clock Output Control Circuit This circuit can output clocks of the following frequencies: • 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (at main system clock frequency of 5.0 MHz) • 32.768 kHz (at subsystem clock frequency of 32.768 kHz) Figure 5-7. Clock Output Control Circuit Block Diagram fXX fXX/2 fXX/24 fXX/25 fXX/26 Selector fXX/22 fXX/23 Synchronization circuit Output control circuit PCL/P35 fXX/27 fXT 5.5 Buzzer Output Control Circuit This circuit can output clocks of the following frequencies that can be used for driving buzzers: • 2.4 kHz/4.9 kHz/9.8 kHz (at main system clock frequency of 5.0 MHz) fXX/29 fXX/210 fXX/211 22 Selector Figure 5-8. Buzzer Output Control Circuit Block Diagram Output control circuit BUZ/P36 µPD780016Y, 780018Y 5.6 A/D Converter The A/D converter consists of eight 8-bit resolution channels. A/D conversion can be started by the following two methods: • Hardware starting • Software starting Figure 5-9. A/D Converter Block Diagram Series resistor string ANI0/P10 AVREF ANI1/P11 ANI2/P12 ANI4/P14 Voltage comparator Selector ANI3/P13 AVSS ANI5/P15 Tap selector Sample & hold circuit ANI6/P16 AVSS ANI7/P17 INTP3/P03 Successive approximation register (SAR) Edge detector Control circuit INTAD INTP3 A/D conversion result register (ADCR) Internal bus 23 µPD780016Y, 780018Y 5.7 Serial Interfaces There are the following three on-chip serial interface channels synchronous with the clock: • Serial interface channel 1 • Serial interface channel 4 • Serial interface channel 5 Table 5-3. Types and Functions of Serial Interfaces Function Serial Interface Channel 1 Serial Interface Channel 4 Serial Interface Channel 5 (Starting bit MSB/LSB switching possible) (Starting bit MSB/LSB switching possible) 3-wire serial I/O mode 3-wire serial I/O mode with automatic data transmit/ /receive function — — — (Starting bit MSB/LSB switching possible) 3-wire serial I/O mode with automatic data transmit/ receive function — I2C bus mode — — (Starting bit MSB/LSB switching possible) — (MSB first) Figure 5-10. Serial Interface Channel 1 Block Diagram Internal bus Automatic data transmit/ receive address pointer (ADTP) Automatic data transmit/receive interval specification register (ADTI) Buffer RAM Serial I/O shift register 1 (SIO1) SI1/P20 Match SO1/P21 5-bit counter BUSY/P24 SCK1/P22 Handshake control circuit Serial clock counter Serial clock control circuit 24 Interrupt request signal generator Selector STB/P23 INTCSI1 fXX/22—fXX/28 TO2 µPD780016Y, 780018Y Figure 5-11. Serial Interface Channel 4 Block Diagram SO4A/P91 SO4B/P94 SO4C/P111 SCK4A/P92 SCK4B/P95 SCK4C/P112 Interrupt request signal generator Serial clock counter Selector SI4C/P110 Serial I/O shift register 4 (SIO4) Selector SI4B/P93 Selector SI4A/P90 Selector Internal bus Serial clock control circuit INTCSI4 fXX/22-fXX/28 TO2 Figure 5-12. Serial Interface Channel 5 Block Diagram Internal bus I2C bus interface control register (IICC) Slave address register 5 (SVA5) Clear Match signal P116/SDA Serial I/O shift register 5 (SIO5) Set Output latch CL0 Data retention time correction circuit N-ch open-drain output I2C bus interface status register (IICS) P116 output latch Wake-up control circuit Acknowledge output circuit Acknowledge detection circuit Start condition detection circuit Stop condition detection circuit P117/SCL Interrupt request signal generation circuit Serial clock counter Serial clock control circuit N-ch open-drain output P117 output latch INTIIC Serial clock wait control circuit Prescaler I2C bus interface clock select register (IICCL) Internal bus 25 µPD780016Y, 780018Y 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 Interrupt Functions A total of 21 interrupt functions are provided, divided into the following three types. • Non-maskable : 1 • Maskable : 19 • Software : 1 Table 6-1. List of Interrupt Factors Interrupt DefaultNote 1 Type Priority Name Nonmaskable — INTWDT Overflow of watchdog timer (When the watchdog timer mode 1 is selected) Maskable 0 INTWDT Overflow of watchdog timer (When the interval timer mode is selected) 1 INTP0 2 Interrupt Factor Trigger Pin input edge detection Internal/ Vector Table BasicNote 2 External Address Structure Type Internal 0004H (A) (B) External 0006H (C) INTP1 0008H (D) 3 INTP2 000AH 4 INTP3 000CH 5 INTP4 000EH 6 INTP5 0010H 7 INTP6 0012H 8 INTCSI1 Completion of serial interface channel 1 transfer 9 INTTM3 Reference interval signal from watch timer 001EH 10 INTTM00 Generation of matching signal of 16-bit timer 0020H Internal 0016H (B) register and capture/compare register (CR00) Software 11 INTTM01 Generation of matching signal of 16-bit timer register and capture/compare register (CR01) 0022H 12 INTTM1 Generation of matching signal of 8-bit timer/event counter 1 0024H 13 INTTM2 Generation of matching signal of 8-bit timer/event counter 2 0026H 14 INTAD Completion of A/D conversion 0028H 15 INTTM5 Generation of matching signal of 8-bit timer/event counter 5 002AH 16 INTTM6 Generation of matching signal of 8-bit timer/event counter 6 002CH 17 INTCSI4 Completion of serial interface channel 4 transfer 002EH 18 INTIIC Completion of serial interface channel 5 transfer 0030H — BRK Execution of BRK instruction — 003EH (E) Notes 1. Default priority is the priority order when several maskable interruptions are generated at the same time. 0 is the highest order and 18 is the lowest order. 2. Basic structure types (A) to (E) correspond to (A) to (E) in Figure 6-1. 26 µPD780016Y, 780018Y Figure 6-1. Interrupt Function Basic Configuration (1/2) (A) Internal non-maskable interrupt Internal bus Priority control circuit Interrupt request Vector table address generator Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Priority control circuit IF Vector table address generator Standby release signal (C) External maskable interrupt (INTP0) Internal bus Interrupt request Sampling clock select register (SCS) External interrupt mode register (INTM0) Sampling clock Edge detector MK IF IE PR Priority control circuit ISP Vector table address generator Standby release signal 27 µPD780016Y, 780018Y Figure 6-1. Interrupt Function Basic Configuration (2/2) (D) External maskable interrupt (except INTP0) Internal bus External interrupt mode register (INTM0, INTM1) Interrupt request Edge detector MK IE PR ISP Priority control circuit IF Vector table address generator Standby release signal (E) Software interrupt Internal bus Interrupt request IF 28 : Interrupt request flag E : ISP : Interrupt enable flag In-service priority flag MK : PR : Interrupt mask flag Priority specification flag Priority control circuit Vector table address generator µPD780016Y, 780018Y 6.2 Test Functions Table 6-2 shows the two test functions available. Table 6-2. Test Input Factors Test Input Factor Name Trigger Internal/ External INTWT Overflow of watch timer Internal INTPT4 Detection of falling edge of port 4 External Figure 6-2. Basic Configuration of Test Function Internal bus MK Test input signal IF IF : Test input flag MK : Test mask flag Standby release signal 29 µPD780016Y, 780018Y 7. EXTERNAL DEVICE EXPANSION FUNCTIONS The external device expansion functions connect external devices to areas other than the internal ROM, RAM and SFR. External devices connection uses ports 4 to 6 and port 8. The external device expansion function has the following two modes: • Separate bus mode : External devices are connected by using an independent address bus and data bus. Because an external latch circuit is not necessary, this mode is effective for reducing the number of components and the mounting area on a printed wiring board. • Multiplexed bus mode : External devices are connected by using a time-division multiplexed address/data bus. This mode is useful for reducing the number of ports used when external devices are connected. 8. STANDBY FUNCTION The standby function intends to reduce current consumption. It has the following three modes: • HALT mode : In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. • Main STOP mode : In this mode, oscillation of the main system clock is stopped. The power consumption • Sub-STOP mode : In this mode, oscillation of the subsystem clock is stopped. The whole operation is can be reduced because the whole internal circuit is stopped. stopped and the power is consumed very little. Figure 8-1. Standby Function CSS = 1 Main system clock operation Subsystem clock operationNote CSS = 0 Interrupt request STOP instruction Interrupt request STOP mode (Oscillation of the main system clock is stopped.) Note HALT instruction HALT instruction Reset HALT mode (Supply of clock to CPU is stopped although clock is generated.) STOP instructon Interrupt request Sub-STOP mode (Oscillation of the main system clock and subsystem clock is stopped.) Note HALT mode (Supply of clock to CPU is stopped although clock is generated.) Current consumption is reduced by shutting off the main system clock. If the CPU is operating on subsystemclock, shut off the main system clock by setting MCC. You cannot use a STOP instruction in HALT mode. Cautions 1. The main stop mode can be used only when the main system clock is being operated. (The oscillation of the subsystem clock cannot be stopped.) 2. When switching on the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to provide enough time for the generation to be stable with the program first. 30 µPD780016Y, 780018Y 9. RESET FUNCTION There are the following two reset methods. • External reset input by RESET pin • Internal reset by watchdog timer inadvertent program loop time detection 31 µPD780016Y, 780018Y 10. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 2nd Operand #byte A rNote sfr saddr !addr16 PSW [DE] MOV MOV XCH [HL] 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP [HL + byte] [HL + B] $addr16 [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP None ROR ROL RORC ROLC MOV ADD ADDC SUB SUBC AND OR XOR CMP B, C 1 INC DEC DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV !addr16 DBNZ INC DEC MOV PSW MOV MOV [DE] MOV [HL] MOV [HL + byte] [HL + B] [HL + C] MOV PUSH POP ROR4 ROL4 X MULU C DIVUW Note 32 Except r = A µPD780016Y, 780018Y (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand 1st Operand #word AX AX ADDW SUBW CMPW rp MOVW MOVWNote sfrp MOVW MOVW saddrp MOVW MOVW MOVW MOVW !addr16 sfrp MOVW XCHW MOVW saddrp MOVW !addr16 MOVW SP None MOVW INCW, DECW PUSH, POP MOVW SP Note rpNote Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd Operand 1st Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 (4) Call instructions/Branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand AX 1st Operand Basic instruction BR !addr16 CALL BR Compound instruction !addr11 CALLF [addr5] CALLT $addr16 BR, BC BNC BZ, BNZ BT, BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 33 µPD780016Y, 780018Y 11. PACKAGE DRAWINGS 100 PIN PLASTIC QFP (14 × 20) A B Q F G H I M 5°±5° 31 30 S 100 1 detail of lead end D 51 50 C 80 81 J M P K N L P100GF-65-3BA1-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 34 ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 0.8 0.031 G 0.6 0.024 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8 ± 0.2 0.071+0.008 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. µPD780016Y, 780018Y APPENDIX A. DEVELOPMENT TOOLS The following tools are available for system development using the µPD780016Y and 780018Y. Language Processing Software RA78K/0Notes 1, 2, 3, 4 Assembler package used in common for the 78K/0 series CC78K/0Notes 1, 2, 3, 4 C compiler package used in common for the 78K/0 series DF780018Notes 1, 2, 3, 4, 8 Device file used in common for the µPD780018 subseries CC78K/0–LNotes 1, 2, 3, 4 C compiler library source file used in common for the 78K/0 series PROM Writing Tools PG-1500 PA-78P0018GF PROM programmer Note 8 PA-78P0018KL-T Programmer adapter connected to the PG-1500 Note 8 PG-1500 controllerNotes 1, 2 Control program for the PG-1500 Debugging Tools IE-78000-R In-circuit emulator used in common for the 78K/0 series IE-78000-R-ANote 8 In-circuit emulator used in common for the 78K/0 series (for integrated debugger) IE-78000-R-BK Break board used in common for the 78K/0 series IE-780018-R-EMNote 8 Emulation board used in common for the µPD780018 subseries EP-78064GF-R Emulation probe used in common for the µPD78064 subseries EV-9200GF-100 Socket mounted on the target system board prepared for 100-pin plastic QFP (GF-3BA type) EV-9900 Tool used for removing the µPD78P0018YKL-T from the EV-9200GF-100. SM78K0Notes 5, 6, 7 System simulator used in common for the 78K/0 series ID78K0Notes 4, 5, 6, 7, 8 Integrated debugger for IE-78000-R-A SD78K/0Notes 1, 2 Screen debugger for the IE-78000-R DF780018Notes 1, 2, 4, 5, 6, 7, 8 Device file used in common for the µPD780018 subseries 35 µPD780016Y, 780018Y Real-Time OS RX78K/0Notes 1, 2, 3, 4 MX78K0 Notes 1, 2, 3, 4 Real-time OS used for the 78K/0 series OS used for the 78K/0 series Fuzzy Inference Development Support System FE9000Note 1/FE9200Note 6 Fuzzy knowledge data creating tool FT9080Note 1/FT9085Note 2 Translator FI78K0Notes 1, 2 Fuzzy inference module FD78K0Notes 1, 2 Fuzzy inference debugger Notes 1. Based on PC-9800 series (MS-DOSTM) 2. Based on IBM PC/ATTM and compatible machines (PC DOSTM /IBM DOSTM/MS-DOS) 3. Based on HP9000 series 300TM (HP-UXTM) 4. Based on HP9000 series 700TM (HP-UX), SPARCstationTM (SunOSTM), and EWS-4800 series (EWS-UX/ V) 5. Based on PC-9800 series (MS-DOS + WindowsTM) 6. Based on IBM PC/AT and compatible machines (PC DOS/IBM DOS/MS DOS + Windows) 7. Based on NEWTM (NEWS-OSTM) 8. Under development Remarks 1. For development tools supplied by third-party manufacturers, refer to 78K/0 Series Selection Guide (U11126E). 2. Use the RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 in combination with the DF780018. 36 µPD780016Y, 780018Y APPENDIX B. RELATED DOCUMENTS Documents Related to Devices Document No. Document Japanese English µPD780018Y, 780018Y Subseries User’s Manual U11754J To be prepared µPD780016Y, 780018Y Preliminary Product Information U11810J This document µPD78P0018Y Preliminary Product Information U11603J To be prepared 78K/0 Series User’s Manual-Instruction IEU-849 IEU-1372 78K/0 Series Instruction Table U10903J — 78K/0 Series Instruction Set U10904J — To be prepared — µPD780018Y Subseries Special-Function Register Table Documents on Development Tools (User’s Manuals) Document No. Document RA78K Series Assembler Package Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 RA78K Series Structured Assembler Preprocessor EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Operation U11517J — Language U11518J — Programing Know-how EEA-618 EEA-1208 CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC-DOS) Base EEU-5008 U10540E IE-78000-R EEU-810 U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-780018-R-EM U11838J To be prepared EP-78064 EEU-934 EEU-1469 Reference U10181J U10181E External component user U10092J U10092E CC78K Series C Compiler CC78K0 C Compiler CC78K/0 C Compiler Application Note SM78K0 System Simulator Windows Base SM78K Series System Simulator open interface specification ID78K0 Integrated Debugger EWS Base Reference U11151J — ID78K0 Integrated Debugger PC Base Reference U11539J — ID78K0 Integrated Debugger Windows Base Guide U11649J — SD78K/0 Screen Debugger Introduction EEU-852 — PC-9800 Series (MS-DOS) Base Reference U10952J — SD78K/0 Screen Debugger Introduction EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Base Reference U11279J EEU-1413 Caution The above documents are subject to change without notice. Be sure to use the latest documents for design or for any other similar purpose. 37 µPD780016Y, 780018Y Documents on Embeded Software (User’s Manuals) Document No. Document 78K/0 Series Real-time OS 78K/0 Series OS MX78K0 Japanese English Basic U11537J — Installation U11536J — Technical U11538J — Fundamental Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series EEU-5010 — EEU-829 EEU-1438 EEU-862 EEU-1444 Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU-858 EEU-1441 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-921 EEU-1458 Other Documents Document Document No. Japanese IC Package Manual English C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System U10983J U10983E Electrostatic Discharge (ESD) Test MEM-539 — Semiconductor Device Quality Assurance Guide MEI-603 MEI-1202 Microcontroller-Related Product Guide – Third Party Products – U11416J — Caution The above documents are subject to change without notice. Be sure to use the latest documents for design or for any other similar purpose. 38 µPD780016Y, 780018Y [MEMO] 39 µPD780016Y, 780018Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 40 µPD780016Y, 780018Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 41 µPD780016Y, 780018Y Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. FIP is a trademark of NEC Corp. IEBus is a trademark of NEC Corp. MS-DOS and Windows are trademarks of Microsoft Corp. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corp. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett Packard Co. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corp. The related documents in this publication may include preliminary versions, but may not be marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5