AT91SAM9260 Microcontroller Schematic Check List 1. Introduction This application note is a schematic review check list for systems embedding the Atmel® ARM® Thumb®-based AT91SAM9260 microcontroller. It gives requirements concerning the different pin connections that must be considered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM9260. It does not consider PCB layout constraints. AT91 ARM Thumb-based Microcontrollers Application Note It also gives advice regarding low-power design constraints to minimize power consumption. This application note is not intended to be exhaustive. Its objective is to cover as many configurations of use as possible. The Check List table has a column reserved for reviewing designers to verify the line item has been checked. 6275F–ATARM–13-May-09 2. Associated Documentation Before going further into this application note, it is strongly recommended to check the latest documents for the AT91SAM9260 microcontroller on Atmel’s Web site. Table 2-1 gives the associated documentation needed to support full understanding of this application note. Table 2-1. 2 Associated Documentation Information Document Title User Manual Electrical/Mechanical Characteristics Ordering Information Errata AT91SAM9260 Product Datasheet Internal architecture of processor ARM/Thumb instruction sets Embedded in-circuit-emulator ARM9EJ-S™ Technical Reference Manual ARM926EJ-S™ Technical Reference Manual Evaluation Kit User Guide AT91SAM9260-EK Evaluation Board User Guide Using SDRAM on AT91SAM9 Microcontrollers Using SDRAM on AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers Application Note 6275F–ATARM–13-May-09 Application Note 3. Schematic Check List CAUTION: The AT91SAM9 board design must comply with the power-up and power-down sequence guidelines provided in the Electrical Characteristics section in the datasheet to guarantee reliable operation of the device. 1.8V and 3.3V Dual Power Supply with 3.3V Powered Memories Schematic Example 100nF VDDANA GNDANA 100nF VDDIOP1 GND VDDIOP0 10µF DC/DC Converter 100nF GND VDDIOM 3.3V 10µF 100nF GND 100nF VDDPLL GNDPLL 100nF VDDBU DC/DC Converter GNDBU VDDCORE 1.8V 10µF 100nF GND 1.8V and 3.3V Dual Power Supply Schematic Example:(1) 3.3V external memories (VDDIOM) - 3.3V Image Sensor (VDDIOP1) - ADC (VDDANA) is used 3 6275F–ATARM–13-May-09 ; Signal Name Recommended Pin Connection Description VDDCORE 1.65V to 1.95V Decoupling/Filtering capacitors (100 nF and 10µF)(1)(2) VDDPLL 1.65V to 1.95V Decoupling capacitor (100 nF)(1)(2) Powers the PLL cells and the Main Oscillator. VDDBU 1.65V to 1.95V Decoupling capacitor (100 nF)(1)(2) Powers the Backup I/O lines (Slow Clock Oscillator and a part of the System Controller). Powers the device. Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. Powers External Bus Interface I/O lines. VDDIOM(3) 1.65V to 1.95V or 3.0V to 3.6V Decoupling/Filtering capacitors (100 nF and 10µF)(1)(2) Dual voltage range supported. The voltage ranges are selected by programming the VDDIOMSEL bit in the EBI_CSA register. At power-up, the selected voltage is 3.3V nominal, and power supply pins can accept either 1.8V or 3.3V. Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VDDIOP0(3) 3.0V to 3.6V Decoupling/Filtering capacitors (100 nF and 10µF)(1)(2) VDDIOP1(3) 1.65V to 3.6V Decoupling/Filtering capacitors (100 nF and 10µF)(1)(2) Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. Powers Peripheral I/O lines involving the Image Sensor Interface (ISI). Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. 3.0V to 3.6V Decoupling capacitor (100 nF)(1)(2) Application dependent Powers the Analog to Digital Converter (ADC) and some PIOC I/O lines. GND Ground GND pins are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins. GND pins should be connected as shortly as possible to the system ground plane. GNDBU Backup Ground GNDBU pin is provided for VDDBU pin. GNDBU pin should be connected as shortly as possible to the system ground plane. GNDPLL PLL and Main Oscillator Ground GNDPLL pin is provided for VDDPLL pin. GNDPLL pin should be connected as shortly as possible to the system ground plane. GNDANA Analog Ground GNDANA pin is provided for VDDANA pin. GNDANA pin should be connected as shortly as possible to the system ground plane. VDDANA 4 Powers Peripheral I/O lines and USB transceivers. Application Note 6275F–ATARM–13-May-09 Application Note ; Signal Name Recommended Pin Connection Description Clock, Oscillator and PLL Crystal Load Capacitance to check (CCRYSTAL). AT91SAM9260 XOUT XIN GNDPLL Crystals between 3 and 20 MHz XIN XOUT Main Oscillator in Normal Mode Capacitors on XIN and XOUT (crystal load capacitance dependent) 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHz. 1K CCRYSTAL CLEXT CLEXT Example: for an 18.432 MHz crystal with a load capacitance of CCRYSTAL= 17.5 pF, external capacitors are required: CLEXT = 12 pF. Refer to the electrical specifications of the AT91SAM9260 datasheet. XIN XOUT Main Oscillator in Bypass Mode XIN: external clock source XOUT: can be left unconnected 1.8V Square wave signal (VDDPLL) External Clock Source up to 50 MHz Duty Cycle: 40 to 60% Refer to the electrical specifications of the AT91SAM9260 datasheet. 5 6275F–ATARM–13-May-09 ; Signal Name Recommended Pin Connection Description Crystal Load Capacitance to check (CCRYSTAL32). AT91SAM9260 XIN32 XIN32 XOUT32 Slow Clock Oscillator 32.768 kHz Crystal XOUT32 GNDBU C CRYSTAL32 Capacitors on XIN32 and XOUT32 (crystal load capacitance dependent) CLEXT32 CLEXT32 Example: for an 32.768 kHz crystal with a load capacitance of CCRYSTAL32= 12.5 pF, external capacitors are required: CLEXT32 = 17pF. Refer to the electrical specifications of the AT91SAM9260 datasheet. See the Excel spreadsheet: “ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx.zip” (available in the software files on the Atmel Web site) allowing calculation of the best R-C1-C2 component values for the PLL Loop Back Filter. PLLRC Second-order filter PLL PLLRCA R Can be left unconnected if PLL not used. C2 C1 GNDPLL R, C1 and C2 must be placed as close as possible to the pins. OSCSEL 6 Application dependent. Please refer to the I/O line considerations and errata section of the AT91SAM9260 datasheet. Slow Clock Oscillator Selection. Must be tied to VVDDBU to select the external 32,768 Hz crystal. Must be tied to GNDBU to select the on-chip RC oscillator. Application Note 6275F–ATARM–13-May-09 Application Note ; Signal Name Recommended Pin Connection Description ICE and JTAG(4) TCK Pull-up (100 kOhm)(1) This pin is a Schmitt trigger input. No internal pull-up resistor. TMS Pull-up (100 kOhm)(1) This pin is a Schmitt trigger input. No internal pull-up resistor. TDI Pull-up (100 kOhm)(1) This pin is a Schmitt trigger input. No internal pull-up resistor. TDO Floating Output driven at up to VVDDIOP0 RTCK Floating Output driven at up to VVDDIOP0 NTRST Can be left unconnected. It is strongly recommended to tie this pin to VDDIOP0 in harsh(5) environments. Internal pull-up resistor to VVDDIOP0 (100 kOhm). JTAGSEL In harsh environments,(5) It is strongly recommended to tie this pin to GNDBU if not used or to add an external lowvalue resistor (such as 1 kOhm). Internal pull-down resistor to GNDBU (15 kOhm). Must be tied to VVDDBU to enter JTAG Boundary Scan. Reset/Test NRST is configured as an output at power up. NRST Application dependent. Can be connected to a push button for hardware reset. TST In harsh environments,(5) It is strongly recommended to tie this pin to GNDBU if not used or to add an external lowvalue resistor (such as 1 kOhm). Internal pull-down resistor to GNDBU (15 kOhm). BMS Application dependent. Must be tied to VVDDIOP0 to boot on Embedded ROM. Must be tied to GND to boot on external memory (EBI Chip Select 0). NRST is controlled by the Reset Controller (RSTC). An internal pull-up resistor to VVDDIOP0 (100 kOhm) is available for User Reset and External Reset control. Shutdown/Wakeup Logic Application dependent. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies. SHDN An external pull-up to VDDBU is needed and its value is to be higher than 1 MOhm. The resistor value is calculated according to the regulator enable implementation and the SHDN level. WKUP 0V to VVDDBU The SHDN pin is a tri state output. No internal pull-up resistor. An external pull-up to VDDBU is needed. SHDN pin is driven low to GNDBU by the Shutdown Controller (SHDWC). This pin is an input-only. WKUP behavior can be configured through the Shutdown Controller (SHDWC). 7 6275F–ATARM–13-May-09 ; Signal Name Recommended Pin Connection Description PIO PAx PBx PCx All PIOs are pulled-up inputs at reset except those which are multiplexed with the Address Bus signals that require to be enabled as peripherals: PC4 (A23), PC5 (A24) and PC10 (A25). Application dependent To reduce power consumption if not used, the concerned PIO can be configured as an output, driven at ‘0’ with internal pull-up disabled. ADC ADVREF 2.4V to VVDDANA Decoupling/Filtering capacitors. Application dependent ADVREF is a pure analog input. To reduce power consumption, if ADC is not used: connect ADVREF to GNDANA. EBI D0-D15 (D16-D31) Data Bus (D0 to D31) Data Bus lines D0 to D15 are pulled-up inputs to VVDDIOM at reset. Application dependent Note: Data Bus lines D16 to D31 are multiplexed with the PIOC controller. Their I/O line reset state is input with pull-up enabled too. Address Bus (A0 to A25) All Address Lines are driven to ‘0’ at reset. A0-A22 (A23-A25) Application dependent Note: A23 (PC4), A24 (PC5) and A25 (PC10) are enabled by default at reset through the PIO controllers. SMC - SDRAM Controller - CompactFlash Support - NAND Flash Support See “External Bus Interface (EBI) Hardware Interface” on page 11. 8 Application Note 6275F–ATARM–13-May-09 Application Note ; Signal Name Recommended Pin Connection Description USB Host (UHP) HDPA HDPB Application dependent(6) Internal pull-down resistors. Refer to the electrical specifications of the AT91SAM9260 datasheet. HDMA HDMB Application dependent(6) Internal pull-down resistors. Refer to the electrical specifications of the AT91SAM9260 datasheet. USB Device (UDP) DDP Application dependent(7) Integrated programmable pull-up resistor (UDP_TXVC) Integrated pull-down resistor to prevent over consumption when t he host is disconnected. To reduce power consumption, if USB Device is not used, DDP must be left unconnected. Integrated pull-down resistor to prevent over consumption when t he host is disconnected. DDM Application dependent(7) To reduce power consumption, if USB Device is not used, DDM must be left unconnected. Notes: 1. These values are given only as a typical example. 2. Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin. 100nF VDDCORE 100nF VDDCORE 100nF VDDCORE GND 3. The power supplies VDDIOM and VDDIOP0 and VDDIOP1 power the device differently when interfacing with memories or with peripherals. 4. It is recommended to establish accessibility to a JTAG connector for debug in any case. 5. In a well-shielded environment subject to low magnetic and electric field interference, the pin may be left unconnected. In noisy environments, a connection to ground is recommended. 9 6275F–ATARM–13-May-09 6. Example of USB Host connection: A termination serial resistor (REXT) must be connected to HDPA/HDPB and HDMA/HDMB. A recommended resistor value is defined in the electrical specifications of the AT91SAM9260 datasheet. 5V 0.20A Type A Connector 10μF HDMA or HDMB 100nF 10nF REXT HDPA or HDPB REXT 7. Example of USB Device connection: As there is an embedded pull-up, no external circuitry is necessary to enable and disable the 1.5 kOhm pull-up. Internal pull-downs on DDP and DDM are embedded to prevent over consumption when t he host is disconnected. A termination serial resistor (REXT) must be connected to DDP and DDM. A recommended resistor value is defined in the electrical specifications of the AT91SAM9260 datasheet. PIO 5V Bus Monitoring 27 K 47 K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 10 Application Note 6275F–ATARM–13-May-09 Application Note 4. External Bus Interface (EBI) Hardware Interface Table 4-1 and Table 4-2 detail the connections to be applied between the EBI pins and the external devices for each Memory Controller: Table 4-1. EBI Pins and External Static Devices Connections Pins of the Interfaced Device Signals: EBI_ 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device Controller 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device SMC D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D8 - D15 – D8 - D15 D8 - D15 D8 - D15 D8 - 15 D8 - 15 D16 - D23 – – – D16 - D23 D16 - D23 D16 - D23 D24 - D31 – – – D24 - D31 D24 - D31 D24 - D31 BE0(5) A0/NBS0 A0 – NLB – A1/NWR2/NBS2 A1 A0 A0 WE(2) NLB(4) BE2(5) A2 - A22 A[2:22] A[1:21] A[1:21] A[0:20] A[0:20] A[0:20] A23 - A25 A[23:25] A[22:24] A[22:24] A[21:23] A[21:23] A[21:23] NCS0 CS CS CS CS CS CS NCS1/SDCS CS CS CS CS CS CS NCS2 CS CS CS CS CS CS NCS3/NANDCS CS CS CS CS CS CS NCS4/CFCS0 CS CS CS CS CS CS NCS5/CFCS1 CS CS CS CS CS CS NRD/CFOE OE OE OE OE OE OE WE WE NWR0/NWE WE WE (1) (1) NWR1/NBS1 – WE NWR3/NBS3 – – Notes: WE NUB – NLB (3) WE (2) WE (2) WE(2) (3) BE1(5) NUB(4) BE3(5) NUB 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2. NWRx enables corresponding byte x writes. (x = 0, 1, 2 or 3) 3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. 5. BEx: Byte x Enable (x = 0,1,2 or 3) 11 6275F–ATARM–13-May-09 Table 4-2. EBI Pins and External Device Connections Pins of the Interfaced Device Signals: EBI_ SDRAM(3) Controller SDRAMC CompactFlash (EBI only) CompactFlash True IDE Mode (EBI only) NAND Flash(4) SMC D0 - D7 D0 - D7 D0 - D7 D0 - D7 I/O0-I/O7 D8 - D15 D8 - D15 D8 - 15 D8 - 15 I/O8-I/O15(5) D16 - D31 D16 - D31 – – – A0/NBS0 DQM0 A0 A0 – A1/NWR2/NBS2 DQM2 A1 A1 – A2 - A10 A[0:8] A[2:10] A[2:10] – A11 A9 – – – SDA10 A10 – – – – – – – A[11:12] – – – – – – – A16/BA0 BA0 – – – A17/BA1 BA1 – – – A18 - A20 – – – – A21 – – – ALE A22 – REG REG CLE A23 - A24 – – A12 A13 - A14 A15 – – (1) A25 – NCS0 – – – – CS – – – NCS2 – – – – NCS3/NANDCS – – – CE(6) NCS4/CFCS0 – CFCS0(1) CFCS0(1) – NCS5/CFCS1 – (1) (1) – NANDOE – – – RE NANDWE – – – WE NRD/CFOE – OE – – NWR0/NWE/CFWE – WE WE – NWR1/NBS1/CFIOR DQM1 IOR IOR – NWR3/NBS3/CFIOW DQM3 IOW IOW – CFCE1 – CE1 CS0 – CFCE2 – CE2 CS1 – SDCK CLK – – – NCS1/SDCS 12 CFRNW (1) CFCS1 CFRNW CFCS1 – Application Note 6275F–ATARM–13-May-09 Application Note Table 4-2. EBI Pins and External Device Connections (Continued) Pins of the Interfaced Device Signals: EBI_ SDRAM(3) Controller SDRAMC CompactFlash (EBI only) CompactFlash True IDE Mode (EBI only) NAND Flash(4) SMC SDCKE CKE – – – RAS RAS – – – CAS CAS – – – SDWE WE – – – NWAIT – WAIT WAIT – Pxx (2) – CD1 or CD2 CD1 or CD2 – Pxx (2) – – – CE(6) – – – RDY Pxx(2) Notes: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 3. For SDRAM connection examples, See Using SDRAM on AT91SAM9 Microcontrollers application note. 4. For NAND Flash connection examples, See NAND Flash Support in AT91SAM9 Microcontrollers application note. 5. I/O8 - I/O15 bits used only for 16-bit NAND Flash. 6. CE connection depends on the NAND Flash. For standard NAND Flash devices, it must be connected to any free PIO line. For “CE don’t care” NAND Flash devices, it can be connected either to NCS3/NANDCS or to any free PIO line. 13 6275F–ATARM–13-May-09 5. AT91SAM Boot Program Hardware Constraints See the AT91SAM Boot Program section of the AT91SAM9260 datasheet for more details on the boot program. 5.1 5.1.1 AT91SAM Boot Program Supported Crystals and Input Frequencies On-chip RC Selected (OSCSEL=0) If the Internal RC Oscillator is used (OSCSEL = 0) and the Main Oscillator is active: Table 5-1. Supported Crystals (MHz) 3.0 6.0 18.432 Other Crystal Boot on DBGU Yes Yes Yes Yes Boot on USB Yes Yes Yes No Note: Any other crystal can be used but it prevents using the USB for SAM-BA Boot. If the Internal RC Oscillator is used (OSCSEL = 0) and the Main Oscillator is bypassed: Table 5-2. 1.0 2.0 6.0 12.0 25.0 50.0 Other Frequency Boot on DBGU Yes Yes Yes Yes Yes Yes Yes Boot on USB Yes Yes Yes Yes Yes Yes No Note: 5.1.2 Any other input frequency can be used but it prevents using the USB for SAM-BA Boot. External 32,768 Hz Crystal Selected (OSCSEL=1) If an external 32,768 Hz Oscillator is used (OSCSEL = 1) and the Main Oscillator is active: Table 5-3. Supported Crystals (MHz) 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 17.734470 18.432 20.0 - Note: 14 Supported Input Frequencies (MHz) Booting either on USB or on DBGU is possible with any of these crystals. Application Note 6275F–ATARM–13-May-09 Application Note If an external 32,768 Hz Oscillator is used (OSCSEL = 1) and the Main Oscillator is bypassed: Table 5-4. 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 17.734470 18.432 20.0 24 25 28.224 32 33 - Note: 5.2 Supported Input Frequencies (MHz) Booting either on USB or on DBGU is possible with any of these input frequencies. SAM-BA Boot The SAM-BA™ Boot Assistant supports serial communication via the DBGU or the USB Device Port. Table 5-5. 5.3 Pins Driven during SAM-BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PB14 DBGU DTXD PB15 DataFlash® Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory. The DataFlash must be connected to NPCS0 or NPCS1 of the SPI0. Table 5-6. 5.4 Pins Driven during DataFlash Boot Program Execution Peripheral Pin PIO Line SPI0 MOSI PA1 SPI0 MISO PA0 SPI0 SPCK PA2 SPI0 NPCS0 PA3 SPI0 NPCS1 PC11 NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory. Table 5-7. Pins Driven during NAND Flash Boot Program Execution Peripheral Pin PIO Line PIOC PIOC14 (for NAND Chip Select) PC14 PIOC PIOC13 (for NAND Ready Busy) PC13 Address Bus NAND CLE A22 Address Bus NAND ALE A21 15 6275F–ATARM–13-May-09 Revision History Table 5-8. Revision History Comments Change Request Ref. Add a Caution paragraph before “Schematic Check List” table 6124 Edit SHDN line in “Schematic Check List” table 6026 - 6149 6275E Updated Recommended Pin Connection for “VDDANA”, “OSCSEL”, “JTAGSEL”, “TST” Updated descriptiion for “ADVREF” 5074/4732 6275D Changed information on internal pull-down resistors for HDPA, HDPB, HDMA, HDMB on page 9. 4207 6275C Updated Main Oscillator description and figure on page 5 and Slow Clock Oscillator description and figure on page 6. OSCSEL, JTAGSEL and BMS pin descriptions updated on page 6 and page 7. Updated HDPA, HDPB, HDMA, HDMB pin descriptions on page 9. Removed resistors from schematic in Note (6) on page 10. Doc. Rev 6275F 6275B 6275A 16 Updated description and schematic for XIN and XOUT pin on page 5. Updated description and schematic for XIN32 and XOUT32 pin on page 6. Updated description of BMS pin on page 7. Updated description of ADVREF pin on page 8. Updated description of DDP and DDM pins on page 9. Added details to schematic 1.8V and 3.3V Dual Power Supply with 3.3V Powered Memories Schematic Example3. Added details on harsh environment in Footnote (5) on page 9. Added details on connection example for CE don’t care NAND Flash in Footnote (6) on page 13. Corrected PIO denomination in Section 5.2 “SAM-BA Boot” , Section 5.3 “DataFlash® Boot” and Section 5.4 “NAND Flash Boot” . 4067 4202 3929 3822 3824 3891 3916 First issue Application Note 6275F–ATARM–13-May-09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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