APPLICATION NOTE AT06609: Differences between ATmega48/88/168 Variants and the New ATmega48/88/168PB Atmel megaAVR Introduction ® This application note is a guide to assist users of the Atmel ATmega48/88/168 variants in starting to use the Atmel ATmega48/88/168PB. ATmega48/88/168PB is not a drop in replacement for ATmega48/88/168 variants, but a brand new product. However, new functions are implemented as a superset of existing ATmega48/88/168 functions. Existing code for these devices will thus work in the new devices without changing existing configuration or enabling new functions. For complete device details, refer to the most recent version of the ATmega48/88/168PB datasheet. Errata differences, typical characteristic changes between ATmega48/88/168 variants and ATmega48/88/168PB are not listed in this document; refer to the relevant device datasheets. Features • Pin functionality difference • Code compatibility • Enhancement and added features Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014 1 Pin Functionality Difference 1.1 Added/Modified Pin Functionality Four additional GPIOs are added to PORTE [3:0]. GPIO pins PE2 and PE3 are added to Pin19 and Pin22. PE2 and PE3 are multiplexed with ADC6 and ADC7. Pin3 (GND) and Pin6 (VCC) are replaced by PE0 and PE1 respectively. PE0 is multiplexed with ACO. Table 1-1. Pin Functionality Difference between ATmega48/88/168 Variants and ATmega48/88/168PB 32-pin TQFP/MLF package 1.2 ATmega48/88/168 variants ATmega48/88/168PB Pin3 GND PE0/ACO Pin6 VCC PE1 Pin19 ADC6 ADC6/PE2 Pin22 ADC7 ADC7/PE3 Alternate Pin Configuration The alternate pin configurations are: • ADC7– Port E, Bit 3 PE3 can also be used as ADC input channel 7. Note that ADC input channel 7 uses analog power AVCC. • ADC6 – Port E, Bit 2 PE2 can also be used as ADC input channel 6. Note that ADC input channel 6 uses analog power AVCC. • None – Port E, Bit 1 No alternate function. • ACO – Port E, Bit 0 ACO Analog Compare Output pin is multiplexed with PE0. 1.3 Register Description 1.3.1 PINE – The Port E Input Pins Address Bit 1.3.2 2 7 6 4 3 2 1 0 − − PINE 3 PINE 2 PINE 1 PINE 0 R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0x0C (0x2C) − − Read/Write R Initial value 0 5 PINE DDRE – The Port E Data Direction Register Bit 7 6 5 4 3 2 1 0 0x0D (0x2D) − − − − DDE3 DDE2 DDE1 DDE0 Read/Write R R R R R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 AT06609: Differences between ATmega48/88/168 and the New ATmega48/88/168PB [APPLICATION NOTE] Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014 DDRE 1.3.3 PORTE – The Port E Data Register Bit 2 7 6 5 4 3 2 1 0 0x0E (0x2E) − − − − PORTE3 PORTE2 PORTE1 PORTE0 Read/Write R R R R R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PORTE Code Compatibility ATmega48/88/168 variants are code compatible with ATmega48/88/168PB devices. Code compiled for ATmega48/88/168 variants will execute the same in the ATmega48/88/168PB device whereas reverse code compatibility is not guaranteed. 3 Enhancement and Added Features This section summarizes the enhancements or added features in ATmega48/88/168PB compared with ATmega48/88/168 variants. 3.1 • USART start frame detection is available in all sleep modes • Analog Comparator output is available on a pin. This pin is multiplexed with PE0. • Unique device ID to identify the device USART In addition to the existing wake up modes, USART start-of-frame detection can also wake up the MCU from all sleep modes when a start bit is detected. When a high-to-low transition is detected on RxDn, the internal 8MHz oscillator is powered up and the USART clock is enabled. After start-up the rest of the data frame can be received, provided that the baud rate is slow enough to allow the internal 8MHz oscillator to start up. Start-up time of the internal 8MHz oscillator varies with supply voltage and temperature. The USART start frame detection works both in asynchronous and synchronous modes. It is enabled by writing a one to the Start Frame Detection Enable bit (SFDE) in “UCSRD – USART Control and Status Register D”. If the USART RX Start- Interrupt Enable (RXSIE) bit is set, the USART Receive Start Interrupt is generated immediately when a start is detected. When using the feature without the Receive Start Interrupt, the start detection logic activates the internal 8MHz oscillator and the USART clock while the frame is being received only. Other clocks remain stopped until the Receive Complete Interrupt optionally wakes up the MCU. The maximum baud rate in synchronous mode depends on the sleep mode the device is woken up from, as follows: • Idle or ADC Noise Reduction sleep mode: system clock frequency divided by four • Standby or Power-down: 500kbps The maximum baud rate in asynchronous mode depends on the sleep mode the device is woken up from, as follows: • Idle sleep mode: the same as in active mode AT06609: Differences between ATmega48/88/168 and the New ATmega48/88/168PB [APPLICATION NOTE] Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014 3 3.1.1 UCSRD – USART Control and Status Register D Bit (0xC3) 7 6 5 4 3 2 1 0 RXSIE RXS SFDE − − − − − Read/Write R/W R/W R/W R R R R R Initial value 0 0 1 0 0 0 0 0 UCSRD Bit 7 – RXSIE: USART RX Start Interrupt Enable • Writing this bit to one enables the interrupt on the RXS flag. In sleep modes this bit enables start frame detector that can wake up the MCU when a start condition is detected on the RxD line. The USART RX Start Interrupt is generated only, if the RXSIE bit, the Global Interrupt Enable flag, and RXS are set. Bit 6 – RXS: USART RX Start • The RXS flag is set when a start condition is detected on the RxD line. If the RXSIE bit and the Global Interrupt Enable flag are set, an RX Start Interrupt will be generated when this flag is set. The flag can only be cleared by writing a logical one to the RXS bit location. If the start frame detector is enabled (RXSIE = 1) and the Global Interrupt Enable Flag is set, the RX Start Interrupt will wake up the MCU from power down mode. Bit 5 – SFDE: Start Frame Detection Enable • Writing this bit to one enables the USART Start Frame Detection mode. The start frame detector is able to wake up the MCU from sleep mode when a start condition, i.e. a high (IDLE) to low (START) transition, is detected on the RxD line. Table 3-1. 3.2 USART Start Frame Detection Modes SFDE RXSIE RXSIE (RX complete interrupt enable) 0 X X Start frame detection disabled 1 0 0 Reserved 1 0 1 Start frame detector enabled. RXC flag wakeup the MCU from all sleep mode 1 1 0 Start of frame detector enabled. RXS flag wakeup the MCU from all sleep mode Description Analog Comparator Analog comparator output is available on a pin. The analog comparator’s output is tied to PE0 when the AC output is enabled by writing a one to the Analog Comparator Output Enable bit (ACOE) in “ACSR0 – Analog Comparator Output Control Register”. 3.2.1 Analog Comparator Output Control Register Bit 7 6 5 4 3 2 1 0 0x2F (0x4F) − − − − − − − ACOE Read/Write R R R R R R R R/W Initial value 0 0 0 0 0 0 0 0 • ACSR0 Bit 7:1 – Reserved These bits are unused bits in the Atmel ATmega48PB/88PB/168PB, and will always read as zero. • Bit 0 – ACOE: Analog Comparator Output Enable Setting this bit makes the output of AC available on PE0. If this bit is not set, PE0 can be used as general I/O pin. 4 AT06609: Differences between ATmega48/88/168 and the New ATmega48/88/168PB [APPLICATION NOTE] Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014 3.3 Unique Device ID In Atmel ATmega48/88/168PB, a unique device ID is now accessible through I/O registers. Reads from I/O address 0xF0 - 0xF8 will return a unique device ID. The ID is made from concatenating the nine bytes read out from these registers. These registers are read only. 3.3.1 DEVID0 – Device ID byte 0 Bit 7 6 5 R R R R R R R x x x x x x x 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R Initial value x x x x x x x x 6 5 4 3 2 1 0 DEVID1 – Device ID byte 1 Device ID byte1[7:0] DEVID1 DEVID2 – Device ID byte 2 7 Device ID byte2[7:0] DEVID2 Read/Write R R R R R R R R Initial value x x x x x x x x 6 5 4 3 2 1 0 DEVID3 – Device ID byte 3 Bit 7 Device ID byte3[7:0] 0xF3 DEVID3 Read/Write R R R R R R R R Initial value x x x x x x x x 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R Initial value x x x x x x x x 6 5 4 3 2 1 0 DEVID4 – Device ID byte 4 Bit Device ID byte4[7:0] 0xF4 DEVID4 DEVID5 – Device ID byte 5 Bit 7 Device ID byte5[7:0] 0xF5 3.3.7 DEVID0 x 0xF2 3.3.6 0 R Bit 3.3.5 1 Initial value 0xF1 3.3.4 2 Read/Write Bit 3.3.3 3 Device ID byte0[7:0] 0xF0 3.3.2 4 DEVID5 Read/Write R R R R R R R R Initial value x x x x x x x x 6 5 4 3 2 1 0 DEVID6 – Device ID byte 6 Bit 7 Device ID byte6[7:0] 0xF6 DEVID6 Read/Write R R R R R R R R Initial value x x x x x x x x AT06609: Differences between ATmega48/88/168 and the New ATmega48/88/168PB [APPLICATION NOTE] Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014 5 3.3.8 DEVID7 – Device ID byte 7 Bit 7 6 5 0xF7 3.3.9 3 2 1 0 DEVID7 Read/Write R R R R R R R R Initial value x x x x x x x x 6 5 4 3 2 1 0 DEVID8 – Device ID byte 8 Bit 7 Device ID byte8[7:0] 0xF8 4 4 Device ID byte7[7:0] DEVID8 Read/Write R R R R R R R R Initial value x x x x x x x x Other Related Documents Refer the following migration notes to know the changes between Atmel ATmega48/88/168 and ATmega48/88/168P, ATmega48/88/168P and ATmega48/88/168PA. Atmel AVR512: Migration from ATmega48/88/168 to ATmega48P/88P/168P Atmel AVR528: Migration from ATmega48/88/168P to ATmega48/88/168PA 6 AT06609: Differences between ATmega48/88/168 and the New ATmega48/88/168PB [APPLICATION NOTE] Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014 5 Revision History Doc Rev. Date 42374A 10/2014 Comments Initial document release. AT06609: Differences between ATmega48/88/168 and the New ATmega48/88/168PB [APPLICATION NOTE] Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014 7 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2014 Atmel Corporation. / Rev.:Atmel-42374A-Differences-between-ATmega48/88/168-Variants-and-the-New-ATmega48/88/168PB_APNote_AT06609_102014. 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