APPLICATION NOTE AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I Atmel AVR XMEGA Introduction This application note lists out the differences and changes between Revision E ® and Revision I of Atmel ATxmega16D4/32D4 devices. For complete device details, always refer to the most recent version of the ® ATxmega16D4/32D4 datasheet and the Atmel XMEGA D manual. Errata differences are not listed in this document, only in the device datasheet. In addition to the differences described in this document, other typical characteristics could be different. Check the latest datasheets for details. The new configuration options and functions available in Revision I of ATxmega16D4/32D4 are a superset of existing functions, and this means that existing code for these revisions will work on the new revision without changing existing configuration or enabling new functions. Features • Enhancements and added functions • Memories • System clock and clock options • Reset system • I/O ports • Registers • Changes in electrical characteristics Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 1 Enhancements and Added Functions In this chapter, we summarize the list of enhancements or added features available in the Revision I of the Atmel ATxmega16D4/32D4. 1.1 Clock System • • • • • • Alternate pin location for TOSC1 and TOSC2 pins for 32.768kHz crystal connection on devices with shared TOSC and XTAL location A divide-by-two option for the PLL output that enables output frequency down to 10MHz PLL lock failure detection with optionally Non-Maskable Interrupt (NMI), for improved safety and robustness Non-prescaled Real Time Counter clock source options: External clock from TOSC1, 32.768kHz from TOSC, and the 32.768kHz from the 32.768kHz internal oscillator Higher drive option for external crystal oscillator to support crystals with higher load The 32MHz internal oscillator can be tuned to run at any frequency between 30MHz and 55MHz 1.2 I/O Ports 1.3 Two-wire Interface 1.4 Analog to Digital Converter 1.5 Analog Comparator 1.6 CRC16/CRC32 Generator 1.7 16-bit Timer/Counter 0 1.8 High Resolution Extension 1.9 Power Management 2 AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] • • • • • • • • • • • • • • • • Alternate pin locations for Timer/Counter 0 Compare Channels, USART0 and SPI Alternate pin locations for the Peripheral Clock and Event output functions The Real Time Counter clock can be output to a port pin Any Event Channel can be output to a port pin The SDA Hold time can be increased and configured in order to be SMBUS compliant Automatic input channel scan VCC/2 voltage reference option 1/2x (divide-by-two) gain stage setting Internal Ground can be used as negative input in differential mode with and without gain Sample time is configurable Analog Comparator 1 can be output on a port pin A constant current source ® A CRC16/CRC32 Generator Module that supports CRC16 (RC-CCITT) and CRC-32 (IEEE 802.3) Split mode that enable two 8-bit Timer/Counters with four PWM channels each Hi-Res+ option to allow PWM resolution to be increased with 8x (3-bit) Possibility to enable sequential start of the components used for analog modules ADC and Analog Comparator in order to reduce start-up current Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 2 Memories 2.1 NVM Controller For Atmel ATxmega16D4/32D4 Revision E devices, the chip erase time is about 40ms. The chip erase time of ATxmega32D4/16/D4 Revision I is longer. The typical chip erase time of ATxmega16D4/32D4 Revision I are listed in Table 2-1. Table 2-1. ATxmega16D4/32D4 Revision E Chip Erase Time Product Flash and Boot Code Size Chip Erase Time ATxmega16D4 16KB + 4KB 45ms ATxmega32D4 32KB + 4KB 50ms To ensure that the flash chip erase is finished correctly, no flash access should be done during the chip erase time. In the user code, it is always needed to check the FBUSY bit in the Non-Volatile Memory Status Register to see when the chip erase is finished. CRC32 is automatically used instead of existing CRC module if the new CRC16/CRC32 module is enabled. There is no change in the commands. 2.2 Fuses and Lock Bits BOD levels are different in ATxmega16D4/32D4 Revision I. See Section 4.1 Brown-out Detection for the differences. 3 System Clock and Clock Options 3.1 Clock Failure The PLLDFIF flag, indicating if the PLL looses lock, is no longer automatically cleared, but must be done from software. AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 3 4 Reset System 4.1 Brown-out Detection The programmable BODLEVEL settings are different in ATxmega16D4/32D4 Revision I. See Table 4-1 for details. Refer to the device datasheet regarding tolerance for the brown-out levels. Table 4-1. Brown-out Levels BODLEVEL VBOT – Revision E VBOT – Revision I 111 1.63V 1.6 V 110 1.9V 1.8 V 101 2.17V 2.0 V 100 2.43V 2.2 V 011 2.68V 2.4 V 010 2.96V 2.6 V 001 3.22V 2.8 V 000 3.49V 3.0 V For devices until Revision E, the BOD is forced on for all Non-Volatile Memory (NVM) programming. For the new Revision I, the BOD is only forced on during chip erase and when the PDI is enabled. For other NVM programming operations, the POR threshold voltage (V POT+) is the limit for aborting. 5 I/O Ports The I/O port pins are LV-TTL and LVCOMS compatible for Atmel ATxmega16D4/32D4 Revision I. The minimum “Input High Voltage” is never higher than 2.0V for VCC > 2.7V. In ATxmega16D4/32D4 Revision E, the minimum “Input High Voltage” is 0.7VCC, and could be higher than 2.0V for VCC > 2.86V. 5.1 I/O Pin Behavior when Disabling TX in USART When the transmitter is disabled in USART peripheral, it will no longer override the TxDn pin, and the pin direction is set as input automatically by hardware, even if it was configured as output by the user. This behavior as mentioned in the XMEGA D manual is valid from Revision I. In the previous revisions, the pin direction does not get changed to input automatically. 4 AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 6 Registers 6.1 Added Registers and Bits Table 6-1 lists the registers and bits, which has been added in the ATxmega16D4/32D4 Revision I. Table 6-1. Register Bits and Functionality added in the ATxmega16D4/32D4 Revision I Register Name Bit Function SAMPCTRL Bit[5:0] - SAMPVAL[5:0] Sampling time control register The SAMPVAL bits control the ADC sampling time in number of half ADC prescaled clock cycles (depends on ADC_PRESCALER value), thus controlling the ADC input impedance. Sampling time is set according to the formula: Sampling time = (SAMPVAL+1)*(ClkADC/2) 6.2 Removed Registers and Bits Table 6-2 lists the registers and bits, which exist in devices until Atmel ATxmega16D4/32D4 revision E but not in ATxmega16D4/32D4 Revision I. Table 6-2. 6.3 Register Bits and Functionality that does not exist in ATxmega16D4/32D4 Revision I Register Name Bit Function COMP0 COMP[7:0] Oscillator Compare Register 0 CALH Register Not Applicable For the ATxmega16D4/32D4 Revision I, CALH is not applicable hence it cannot be written. When read, the CALH register will return zero. This new design ATxmega16D4/32D4 ADC requires only one calibration byte (only 8 bit value not 12 bit value). For code compatibility with the earlier revisions, dependent registers like CALH, CALL, ADC CAL0, and ADC CAL1 has been kept same as the older design. AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 5 6.4 MUXNEG Configurations in ADC Channel MUX Control Register In the Revision E of the ATxmega16D4/32D4 devices, Bit 2 of the MUXNEG configuration in ADC Channel MUX Control registers is reserved. This bit is now available for configuration in the Revision I. Below are the configurations available in the older and latest revision: Revision E: Bit 7 +0x01 - Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 6-3. Table 6-4. 6 6 5 4 3 MUXPOS[3:0] 2 1 - 0 MUXNEG[1:0] MUXCTRL ADC MUXNEG Configuration, INPUTMODE[1:0] = 10, Differential without Gain MUXNEG[1:0] Group Configuration Analog Input 00 PIN0 ADC0 pin 01 PIN1 ADC1 pin 10 PIN2 ADC2 pin 11 PIN3 ADC3 pin ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with Gain MUXNEG[1:0] Group Configuration Analog Input 00 PIN4 ADC4 pin 01 PIN5 ADC5 pin 10 PIN6 ADC6 pin 11 PIN7 ADC7 pin AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 Revision I: Bit 7 +0x01 - Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 6-5. Table 6-6. 6 5 4 3 2 MUXPOS[3:0] 1 0 MUXNEG[2:0] ADC MUXNEG Configuration, INPUTMODE[1:0] = 10, Differential without Gain MUXNEG[2:0] Group Configuration Analog Input 000 PIN0 ADC0 pin 001 PIN1 ADC1 pin 010 PIN2 ADC2 pin 011 PIN3 ADC3 pin 100 - Reserved 101 GND PAD ground 110 - Reserved 111 INTGND Internal ground ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with Gain MUXNEG[2:0] Group Configuration Analog Input 000 PIN4 ADC4 pin 001 PIN5 ADC5 pin 010 PIN6 ADC6 pin 011 PIN7 ADC7 pin 100 INTGND Initial ground 101 - Reserved 110 - Reserved 111 GND PAD ground AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 7 7 Changes in Electrical Characteristics 7.1 Reduced Current Consumption in Active and Idle Mode Table 7-1 lists the typical and maximum current consumption in the Revision E and Revision I. Table 7-1. Current Consumption in Sleep Modes Revision E Parameter Condition 32kHz, ext. clk. 1MHz, ext. clk. Active power consumption 2MHz, ext. clk. 32MHz, ext. clk. 32kHz, ext. clk. Power-down power consumption Power-save power consumption Reset power consumption 8 Typ. Max. Min. Typ. Max. VCC = 1.8V 68 40 VCC = 3.0V 145 80 VCC = 1.8V 260 200 VCC = 3.0V 540 410 VCC = 1.8V 460 600 350 600 0.96 1.4 0.75 1.4 9.8 12 7.5 12 VCC = 3.0V 2.4 2 VCC = 3.0V 3.9 2.8 VCC = 1.8V 62 42 VCC = 3.0V 118 85 VCC = 1.8V 125 225 85 225 240 350 170 350 32MHz, ext. clk. 3.8 5.5 2.7 5.5 T = 25°C 0.1 1 0.1 1 1.2 4.5 2 4.5 WDT and sampled BOD enabled, T = 25°C 1.3 3 1.4 3 WDT and sampled BOD enabled, T = 85°C 2.4 6 3 6 2MHz, ext. clk. T = 85°C VCC = 3.0V VCC = 1.8V 1.2 1.5 VCC = 3.0V 1.3 1.5 RTC from 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.6 2 0.6 2 VCC = 3.0V 0.7 2 0.7 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.8 3 0.8 3 VCC = 3.0V 1 3 1 3 VCC = 3.0V 320 300 AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 mA µA RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C Current through RESET pin subtracted Units µA VCC = 1.8V 1MHz, ext. clk. Idle power consumption Min. Revision I mA µA 7.2 Increased ADC Maximum Samples Rate The maximum ADC clock frequency and sample rate is increased, as shown in Table 7-2. Table 7-2. ADC Characteristics Revision E 7.3 Parameter Min. ADC clock frequency ADC samples rate Typ. Revision I Max. Min. 100 1400 14 200 Typ. Max. Units 100 1800 kHz 16 300 kSPS Typ. Max. Units 16 90 Reduced Analog Comparator Propagation Delay The Analog Comparator propagation delay is reduced, as shown in Table 7-3. Table 7-3. Analog Comparator Characteristics Revision E 7.4 Parameter Condition Propagation delay Propagation delay Min. Revision I Typ. Max. VCC = 3.0V, T = 85°C 30 90 VCC = 1.6 – 3.6V, T = 25°C 30 Min. 16 ns 32kHz Internal ULP Oscillator Frequency The frequency of the 32kHz internal ULP oscillator is increased to match its nominal frequency with guaranteed accuracy. Table 7-4. 32kHz Internal ULP Oscillator Frequency Revision E Parameter Condition Min. Factory calibrated frequency Factory calibration accuracy Accuracy Typ. Revision I Max. Min. 26 VCC = 3.0V, T = 85°C Typ. Max. 32 Units kHz na na -12 12 na Na -30 30 AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 % 9 8 10 Revision History Doc Rev. Date 42401A 02/2015 Comments Initial document release. AT11008: Migration from ATxmega16D4/32D4 Revision E to Revision I [APPLICATION NOTE] Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2015 Atmel Corporation. / Rev.:Atmel-42401A-Migration-from-ATxmega16D4/32D4-RevisionE-to-RevisionI-ApplicationNote_AT11008_022015. Atmel®, Atmel logo and combinations thereof, AVR®, Enabling Unlimited Possibilities®, XMEGA®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. 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