HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Switching Regulator for Chopper Type DC/DC Converter Description The HA16114P/FP/FPJ and HA16120FP/FPJ are single-channel PWM switching regulator controller ICs suitable for chopper-type DC/DC converters. Integrated totem-pole output circuits enable these ICs to drive the gate of a power MOSFET directly. The output logic of the HA16120 is designed to control a DC/DC step-up (boost) converter using an N-channel power MOS FET. The output logic of the HA16114 is designed to control a DC/DC step-down (buck) converter or inverting converter using a P-channel power MOS FET. These ICs can operate synchronously with external pulse, a feature that makes them ideal for power supplies that use a primary-control AC/DC converter to convert commercial AC power to DC, then use one or more DC/DC converters on the secondary side to obtain multiple DC outputs. Synchronization is with the falling edge of the ‘sync’ pulse, which can be the secondary output pulse from a flyback transformer. Synchronization eliminates the beat interference that can arise from different operating frequencies of the AC/DC and DC/DC converters, and reduces harmonic noise. Synchronization with an AC/DC converter using a forward transformer is also possible, by inverting the ‘sync’ pulse. Overcurrent protection features include a pulse-by-pulse current limiter that can reduce the width of individual PWM pulses, and an intermittent operating mode controlled by an on-off timer. Unlike the conventional latched shutdown function, the intermittent operating function turns the IC on and off at controlled intervals when pulse-by-pulse current limiting continues for a programmable time. This results in sharp vertical settling characteristics. Output recovers automatically when the overcurrent condition subsides. Using these ICs, a compact, highly efficient DC/DC converter can be designed easily, with a reduced number of external components. Functions • • • • • • 2.5 V voltage reference Sawtooth oscillator (Triangle wave) Overcurrent detection External synchronous input Totem-pole output Undervoltage lockout (UVL) HA16114P/PJ/FP/FPJ, HA16120FP/FPJ • Error amplifier • Vref overvoltage protection (OVP) Features • Wide supply voltage range: 3.9 V to 40 V* • Maximum operating frequency: 600 kHz • Able to drive a power MOS FET (±1 A maximum peak current) by the built-in totem-pole gate predriver circuit • Can operate in synchronization with an external pulse signal, or with another controller IC • Pulse-by-pulse overcurrent limiting (OCL) • Intermittent operation under continuous overcurrent • Low quiescent current drain when shut off by grounding the ON/OFF pin HA16114: IOFF = 10 µA (max) HA16120: IOFF = 150 µA (max) • Externally trimmable reference voltage (Vref): ±0.2 V • Externally adjustable undervoltage lockout points (with respect to VIN) • Stable oscillator frequency • Soft start and quick shut function Note: The reference voltage 2.5 V is under the condition of VIN ≥ 4.5 V. Ordering Information Hitachi Control ICs for Chopper-Type DC/DC Converters Product Channel Channels Number No. Step-Up Step-Down Inverting Output Circuits Protection Dual HA17451 Ch 1 ❍ ❍ ❍ Open collector SCP with timer (latch) Ch 2 ❍ ❍ ❍ HA16114 — — ❍ ❍ Totem pole Pulse-by-pulse HA16120 — ❍ — — power MOS FET current limiter and HA16116 Ch 1 — ❍ ❍ driver intermittent operation Ch 2 — ❍ — Ch 1 — ❍ ❍ Ch 2 ❍ — — Single Dual HA16121 2 Control Functions Overcurrent by on/off timer HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Pin Arrangement GND*1 1 16 Vref SYNC 2 15 ADJ RT 3 14 DB CT 4 13 ON/OFF IN(−) 5 12 TM E/O 6 11 CL(−) IN(+) 7 10 VIN P.GND*1 8 9 OUT (Top view) Note: 1. Pin 1 (GND) and Pin 8 (P.GND) must be connected each other with external wire. Pin Description Pin No. Symbol Function 1 GND Signal ground 2 SYNC External sync signal input (synchronized with falling edge) 3 RT Oscillator timing resistor connection (bias current control) 4 CT Oscillator timing capacitor connection (sawtooth voltage output) 5 IN(–) Inverting input to error amplifier 6 E/O Error amplifier output 7 IN(+) Non-inverting input to error amplifier 8 P.GND Power ground 9 OUT Output (pulse output to gate of power MOS FET) 10 VIN Power supply input 11 CL(–) Inverting input to current limiter 12 TM Timer setting for intermittent shutdown when overcurrent is detected (sinks timer transistor current) 13 ON/OFF IC on/off control (off below approximately 0.7 V) 14 DB Dead-band duty cycle control input 15 ADJ Reference voltage (Vref) adjustment input 16 Vref 2.5 V reference voltage output 3 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Block Diagram Vref 16 ADJ VIN 2.5V bandgap reference voltage generator ADJ DB ON/OFF TM CL(−) VIN OUT 15 14 13 12 11 10 9 ON/OFF from UVL UVL H L VL VH 0.2 V − 1k + CL Vref 0.3V UVL output Latch S Q R OVP from UVL PWM COMP VIN + − + Triangle waveform generator *1 OUT NAND (HA16114) 1.6 V 1.0 V 1k 0.3 V Latch reset pulses 1.1 V RT Bias current + EA − 1 2 3 4 5 6 7 8 GND SYNC RT CT IN(−) E/O IN(+) P.GND Note: 1. The HA16120 has an AND gate. 4 from UVL HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Timing Waveforms Generation of PWM pulse output from sawtooth wave (during steady-state operation) T= Dead-band voltage (at DB) 1 fOSC 1.6 V typ Sawtooth wave (at CT ) 1.0 V typ Error amplifier output (at E/O) HA16114 PWM pulse output (drives gate of P-channel power MOS FET) VIN HA16120 PWM pulse output (drives gate of N-channel power MOS FET) VIN Off 0V 0V Off Off Off Off Off On On On On On On On On On On Off Off Off Off Time t t Note: On duty = ON T 5 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Guide to the Functional Description The description covers the topics indicated below. Oscillator 1. frequency (fOSC) control and synchronization DC/DC output 2. voltage setting and error amplifier usage 3. Dead-band and soft-start settings Output stage and 4. power MOS FET driving method GND*1 1 16 Vref SYNC 2 15 ADJ RT 3 14 DB CT 4 13 ON/OFF IN(−) 5 12 TM E/O 6 11 CL(−) IN(+) 7 10 VIN P.GND*1 8 9 OUT Vref adjustment, undervoltage 5. lockout, and overcurrent protection 6. ON/OFF pin usage Intermittent 7. mode timing during overcurrent 8. Setting of current limit (Top view) Note: 1. P.GND is a high-current (±1 A maximum peak) ground pin connected to the totem-pole output circuit. GND is a low-current ground pin connected to the Vref voltage reference. Both pins must be grounded. 1. Sawtooth Oscillator (Triangle Wave) 1.1 Operation and Frequency Control The sawtooth wave is a voltage waveform from which the PWM pulses are created (See figure 1). The sawtooth oscillator operates as follows. A constant current I O determined by an external timing resistor RT is fed continuously to an external timing capacitor C T . When the CT pin voltage exceeds a comparator threshold voltage VTH, the comparator output opens a switching transistor, allowing a 3I O discharge current to flow from C T . When the CT pin voltage drops below a threshold voltage VTL, the comparator output closes the switching transistor, stopping the 3IO discharge. Repetition of these operations generates a sawtooth wave. The value of IO is 1.1 V/RT Ω. The IO current mirror has a limited current capacity, so RT should be at least 5 kΩ (IO ≤ 220 µA). Internal resistances R A, RB, and R C set the peak and valley voltages VTH and V TL of the sawtooth waveform at approximately 1.6 V and 1.0 V. 6 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ The oscillator frequency f OSC can be calculated as follows. fOSC = 1 t1 + t2 + t3 Here, t1 = CT × (VH − VL) 1.1 V/RT t2 = CT × (VH − VL) 3 × 1.1 V/RT t3 ≈ 0.8 µs (comparator delay time) Since VH − VL = 0.6 V fOSC ≈ 1 (Hz) 0.73 × CT × RT + 0.8 (µs) At high frequencies the comparator delay causes the sawtooth wave to overshoot the 1.6 V threshold and undershoot the 1.0 V threshold, and changes the dead-band thresholds accordingly. Select constants by testing under implementation conditions. 3.2 V (Internal voltage) Current mirror Vref 2.5 V CT charging IO RA Oscillator comparator 1.1 V 1:4 Discharg -ing 3I O RC RB Sync circuit RT CT IO SYNC External circuit VH = 1.6 V typ t2 VL = 1.0 V typ t1 : t2 = 3 : 1 t1 Figure 1.1 Equivalent Circuit of Oscillator 7 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 1.2 External Synchronization These ICs have a sync input pin so that they can be synchronized to a primary-control AC/DC converter. Pulses from the secondary winding of the switching transformer should be dropped through a resistor voltage divider to the sync input pin. Synchronization takes place at the falling edge, which is optimal for multiple-output power supplies that synchronize with a flyback AC/DC converter. The sync input pin (SYNC) is connected internally through a synchronizing circuit to the sawtooth oscillator to synchronize the sawtooth waveform (see figure 1.2). • • • • Synchronization is with the falling edge of the external sync signal. The frequency of the external sync signal must be in the range fOSC < fSYNC < fOSC × 2. The duty cycle of the external sync signal must be in the range 5% < t1/t 2 < 50% (t 1 = 300 ns Min). With external synchronization, VTH' can be calculated as follows. VTH’ = (VTH − VTL) × fOSC + VTL fSYNC Note: When not using external synchronization, connect the SYNC pin to the Vref pin. VTH (1.6 V typ) VTH Sawtooth wave (fOSC) VTL (1.0 V typ) Vref SYNC pin (f SYNC ) Synchronized at falling edge t1 t2 Figure 1.2 External Synchronization 8 1V HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 2. DC/DC Output Voltage Setting and Error Amplifier Usage 2.1 DC/DC Output Voltage Setting (1) Positive Output Voltage (VO > Vref) HA16114 with step-down topology CL VIN IN(−) IN(+) − + EA CL VIN IN(−) IN(+) OUT VO GND − + EA VO GND OUT + − + − Vref R2 HA16120 with step-down (boost) topology Vref R1 R2 R1 R1 + R2 R2 VO = Vref × Figure 2.1 Output Voltage Setting (1) (2) Negative Output Voltage (V O < 0 V) HA16114 with inverting topology CL VIN IN(−) IN(+) − EA OUT + Vref R3 − + R4 R2 VO = −Vref × R1 R3 R1 + R2 × −1 R3 + R4 R2 Figure 2.2 Output Voltage Setting (2) 9 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 2.2 Error Amplifier Usage Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier in these ICs is a simple NPN-transistor differential amplifier with a constant-current-driven output circuit. The amplifier combines a wide bandwidth (fT = 4 MHz) with a low open-loop gain (50 dB Typ), allowing stable feedback to be applied when the power supply is designed. Phase compensation is also easy. IC internal VIN IN(−) E/O IN(+) To internal PWM comparator 80 µA 40 µA Figure 2.3 Error Amplifier Equivalent Circuit 3. Dead-Band Duty Cycle and Soft-Start Settings 3.1 Dead-Band Duty Cycle Setting The dead-band duty cycle (the maximum duty cycle of the PWM pulse output) can be programmed by the voltage VDB at the DB pin. A convenient way to obtain VDB is to divide the IC’s Vref output by two external resistors. The dead-band duty cycle (DB) and VDB can be calculated as follows. VTH − VDB × 100 (%) ⋅ ⋅ ⋅ ⋅ This applies when VDB > VTL. VTH − VTL If VDB < VTL, there is no PWM output. R2 VDB = Vref × R1 + R2 DB = Note: VDB is the voltage at the DB pin. VTH: 1.6 V (Typ) VTL: 1.0 V (Typ) Vref is typically 2.5 V. Select R1 and R2 so that 1.0 V ≤ VDB ≤ 1.6 V. To Vref R1 Sawtooth wave Sawtooth wave − DB E/O PWM COMP + + VDB R2 VTL from UVL Dead band Note: VTH and VTL vary depending on the oscillator. Select constants by testing under implementation conditions. Figure 3.1 Dead-Band Duty Cycle Setting 10 Voltage at DB pin VTH VDB HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 3.2 Soft-Start Setting Soft-start avoids overshoot at power-up by widening the PWM output pulses gradually, so that the converted DC output rises slowly. Soft-start is programmed by connecting a capacitor between the DB pin and ground. The soft-start time is determined by the time constant of this capacitor and the resistors that set the voltage at the DB pin. tsoft = −C1 × R × ln (1 − R= R1 × R2 R1 + R2 VDB = Vref × VX ) VDB R2 R1 + R2 Note: VX is the voltage at the DB pin after time t (VX < VDB). Undervoltage lockout released Sawtooth To Vref wave PWM COMP − E/O R1 VX + R2 1.6 V V DB V TL DB 1.0 V + C1 V TH Sawtooth wave VX from UVL UVL sink transistor t Soft-start time tsoft Figure 3.2 Soft-Start Setting 3.3 Quick Shutdown The quick shutdown function resets the voltages at all pins when the IC is turned off, to assure that PWM pulse output stops quickly. Since the UVL pull-down resistor in the IC remains on even when the IC is turned off, the sawtooth wave output, error amplifier output, and DB pin are all reset to low voltage. This feature helps in particular to discharge capacitor C 1 in figure 3.2, which has a comparatively large capacitance. In intermittent mode (explained on a separate page), this feature enables the IC to soft-start in each on-off cycle. 11 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 4. PWM Output Circuit and Power MOSFET Driving Method These ICs have built-in totem-pole push-pull drive circuits that can drive a power MOS FET as shown in figure 4.1. The power MOS FET can be driven directly through a gate protection resistor. If VIN exceeds the gate breakdown voltage of the power MOS FET additional protective measures should be taken, e.g. by adding Zener diodes as shown in figure 4.2. To drive a bipolar power transistor, the base should be protected by voltage and current dividing resistors as shown in figure 4.3. VIN To CL RG OUT Bias circuit Example: P-channel power MOSFET Gate protection resistor VO Totem-pole output circuit P.GND Figure 4.1 Connection of Output Stage to Power MOS FET VIN VO RG OUT GND DZ Example: N-channel power MOSFET Figure 4.2 Gate Protection by Zener Diodes VIN Base current limiting resistor VO OUT GND Base discharging resistor Example: NPN power transistor Figure 4.3 Driving a Bipolar Power Transistor 12 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 5. Voltage Reference (Vref = 2.5 V) 5.1 Voltage Reference A bandgap reference built into the IC (see figure 5.1) outputs 2.5 V ± 50 mV. The sawtooth oscillator, PWM comparator, latch, and other internal circuits are powered by this 2.5 V and an internally-generated voltage of approximately 3.2 V. The voltage reference section shut downs when the IC is turned off at the ON/OFF pin as described later, saving current when the IC is not used and when it operates in intermittent mode during overcurrent. VIN ON/OFF − + 1.25 V 25 kΩ Sub bandgap circuit 1.25 V 3.2 V Vref 2.5 V ADJ 25 kΩ Main bandgap circuit Figure 5.1 Vref Reference Circuit 5.2 Trimming the Reference Voltage (Vref and ADJ pins) Figure 5.2 shows a simplified circuit equivalent to figure 5.1. The ADJ pin in this circuit is provided for trimming the reference voltage (Vref). The output at the ADJ pin is a voltage V ADJ of 1.25 V (Typ) generated by the bandgap circuit. Vref is determined by VADJ and the ratio of internal resistors R1 and R2 as follows: Vref = VADJ × R1 + R2 R2 The design values of R1 and R2 are 25 kΩ with a tolerance of ±25%. If trimming is not performed, the ADJ pin open can be left open. VIN Vref R1 25 kΩ (typ) R2 25 kΩ (typ) ADJ − + VBG (bandgap voltage) 1.25 V (typ) Figure 5.2 Simplified Diagram of Voltage Reference Circuit 13 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ The relation between Vref and the ADJ pin enables Vref to be trimmed by inserting one external resistor (R3) between the Vref and ADJ pins and another (R 4) between the ADJ pin and ground, to change the resistance ratio. Vref is then determined by the combined resistance ratio of the internal R1 and R2 and external R3 and R4. Vref = VADJ × RA + RB RB Where, R A: parallel resistance of R1 and R3 R B: parallel resistance of R2 and R4 Although Vref can be trimmed by R3 or R 4 alone, to decrease the temperature dependence of Vref it is better to use two resistors having identical temperature coefficients. Vref can be trimmed in the range of 2.5 V ± 0.2 V. Outside this range, the bandgap circuit will not operate and the IC may shut down. Vref R3 External resistors ADJ R4 R1 RA = R1 R3 R1 + R3 RB = R2 R4 R2 + R4 Internal resistors R2 Figure 5.3 Trimming of Reference Voltage 5.3 Vref Undervoltage Lockout and Overvoltage Protection The undervoltage lockout (UVL) function turns off PWM pulse output when the input voltage (VIN) is low. In these ICs, this is done by monitoring the Vref voltage, which normally stays constant at approximately 2.5 V. The UVL circuit operates with hysteresis: it shuts PWM output off when Vref falls below 1.7 V, and turns PWM output back on when Vref rises above 2.0 V. Undervoltage lockout also provides protection in the event that Vref is shorted to ground. ! The overvoltage protection circuit shuts PWM output off when Vref goes above 6.8 V. This provides protection in case the Vref pin is shorted to VIN or another high-voltage source. PWM output PWM output off PWM output on PWM output off 1.7 2.0 2.5 5.0 6.8 10 Vref (V) Figure 5.4 Vref Undervoltage Lockout and Overvoltage Protection UVL Voltage Vref (V typ) VIN (V typ) Description VH 2.0 V 3.6 V VIN increasing: UVL releases; PWM output starts VL 1.7 V 3.3 V VIN decreasing: undervoltage lockout; PWM output stops 14 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 6. Usage of ON/OFF Pin This pin is used for the following purposes: • To shut down the IC while its input power remains on (power management) • To externally alter the UVL release voltage • With the timer (TM) pin, to operate in intermittent mode during overcurrent (see next section) 6.1 Shutdown by ON/OFF Pin Control The IC can be shut down safely by bringing the voltage at the ON/OFF pin below about 0.7 V (the internal VBE value). This feature can be used in power supply systems to save power. When shut down, the HA16114 draws a maximum current (I OFF) of 10 µA, while the HA16120 draws a maximum 150 µA. The ON/OFF pin sinks 290 µA (Typ) at 5 V, so it can be driven by TTL and other logic ICs. If intermittent mode will also be employed, use a logic IC with an open-collector or open-drain output. IIN RA VIN External logic IC Off To other circuitry On RB TM To latch 10 kΩ Switch CON/OFF VIN Q1 Vref reference ON/OFF + Vref output 3V BE − Q2 GND Q3 On/off hysteresis circuit HA16114, HA16120 Figure 6.1 Shutdown by ON/OFF Pin Control 6.2 Adjustment of UVL Voltages (when not using intermittent mode) These ICs permit external adjustment of the undervoltage lockout voltages. The adjustment is made by changing the undervoltage lockout thresholds VTH and V TL relative to VIN, using the relationships shown in the accompanying diagrams. When the IC is powered up, transistor Q3 is off, so VON is 2VBE, or about 1.4 V. Connection of resistors RC and R D in the diagram makes undervoltage lockout release at: VIN = 1.4 V × RC + RD RD This VIN is the supply voltage at which undervoltage lockout is released. At the release point Vref is still below 2.5 V. To obtain Vref = 2.5 V, V IN must be at least about 4.3 V. Since V ON/OFF operates in relation to the base-emitter voltage of internal transistors, VON has a temperature coefficient of approximately –4 mV/°C. Keep this in mind when designing the power supply unit. When undervoltage lockout and intermittent mode are both used, the intermittent-mode time constant is shortened, so the constants of external components may have to be altered. 15 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ I IN TM (open) RC VIN VIN To other circuitry To latch ON/OFF Q1 10 kΩ RD 3V BE Vref generation circuit Q3 Q2 GND 3 Vref output On/off hysteresis circuit 2.5 V VIN ≥ 4.5 V 2 Vref VOFF 0.7 V 1 0 0 1 VON 1.4 V 2 3 VON/OFF 4 5 Figure 6.2 Adjustment of UVL Voltages 7. Timing of Intermittent Mode during Overcurrent 7.1 Principle of Operation These ICs provide pulse-by-pulse overcurrent protection by sensing the current during each pulse and shutting off the pulse if overcurrent is detected. In addition, the TM and ON/OFF pins can be used to operate the IC in intermittent mode if the overcurrent state continues. A power supply with sharp settling characteristics can be designed in this way. Intermittent mode operates by making use of the hysteresis of the ON/OFF pin threshold voltages VON and VOFF (VON – VOFF = VBE ). The timing can be programmed as explained below. When not using intermittent mode, leave the TM pin open, and pull the ON/OFF pin up to VON or higher. The VBE is base emitter voltage of internal transistors. VIN 390 kΩ Latch S Q R RA TM 2.2 kΩ + 2.2 µF − RB ON/OFF Current limiter CL Vref reference C ON/OFF Figure 7.1 Connection Diagram (example) 16 # " ! HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 7.2 Intermittent Mode Timing Diagram (VON/OFF only) 3VBE*1 c c V ON/OFF 2VBE VBE On IC is on a IC is off b On Off 0V t T ON 2TON TOFF a. Continuous overcurrent is detected b. Intermittent operation starts (IC is off) c. Voltage if overcurrent ends (thick dotted line) Note: 1. VBE is the base-emitter voltage of internal transistors, and is approximately 0.7 V. (See the figure 6.1.) For details, see the overall waveform timing diagram. Figure 7.2 Intermittent Mode Timing Diagram (VON/OFF only) 7.3 Calculation of Intermittent Mode Timing Intermittent mode timing is calculated as follows. (1) TON (time until the IC shuts off when continuous overcurrent occurs) TON = CON/OFF × RB × ln 2VBE VBE × 1 1 − On duty* 1 1 − On duty* 1 ≈ 0.69 × CON/OFF × RB × 1 − On duty* = CON/OFF × RB × ln2 × (2) TOFF (time from when the IC shuts off until it next turns on) TOFF = CON/OFF × (RA + RB) × ln VIN − VBE VIN − 2VBE Where VBE ≈ 0.7 V The greater the overload, the sooner the pulse-by-pulse current limiter operates, the smaller tON becomes, and from the first equation (1) above, the smaller TO N becomes. From the second equation (2), TOFF depends on VIN. Note that with the connections shown in the diagram, when VIN is switched on the IC does not turn on until TOFF has elapsed. Dead-band voltage Sawtooth wave Point at which the current limiter operates PWM output (In case of HA16114) t ON t ON × 100 (%) T Where T = t/f OSC On duty = T Note: On duty is the percent of time the IC output is on during one PWM cycle when the pulse-by-pulse current limiter is operating. Figure 7.3 17 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 7.4 Examples of Intermittent Mode Timing (calculated values) 8 (1) TON TON = T1 × C ON/OFF × R B 6 Here, coefficient T1 = 0.69 × 1 1 − On duty 4 from section 7.3 (1) previously. T1 2 Example: If C ON/OFF = 2.2 µF, R B = 2.2 k Ω, and the on duty of the current limiter is 75%, then TON = 13 ms. 0 0 20 40 60 80 100 (PWM) On duty (%) Figure 7.4 Examples of Intermittent Mode Timing (1) (2) TOFF TOFF = T2 × C ON/OFF × (R A + R B) 0.1 Here, coefficient T2 = ln VIN − VBE VIN − 2VBE T2 from section 7.3 (2) previously. 0.05 Example: If C ON/OFF = 2.2 µF, R B = 2.2 k Ω, RA = 390 k Ω, VIN = 12 V, 0 then TOFF = 55 ms. 0 10 20 V IN (V) Figure 7.5 Examples of Intermittent Mode Timing (2) 18 30 40 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Example of step-up circuit VIN Sawtooth wave VCT Dead band VDB CF RF Error output VE/O PWM pulse output (In case of HA16120) IC RCS CL Inductor L OUT Power MOS FET drain current (ID) (dotted line shows inductor current) VIN Current limiter pin (CL) VIN − 0.2 V VOUT ID F.B. Determined by L and VIN VTH (CL) Determined by RCS and RF Figure 7.6 8. Setting the Overcurrent Detection Threshold The voltage drop VTH at which overcurrent is detected in these ICs is typically 0.2 V. The bias current is typically 200 µA. The power MOS FET peak current value before the current limiter goes into operation is given as follows. ID = VTH − (RF + RCS) × IBCL RCS Where, VTH = VIN – VCL = 0.2 V, V CL is a voltage refered on GND. Note that RF and CF form a low-pass filter with a cutoff frequency determined by their RC time constant. This filter prevents incorrect operation due to current spikes when the power MOS FET is switched on or off. VIN C F 1800 pF I BCL To other circuitry CL 1k 200 µA R CS 0.05 Ω V IN RF 240 Ω G OUT S Detector output (internal) VO D + IN(−) − + − Note: This circuit is an example for step-down use. Figure 8.1 Example for Step-Down Use With the values shown in the diagram, the peak current is: ID = 0.2 V − (240 Ω + 0.05 Ω) × 200 µA = 3.04 A 0.05 Ω The filter cutoff frequency is calculated as follows: fC = 1 1 = = 370 kHz 2π CF RF 6.28 × 1800 pF × 240 Ω 19 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Absolute Maximum Ratings (Ta = 25°C) Rating Item Symbol HA16114P/FP, HA16120FP HA16114PJ/FPJ, HA16120FPJ Unit Supply voltage VIN 40 40 V Output current (DC) IO ±0.1 ±0.1 A Output current (peak) I O peak ±1.0 ±1.0 A Current limiter input voltage VCL VIN VIN V Error amplifier input voltage VIEA VIN VIN V E/O input voltage VIE/O Vref Vref V RT source current I RT 500 500 µA TM sink current I TM 3 3 mA SYNC voltage VSYNC Vref Vref V SYNC current I SYNC ±250 1, ±250 2 1, Power dissipation PT 680* * Operating temperature Topr –20 to +85 –40 to +85 °C Junction temperature TjMax 125 125 °C Storage temperature Tstg –55 to +125 –55 to +125 °C Permissible dissipation PT (mW) Note: mW 1. This value is for an SOP package (FP) and is based on actual measurements on a 40 × 40 × 1.6 mm glass epoxy circuit board. With a 10% wiring density, this value is permissible up to Ta = 45°C and should be derated by 8.3 mW/°C at higher temperatures. With a 30% wiring density, this value is permissible up to Ta = 64°C and should be derated by 11.1 mW/°C at higher temperatures. 2. For the DILP package. This value applies up to Ta = 45°C; at temperatures above this, 8.3 mW/°C derating should be applied. 800 10% wiring density 680 mW 30% wiring density 600 447 mW 400 348 mW 200 0 −20 20 680* * µA 2 45°C 0 20 64°C 85°C 40 60 80 100 Operating ambient temperature Ta (°C) 125°C 120 140 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Electrical Characteristics (Ta = 25°C, VIN = 12 V, fOSC = 100 kHz) Item Symbol Min Typ Max Unit Test Conditions Voltage Output voltage Vref 2.45 2.50 2.55 V I O = 1 mA reference Line regulation Line — 2 60 mV 4.5 V ≤ V IN ≤ 40V section Load regulation Load — 30 60 mV 0 ≤ IO ≤ 10 mA Short-circuit output current I OS 10 24 — mA Vref = 0 V Vref overvoltage protection threshold Vrovp 6.2 6.8 7.4 V Temperature stability of output voltage ∆Vref/∆Ta — 100 — ppm/°C Vref adjustment voltage VADJ 1.225 1.25 1.275 V Sawtooth Maximum frequency fmax 600 — — kHz oscillator Minimum frequency fmin — — 1 Hz section Frequency stability with input voltage ∆f/f 01 — ±1 ±3 % Frequency stability with temperature ∆f/f 02 — ±5 Oscillator frequency f OSC 90 Dead-band adjustment Low level threshold voltage VTL section High level threshold voltage VTH Threshold difference ∆VTH 1 4.5 V ≤ V IN ≤ 40 V (f01 = (fmax + fmin)/2) % –20°C ≤ Ta ≤ 85°C (f02 = (fmax + fmin)/2) 100 110 kHz RT = 10 kΩ CT = 1300 pF 0.9 1.0 1.1 V Output duty cycle: 0% on 1.5 1.6 1.7 V — Output duty cycle: 100% on Output source current Isource 0.5 0.6 0.7 V ∆VTH = VTH – VTL 170 250 330 µA DB pin: 0 V PWM Low level threshold comparator voltage VTL 0.9 1.0 1.1 V Output duty cycle: 0% on section High level threshold voltage VTH 1.5 1.6 1.7 V Output duty cycle: 100% on Threshold difference ∆VTH 0.5 0.6 0.7 V ∆VTH = VTH – VTL Note: Notes 1. Resistors connected to ON/OFF pin: 10 VIN pin 390 kΩ 12 TM pin 2 kΩ 13 ON/OFF pin 21 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Electrical Characteristics (Ta = 25°C, VIN = 12 V, fOSC = 100 kHz) (cont) Item Symbol Min Typ Max Unit Test Conditions Error Input offset voltage VIO — 2 10 mV amplifier Input bias current — 0.5 2.0 µA section Output sink current I Osink 28 40 52 µA VO = 2.5 V Output source current 28 40 52 µA VO = 1.0 V Common-mode VCM input voltage range 1.1 — 3.7 V Voltage gain AV 40 50 — dB Unity gain bandwidth BW — 4 — MHz High level output voltage VOH 3.5 4.0 — V I O = 10 µA Low level output voltage VOL — 0.2 0.5 V I O = 10 µA Overcurrent Threshold voltage VTH VIN –0.22 VIN –0.2 VIN –0.18 V detection CL(–) bias current I BCL(–) 140 200 260 µA section Turn-off time t OFF — 200 300 ns 500 600 IB I Osource VTH 1.7 2.0 2.3 V Vref low level threshold voltage VTL 1.4 1.7 2.0 V Threshold difference ∆ VTH 0.1 0.3 0.5 V VIN high level threshold voltage VINH 3.3 3.6 3.9 V VIN low level threshold voltage VINL 3.0 3.3 3.6 V 22 f = 10 kHz CL(–) = VIN 1 2 UVL section Vref high level threshold voltage Notes: 1. HA16114 only. 2. HA16120 only. Notes ∆VTH = VTH – VTL HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Electrical Characteristics (Ta = 25°C, VIN = 12 V, fOSC = 100 kHz) (cont) Item Test Conditions Symbol Min Typ Max Unit Notes Output Output low voltage VOL — 0.9 1.5 V I Osink = 10 mA stage Output high voltage VOH1 VIN –2.2 VIN –1.6 — V I Osource = 10 mA High voltage when off VOH2 VIN –2.2 VIN –1.6 — V I Osource = 1 mA 1 ON/OFF pin: 0 V Low voltage when off VOL2 — 0.9 1.5 V I Osink = 1 mA 2 ON/OFF pin: 0 V Rise time tr — 50 200 ns CL = 1000 pF Fall time tf — 50 200 ns CL = 1000 pF External sync SYNC source current I SYNC 120 180 240 µA SYNC pin: 0 V section Sync input frequency range f SYNC f OSC — f OSC × 2 kHz External sync initiation voltage VSYNC Vref –1.0 — Vref –0.5 V Minimum pulse width of sync input PWmin 300 — — ns Input sync pulse duty cycle PW 5 — 50 % ON/OFF sink current 1 I ON/ OFF 1 60 90 120 µA ON/OFF pin: 3 V ON/OFF sink current 2 I ON/ OFF 2 220 290 380 µA ON/OFF pin: 5 V IC on threshold VON 1.1 1.4 1.7 V IC off threshold VOFF 0.4 0.7 1.0 V ON/OFF threshold difference ∆VON/OFF 0.5 0.7 0.9 V Total Operating current I IN 6.0 8.5 11.0 mA CL = 1000 pF device Quiescent current I OFF 0 — 10 µA ON/OFF pin: 0 V 1 — 120 150 µA ON/OFF pin: 0 V 2 On/off section 3 Notes: 1. HA16114 only. 2. HA16120 only. 3. PW = t1 / t2 × 100 External sync pulse t1 t2 23 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Characteristic Curves Reference Voltage vs. Supply Voltage Reference Voltage vs. Ambient Temperature 2.54 VIN = 12 V 2.55 max 4.0 Ta = 25°C Reference voltage (V) Reference voltage (V) 3.0 2.5V 2.0 1.0 2.52 2.50 SPEC 2.48 2.45 min 0.0 0 1 2 3 4 4.3V 40 0 20 40 60 80 Low Level Threshold Voltage of Sawtooth Wave vs. Frequency 2.5 Ta = 25°C V IN = 12 V 2.0 RT = 10 kΩ High Level Threshold Voltage of Sawtooth Wave vs. Frequency 2.5 Ta = 25°C V IN = 12 V 2.0 RT = 10 kΩ 1.5 1.0 0.5 200 300 400 Frequency (kHz) 500 600 High level threshold voltage of sawtooth wave (V) Ambient temperature (°C) Low level threshold voltage of sawtooth wave (V) Supply voltage (V) 0.0 100 24 5 2.46 −20 1.5 1.0 0.5 0.0 100 200 300 400 Frequency (kHz) 500 600 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Oscillator Frequency Change with Ambient Temperature (1) Oscillator Frequency Change with Ambient Temperature (2) 10 V IN = 12 V fOSC = 100 kHz 5 SPEC 0 −5 −10 −20 0 20 40 60 80 V IN = 12 V fOSC = 350 kHz Oscillator frequency change (%) Oscillator frequency change (%) 10 5 0 −5 −10 −20 0 Ambient temperature (°C) 20 40 60 80 Ambient temperature (°C) Error Amplifier Gain, Error Amplifier Phase vs. Error Amplifier Input Frequency AVO 40 0 φ 45 20 90 Error amplifier phase φ (deg.) Error amplifier gain AVO (dB) 60 135 0 1k BW 3k 10 k 30 k 100 k 300 k 1M 3M 180 10 M Error amplifier input frequency fIN (Hz) 25 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Current limiter turn-off time (ns) Error amplifier voltage gain (dB) Error Amplifier Voltage Gain vs. Ambient Temperature 60 VIN = 12 V f = 10 kHz 55 50 dB typ 50 45 Current Limiter Turn-Off Time vs. Current Limiter Threshold Voltage Note 500 • HA16114 Ta = 25°C V IN = 12 V CL = 1000 pF 400 300 ns max 300 200 40 dB min 40 −20 0.2 0.3 0.4 0.5 CL voltage VIN−VCL (V) Note: Approximatery 300 ns greater than this in the case of the HA16120. Current Limiter Threshold Voltage vs. Ambient Temperature VIN = 12 V 300 0.22 max 0.21 0.20 0.19 Current Limiter Turn-Off Time vs. Ambient Temperature Note • HA16114 300 ns max 250 200 200 ns typ 150 V IN = 12 V V CL = VTH − 0.3 V C L = 1000 pF 0.18 min 0.18 −20 26 100 0.1 80 Current limiter turn-off time (ns) Current limiter threshold voltage (V) 0.22 0 20 40 60 Ambient temperature (°C) 0 20 40 60 Ambient temperature (°C) 80 100 −20 0 20 40 60 80 Ambient temperature (°C) Note: Approximatery 300 ns greater than this in the case of the HA16120. HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Reference Voltage vs. IC On/Off Voltages IC On/Off Voltages vs. Ambient Temperature 2.0 V IN = 12 V fOSC = 100 kHz 5.0 Ta = 25°C V IN = 12 V IC off voltage 3.0 IC on voltage SPEC 2.0 IC on/off voltage (V) Reference voltage (V) 4.0 SPEC SPEC 1.5 IC on voltage 1.0 SPEC IC off voltage 0.5 1.0 0.0 0 0.5 1.0 1.5 2.0 2.5 0.0 −20 0 20 40 60 80 Ambient temperature (°C) Peak Output Current vs. Load Capacitance 600 Ta = 25°C V IN = 12 V 500 f OSC = 100 kHz 400 300 200 Operating Current vs. Supply Voltage 20 Operating current (mA) Peak output current (mA) IC on/off voltage (V) Ta = 25°C f OSC = 100 kHz On duty = 50% C L = 1000 pF 15 SPEC 10 5 100 0 0 1000 2000 3000 4000 Load capacitance (pF) 5000 0 0 10 20 30 40 Supply voltage (V) 27 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Operating Current vs. Output Duty Cycle Operating current (mA) 20 Ta = 25°C V IN = 12 V f OSC = 100 kHz C L = 1000 pF 15 SPEC 10 5 0 0 20 40 60 80 100 Output duty cycle (%) PWM Comparator Input vs. Output Duty Cycle (1) 100 • HA16114 PWM Comparator Input vs. Output Duty Cycle (2) 100 • HA16120 80 ON duty (%) ON duty (%) 80 60 40 fOSC 600 kHz 60 fOSC 600 kHz 40 50 kHz 20 20 300 kHz 50 kHz 300 kHz 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VDB or VE/O (V) Note: The on-duty of the HA16114 is the proportion of one cycle during which output is low. 28 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VDB or VE/O (V) Note: The on-duty of the HA16120 is the proportion of one cycle during which output is high. HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Output voltage VO (VDC) Output pin (Output Resistor) Characteristics 12 • HA16114 Output high voltage 11 when on VGS (P-channel Power MOS FET) 10 Output high voltage when off 9 • HA16120 3 Output low voltage when on Output low voltage when off 2 1 0 0 2 4 6 8 10 VGS (N-channel Power MOS FET) Io sink or Io source (mA) 29 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Output Waveforms: Rise of Output Voltage VOUT 15 10 VOUT (V) 5 Vref DB 0 CL(−) VIN OUT 400 IN(+) RT CL 1000 pF CT 200 IO (mA) 10 kΩ 1300 pF IO 0 Test Circuit −200 −400 200 ns/div Output Waveforms: Fall of Output Voltage VOUT 15 10 VOUT (V) 5 Vref DB 0 CL(−) VIN OUT 400 IN(+) RT CL 1000 pF CT 200 IO (mA) 10 kΩ 0 Test Circuit −200 −400 30 1300 pF 200 ns/div IO HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Oscillator Frequency vs. Timing Capacitance 1000 RT = 3kΩ RT = 10kΩ RT = 30kΩ Oscillator frequency f OSC (kHz) 100 10 RT = 100kΩ RT = 300kΩ RT = 1MΩ 1 0.1 101 102 103 104 105 106 Timing capacitance C T (pF) 31 • 12 VDC to 5 VDC Step-Down Converter Using HA16114FP 50m 9 Overcurrent sense resistor HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Application Examples (1) 32 − 5C Ground strip 0.1µ 10 k ADJ Vref 1 − + 13 12 3 RT 560p 4 CT 220 7 1 2 3 4 OUT Use a switching element (power MOS FET) with low on-resistance. Use an inductor with low DC resistance. Use a Schottky barrier diode (SBD) with low VF. Use a low-ESR capacitor designed for switching power supplies. 8 5D 1 GDS 5k 5A 5k 3 HRP24 SBD 47µH − + Low-ESR capacitor 560µ 12V 4 Units: C : F R:Ω − 5 V DC steppeddown output + 5 Noise countermeasures: 5A Separate the power ground from the small-signal ground, and connect both at one point. 5B Add noise-absorbing capacitors. 5C Ground the bottom of the package with a ground strip. 5D Make the output-to-gate wiring as short as possible. Feedback 2 High-saturation-current choke coil Example: Toko 8R-HB Series Low on-resistance P-channel power MOSFET Example: 2SJ214, 2SJ296 Power ground 0.22 µ (noiseabsorbing capacitor) 5.6 (gate protection resistor) IN(+) P.GND VIN 470p 6 E/O CL(−) 10 1800p 11 130k 5 IN(−) HA16114FP DB ON/OFF TM 14 10k 2 GND SYNC 15 16 Small-signal ground 5B 470 µ 35 V (noiseabsorbing capacitor) + 15 k 2µ 2k 390 k Specific tips for high efficiency (see the numbers in the diagram) 5A 12 V DC input − + + 4.7µ − Dead-band and soft-start circuit Timing circuit for intermittent mode during overcurrent ! HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Application Examples (2) • External Synchronization with Primary-Control AC/DC Converter (1) Combination with a flyback AC/DC converter (simplified schematic) HRA83 Commercial AC Transformer 1S2076A + 1S2076A − + D HRP24 + SBD + R1 Main DC output − R2 Error amp. − + − VIN OUT CL(CS) 2 SYNC VIN 10 HA16114, HA16120 CL 11 GND OUT P.GND 1 Primary AC/DC converter IC (HA16107, HA17384, etc.) 9 8 To A of SBD 2SJ296 + Step-down output (HA16114) K + − Sub DC output A SBD HRP24 − This is one example of a circuit that uses the features of the HA16114/120 by operating in synchronization with a flyback AC/DC converter. Note the following design points concerning the circuit from the secondary side of the transformer to the SYNC pin of the HA16114/120. • Diode D prevents reverse current. Always insert a diode here. Use a general-purpose switching diode. • Resistors R1 and R2 form a voltage divider to ensure that the input voltage swing at the SYNC pin does not exceed Vref (2.5 V). To maintain operating speed, R1 + R2 should not exceed 10 kΩ. 33 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Application Examples (3) • External Synchronization with Primary-Control AC/DC Converter (cont.) (2) Combination with a forward AC/DC converter (simplified schematic) DFG1C8 D HRW26F HA17431 and optocoupler + Input C A B Main DC output Feedback section SBD module − HA16107, HA16666 etc. FB 2SC458 R3 Switching transformer Coil Coil Coil Coil A B C D Primary, for main Secondary, for output Tertiary, for IC For reset R1 2 6.2kΩ Q R2 510Ω VIN 390Ω 10 SYNC VIN HA16114, HA16120 OUT ZD GND 1 9 Other parts as on previous page This circuit illustrates the combination of the HA16114/120 with a forward AC/DC converter. The HA16114/120 synchronizes with the falling edge of the external sync signal, so with a forward transformer, the sync pulses must be inverted. In the diagram, this is done by an external circuit consisting of the following components: • Q: Transistor for inverting the pulses. Use a small-signal transistor. • R1 and R2: These resistors form a voltage divider for driving the base of transistor Q. R2 also provides a path for base discharge, so that the transistor can turn off quickly. • R 3: Load resistor for transistor Q. Zener diode for protecting the SYNC pin. • ZD: 34 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Overall Waveform Timing Diagram (for Application Example (1)) 12 V VIN 0V VTM , VON/OFF VTM , 2.1 V 1.4 V VON/OFF 1.4 V 0.7 V 0.0 V On On (V) 3.0 On VE/O Off 2.0 VE/O, VCT, VDB On On Off Off Off Off VCT sawtooth wave 1.0 VDB 0.0 VCL 12 V 11.8 V 0V Pulse-by-pulse current limiting VOUT *1 12 V PWM pulse 0 V DC/DC output (example for positive voltage) Soft start IC operation status Power-up IC on Steady state Overcurrent detected; intermittent operation Overcurrent Quick subsides; shutdown steady-state operation Power supply off, IC off Note: 1. This PWM pulse is on the step-down/inverting control channel (HA16114). The booster control channel (HA16120) output consists of alternating L and H of the IC on cycle. 35 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Application Examples (4) (Some Pointers on Use) 1. Inductor, Power MOS FET, and Diode Connections 1. Step-up topology 2. Step-down topology V IN V IN CF RF V IN RCS CF Applicable only to HA16120 RF V IN CL RCS Applicable only to HA16114 CL OUT VO VO OUT GND GND FB FB 3. Inverting topology 4. Step-down/step-up (buck-boost) topology CF RF V IN RCS CF Applicable only to HA16114 RF V IN CL RCS Applicable only to HA16114 CL OUT OUT VO GND GND FB FB Vref 2. Turning Output On and Off while the IC is On To turn only one channel off, ground the DB pin or the E/O pin. In the case of E/O, however, there will be no soft start when the output is turned back on. DB E/O OFF 36 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Package Dimensions Unit: mm 19.20 20.00 Max 6.30 9 1 7.40 Max 16 8 1.3 0.48 ± 0.10 7.62 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Mass (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Mass (reference value) FP-16DA — Conforms 0.24 g 37 HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright ' Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 38