Batch Flow TCL for SmartFusion2 and IGLOO2

Batch Flow Scripting for SmartFusion2
and IGLOO2
Tcl User Guide
Batch Flow Scripting for SmartFusion2 and IGLOO2
Batch Flow Scripting for SmartFusion2 and IGLOO2
Table of Contents
Full Flow Script Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Import Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Pre-Synthesis Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Relevant Tcl documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Synthesize the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Relevant Tcl documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Post-Synthesis Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Import Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 Place and Route the Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 Run Post-Layout Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Table of Contents
10 Export Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tcl snippet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relevant Tcl commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full flow script—complete text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
21
A Support Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
io_constraints.pdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
basicblock.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
testbench.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
B Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4
Full Flow Script Introduction
Figure 1 shows the flowchart for a complete flow through the Libero toolset up to device programming. This document is organized in sections that correspond with the example script. Support files are provided in Appendix A, which allows you to run an example through the flow and supplies a basis for construction of your own batch process. This flow is specific to Libero Versions 11.4 and above, with SmartFusion2 and IGLOO2 devices.
Figure 1 • Organization of App Note and Full Flow Steps
5
Full Flow Script Introduction
This document uses two new Tcl commands: configure_tool and run_tool. These commands control tools
used in the flow for SmartFusion2 and IGLOO2 product families. Configure_tool sets operation and
control parameters for a tool, and run_tool starts the tool with the current parameter settings. This
document follows the two-step process of configuring the parameters of a tool, then starting it. The
information required for using these commands with a particular tool is presented in the portion of the
flow where the tool is used. As a matter of good coding practice, always specify explicitly the parameter
name and value for the command, unless the command does not have any parameter name-value pair.
Depending on parameters to default to particular values is a common source of errors that can be difficult
to troubleshoot.
6
Create a New Project
1 – Create a New Project
Description
Start the design creation in a new project and clean design area by removing all files from previous runs.
This script removes the log file and an old project directory (if it exists), creates the new project directory,
and sets tool profiles and library options.
Tcl snippet
file delete -force log_file.txt
catch
{ close_project -save 1 }
file delete -force "Full_flow_example"
new_project -location
"./Full_flow_example"
\
-name
"Full_flow_example"
\
-hdl
"VERILOG"
\
-family
"SmartFusion2"
\
-die
"M2S050T"
\
-package "896 FBGA"
\
-speed {-1}
\
-die_voltage {1.2}
\
-adv_options {IO_DEFT_STD:LVCMOS 1.2V} \
-adv_options {OPCONR:COM}
\
-adv_options {TEMPR:COM}
\
-adv_options {VCCI_1.2_VOLTR:COM}
\
-adv_options {VCCI_1.5_VOLTR:COM}
\
-adv_options {VCCI_1.8_VOLTR:COM}
\
-adv_options {VCCI_2.5_VOLTR:COM}
\
-adv_options {VCCI_3.3_VOLTR:COM}
\
-adv_options {VOLTR:COM}
Relevant Tcl commands
new_project
The new_project command creates a project directory at the specified location. You must specify the
device and package the design is targeted to, as well as the design language. Other options include
voltages, speed and temperature grades. For complete information, see the Libero User’s Guide or
online help.
7
Import Design Files
2 – Import Design Files
Description
Import the design source files and identify the top of the design. Import stimulus or a testbench, and then
connect the testbench with the top of the design hierarchy.
Tcl snippet
import_files
set_root
import_files
associate_stimulus
-hdl_source {./hdl/basicblock.v}
-module "BASICBLOCK::work"
-stimulus "./hdl/testbench.v"
-file "Full_flow_example/stimulus/testbench\
-mode {new}
\
-module "BASICBLOCK::work"
Relevant Tcl commands
import_files
The import_files command is used to copy a design file into the project. Many different types of files are
supported, including HDL design source files, constraints, placement, simulation, etc. The copied version
will not be associated with the original after the importation. For complete information, see the Libero
User’s Guide or online help.
link_files
The link_files command is used much like import_files, but instead of making a copy, the project directory
will contain a link to the specified file. In cases where the latest version of a file (located and maintained
outside of the Libero project) should be used, link to the file rather than import it. For complete
information, see the Libero User’s Guide or online help.
set_root
The set_root command identifies the top of your design hierarchy. For complete information, see the
Libero User’s Guide or online help.
8
Pre-Synthesis Simulation
3 – Pre-Synthesis Simulation
Description
Set up and run RTL simulation. This script assumes ModelSim as the default simulator. For complete
ModelSim operation information, see the ModelSim User’s Guide.
Tcl snippet
set SimTime {150 us}
set_modelsim_options -use_automatic_do_file 1
-sim_runtime $SimTime
\
\
-tb_module_name {testbench}\
-tb_top_level_name {DUT}
\
-include_do_file 0
\
-type {typ}
\
-resolution {1fs}
\
-add_vsim_options {-novopt}\
-display_dut_wave 1
\
-log_all_signals 1
\
-do_file_args {}
\
-dump_vcd 0
run_tool -name {SIM_PRESYNTH}
Relevant Tcl documentation
set_modelsim_options
The set_modelsim_options command sets the runtime options for ModelSim. Common parameters are
shown below, but for a complete list see the Libero User’s Guide.
Common Parameters
Note
Example Value
-use_automatic_do_file
When set (1) enables the use of the do file created 1 or 0
by Libero.
-sim_runtime
Sets the length of the simulation run.
150 ns
-tb_module_name
Identifies the testbench driving the design.
testbench
-tb_top_level_name
Identifies the top of the design tree.
DUT
-include_do_file
When set (1) will use the do file specified with the - 0 or 1
included_do_file parameter.
-type
Set what timing values are to be used in the
simulation.
typ, min, max
-resolution
Sets the time scale for the simulation.
1fs, 1ns, etc.
9
Pre-Synthesis Simulation
Common Parameters
Note
Example Value
-add_vsim_options
Calls ModelSim with the options listed.
-display_dut_wave
<value>
-display_dut_wave
When set (1), will cause ModelSim to display all
signals in the design. 0 will display only the
testbench.
1 or 0
SIM_PRESYNTYH
SIM_PRESYNTH launches RTL level simulation with the simulator from the selected profile. It has no
configuration options or parameters.
Syntax
run_tool -name {SIM_PRESYNTH}
Usage
configure_tool parameters
none
run_tool parameters
none
10
Type
Values
Description
—
—
—
Type
Values
Description
—
—
—
Synthesize the Design
4 – Synthesize the Design
Description
Synthesize the design into an EDIF netlist.
Tcl snippet
run_tool -name {SYNTHESIZE}
Relevant Tcl documentation
SYNTHESIZE
SYNTHESIZE runs the synthesis tool specified in the selected profile. Libero supports mixed language
designs, so the tool is configured to indicate all the languages used in the design description. By default,
Verilog 2001 is assumed.
Syntax
configure_tool -name {SYNTHESIZE} -params {parm:value} [–params {parm:value}]
run_tool -name {SYNTHESIZE}
Usage
configure_tool parameters
Type
Values
LANGUAGE_VERILOG_2001
bool
1|0
Set to 1 when this HDL version
used in design.
LANGUAGE_SYSTEM_VLOG
bool
0|1
Set to 1 when this HDL version
used in design.
LANGUAGE_VHDL_2008
bool
0|1
Set to 1 when this HDL version
used in design.
run_tool parameters
Type
Values
Description
—
—
—
none
Description
11
Post-Synthesis Simulation
5 – Post-Synthesis Simulation
Description
Perform gate level simulation.
Tcl snippet
run_tool -name {SIM_POSTSYNTH}
Relevant Tcl commands
SIM_POSTSYNTH
SIM_POSTSYNTH launches gate level simulation without placement and routing delays, with the
simulator from the selected profile. It has no configuration options or parameters.
Syntax
run_tool -name {SIM_POSTSYNTH}
Usage
configure_tool parameters
none
run_tool parameters
none
12
Type
Values
Description
—
—
—
Type
Values
Description
—
—
—
Import Constraints
6 – Import Constraints
Description
This section imports a physical design constraint file for I/Os, sets its place in the design hierarchy, and
then instructs the COMPILE to use the constraints at run time. Notice when organizing your constraints,
you point to the file at its location in the Libero project structure.
Tcl snippet
import_files
-io_pdc {.\constraints\io_constraints.pdc}
organize_constraints -file {.\Full_flow_example\constraint\io\io_constraints.pdc}\
-mode {new}
-designer_view {Impl1}
-module {BASICBLOCK::work}
-tool {designer}
organize_tool_files
-tool {COMPILE}
-file {.\Full_flow_example\constraint\io\io_constraints.pdc}
-module
{BASICBLOCK::work}
-input_type {constraint}
\
\
\
\
\
\
Relevant Tcl commands
organize_constraints
Associates a constraint file with a part of the design hierarchy and the part of the design flow where it will
be used. For complete information, see the Libero User’s Guide or online help.
organize_tool_files
Used to specify specific constraint files to be passed to and used by a Libero tool. For complete
information, see the Libero User’s Guide or online help.
13
Compile the Design
7 – Compile the Design
Description
The COMPILE tool converts the EDIF netlist and design constraints into an internal database.
configure_tool -name
-params
-params
-params
-params
-params
-params
-params
{COMPILE}
\
{MERGE_SDC:0}
\
{PDC_IMPORT_HARDERROR:0}
\
{DISPLAY_FANOUT_LIMIT:10}
\
{BLOCK_PLACEMENT_CONFLICTS:ERROR}\
{BLOCK_ROUTING_CONFLICTS:ERROR} \
{BLOCK_MODE:0}
\
{ENABLE_DESIGN_SEPARATION:0}
run_tool -name {COMPILE}
Relevant Tcl commands
COMPILE
The COMPILE tool converts the EDIF netlist and design constraints into an internal database.
Syntax
configure_tool -name {COMPILE} -params {parm:value} [-params {parm:value}]
run_tool -name {COMPILE}
Usage
configure_tool parameters
Type
Values
MERGE_SDC
bool
0|1
Merges existing SDC with existing timing
constraints.
PDC_IMPORT_HARDERROR
bool
0|1
Abort compile when errors occur in physical
design constraints.
DISPLAY_FANOUT_LIMIT
int
10
Sets display limit for number of high fanout
nets.
BLOCK_PLACEMENT_CONFLICTS
str
ERROR | KEEP |
LOCK | DISCARD
Resolve multiple block placement conflicts see the Libero User’s Guide.
BLOCK_ROUTING_CONFLICTS
str
ERROR | KEEP |
LOCK | DISCARD
Resolve multiple block routing conflicts see the Libero User’s Guide.
BLOCK_MODE
bool
0|1
Selects regular mode or block mode.
ENABLE_DESIGN_SEPARATION
bool
0|1
Set to 1, it removes nets used for power
saving.
run_tool parameters
Type
Values
—
—
none
14
Description
Description
—
Place and Route the Design
8 – Place and Route the Design
Description
This step takes the database created by COMPILE and adds placement and routing information.
Tcl snippet
configure_tool -name {PLACEROUTE}
\
-params {TDPR:1}
\
-params {PDPR:0}
\
-params {EFFORT_LEVEL:0}
\
-params {INCRPLACEANDROUTE:0}
run_tool -name {PLACEROUTE}
Relevant Tcl commands
PLACEROUTE
This tool performs the placement and routing functions on the design. It supports multiple modes
allowing for a balance between speed, power, and runtime. A full explanation can be found in the Libero
User’s Guide under the section "Place and Route - SmartFusion2 and IGLOO2".
Syntax
configure_tool -name {PLACEROUTE} -params {parm:value} [-params {parm:value}]
run_tool -name {PLACEROUTE}
Usage
configure_tool parameters
Type
Values
TDPR
bool
1|0
Timing driven place and route
PDPR
bool
0|1
Power driven place and route
EFFORT_LEVEL
bool
0|1
Higher optimization for longer runtime
INCRPLACEANDROUTE
bool
0|1
Use previous placement as starting
point
run_tool parameters
Type
Values
—
—
none
Description
Description
—
15
Run Post-Layout Tools
9 – Run Post-Layout Tools
Description
Post layout tools use the placed and routed database to do simulation with full timing and generate timing
and power reports.
Tcl snippet
run_tool -name {SIM_POSTLAYOUT}
run_tool -name {VERIFYTIMING}
run_tool -name {VERIFYPOWER}
Relevant Tcl commands
SIM_POSTLAYOUT
SIM_POSTLAYOUT launches gate level simulation including placement and routing delays, with the
simulator from the selected profile. It has no configuration options or parameters.
Syntax
run_tool -name {SIM_POSTLAYOUT}
Usage
configure_tool parameters
none
run_tool parameters
none
Type
Values
Description
—
—
—
Type
Values
Description
—
—
—
VERIFYTIMING
VERIFYTIMING launches the timing tool. While it has no configuration options or parameters that can be
directly set from a Libero Tcl script, there is a rich scripting capability that can be utilized from a separate
file. For complete information about SmartTime Tcl, see the SmartTime User’s Guide.
Syntax
run_tool -name {VERIFYTIMING}
configure_tool parameters
none
run_tool parameters
-script
16
[-script {<filename>}]
Type
Values
Description
—
—
—
Type
Values
Description
str
<filename>
Path and filename of a SmartTime
script file.
Run Post-Layout Tools
VERIFYPOWER
VERIFYPOWER launches the power analysis tool. While it has no configuration options or parameters
that can be directly set from a Libero Tcl script, there is a rich scripting capability that can be utilized from
a separate file. For complete information about SmartPower Tcl, see the SmartPower User’s Guide.
Syntax
run_tool -name {VERIFYPOWER} [-script {<filename>}]
Usage
configure_tool parameters
none
run_tool parameters
-script
Type
Values
Description
—
—
—
Type
Values
Description
str
<filename>
Path and filename of a SmartPower
script file.
17
Export Design Information
10 – Export Design Information
Description
This section covers the commands available for extracting design information from the database into a
variety of design files.
Tcl snippet
configure_tool -name {EXPORTFPPDC} \
-params {EXPORT_MODE:PDC_PLACE}
run_tool
-name {EXPORTFPPDC}
run_tool
-name {EXPORTIOPDC}
configure_tool -name {EXPORTPIN}\
-params {PINRPT_BY_NAME:1}\
-params {PINRPT_BY_NUMBER:1}
run_tool-name {EXPORTPIN}
configure_tool -name {EXPORTNETLIST} \
-params {EXPORT_HDL_TYPE:Verilog}
run_tool
-name {EXPORTNETLIST}
configure_tool -name {EXPORTNETLIST} \
-params {EXPORT_HDL_TYPE:VHDL}
run_tool
-name {EXPORTNETLIST}
configure_tool -name
{EXPORTSDF} \
-params {EXPORT_HDL_TYPE:Verilog}\
run_tool
-name {EXPORTSDF}
configure_tool -name {EXPORTSDF} \
-params {EXPORT_HDL_TYPE:VHDL}\
run_tool
-name {EXPORTSDF}
run_tool
-name {EXPORTSDC}
run_tool
-name {EXPORTG4IBIS}
run_tool
-name {EXPORTBSDL}
Relevant Tcl commands
EXPORTFPPDC
This tool generates a floorplanning PDC file. It will be stored within the Libero project folders under
<project name>/designer/<design name>.
Syntax
configure_tool -name {EXPORTFPPDC} [-params {parm:value}]
run_tool -name {EXPORTFPPDC}
18
Export Design Information
Usage
configure_tool parameters
EXPORT_MODE
run_tool parameters
none
Type
Values
Description
str
PDC_PLACE |
PDC_FULL_PLACEMENT
PDC_PLACE: Exports user's floorplanning constraints, e.g., fixed logic and regions.
PDC_FULL_PLACEMENT: Exports ALL floorplanning information, including initial and fixed (user's) placement.
Type
Values
Description
—
—
—
EXPORTIOPDC
This tool generates an I/O PDC file. It will be stored within the Libero project folders under <project
name>/designer/<design name>. It has no configuration options or parameters.
Syntax
run_tool -name {EXPORTIOPDC}
Usage
configure_tool parameters
none
run_tool parameters
none
Type
Values
Description
—
—
—
Type
Values
Description
—
—
—
EXPORTPIN
This tool generates a pin file. It will be stored within the Libero project folders under <project
name>/designer/<design name>.
Syntax
configure_tool -name {EXPORTPIN} -params {parm:value} [-params {parm:value}]
run_tool -name {EXPORTPIN}
Usage
configure_tool parameters
Type
Values
PINRPT_BY_NAME
bool
1|0
List the pins ordered by pin name
PINRPT_BY_NUMBER
bool
1|0
List the pins ordered by pin number
run_tool parameters
Type
Values
Description
—
—
—
none
Description
EXPORTNETLIST
This tool generates a netlist file. It will be stored within the Libero project folders under <project
name>/designer/<design name>.
19
Export Design Information
Syntax
configure_tool -name{EXPORTNETLIST}
[-params {parm:value}]
run_tool -name {EXPORTNETLIST}
Usage
configure_tool parameters
Type
Values
EXPORT_HDL_TYPE
str
VERILOG |
VHDL
run_tool parameters
Type
Values
Description
—
—
—
none
Description
Sets the HDL language for the
netlist.
EXPORTSDF
This tool generates the STD (Standard Delay Format) file. It will be stored within the Libero project
folders under <project name>/designer/<design name>.
Syntax
configure_tool -name {EXPORTSDF} -params {parm:value}
run_tool -name {EXPORTSDF}
Usage
configure_tool parameters
Type
Values
Description
EXPORT_HDL_TYPE
str
VERILOG |
VHDL
Sets the HDL language to be used.
run_tool parameters
Type
Values
Description
—
—
—
none
EXPORTSDC
This tool generates the SDC (Synopsys Design Constraints) file. It will be stored within the Libero project
folders under <project name>/designer/<design name>. It has no configuration options or parameters.
Syntax
run_tool -name {EXPORTSDC}
Usage
configure_tool parameters
none
run_tool parameters
none
Type
Values
Description
—
—
—
Type
Values
Description
—
—
—
EXPORTG4IBIS
This tool generates the IBIS (I/O Buffer Information Specification) file. It will be stored within the Libero
project folders under <project name>/designer/<design name>. It has no configuration options or
parameters.
Syntax
run_tool -name {EXPORTG4IBIS}
20
Export Design Information
Usage
configure_tool parameters
Type
Values
Description
—
—
—
Type
Values
Description
—
—
—
none
run_tool parameters
none
EXPORTBSDL
This tool generates the BSDL (Boundary Scan Description Language) file. It will be stored within the
Libero project structure under <project name>/designer/<design name>. It has no configuration options
or parameters.
Syntax
run_tool -name {EXPORTBSDL}
Usage
configure_tool parameters
Type
Values
Description
—
—
—
Type
Values
Description
—
—
—
none
run_tool parameters
none
Full flow script—complete text
#short_full_flow.tcl
file delete -force "Full_flow_example"
# form the project
new_project \
-location "./Full_flow_example" \
-name
"Full_flow_example" \
-hdl
"VERILOG" \
-family
"SmartFusion2" \
-die
"M2S050T" \
-package
"896 FBGA" \
-speed {-1} \
-die_voltage {1.2} \
-adv_options {IO_DEFT_STD:LVCMOS 1.2V} \
-adv_options {OPCONR:COM} \
-adv_options {TEMPR:COM} \
-adv_options {VCCI_1.2_VOLTR:COM} \
-adv_options {VCCI_1.5_VOLTR:COM} \
-adv_options {VCCI_1.8_VOLTR:COM} \
-adv_options {VCCI_2.5_VOLTR:COM} \
-adv_options {VCCI_3.3_VOLTR:COM} \
-adv_options {VOLTR:COM}
# change these names to generic ones after testing the script.
select_profile "modelsim_batch"
select_profile "synplify_batch"
21
Export Design Information
set_actel_lib_options -use_default_sim_path 1
#----------------------------------------------------------# Load design file
#----------------------------------------------------------import_files -hdl_source {./hdl/basicblock.v}
set_root -module "BASICBLOCK::work"
#---------------------------------------------------------------# Import testbench
#---------------------------------------------------------------import_files -stimulus "./hdl/testbench.v"
associate_stimulus -file "Full_flow_example/stimulus/testbench.v" \
-mode {new}
\
-module "BASICBLOCK::work"
#-----------------------------------------------------------------------------------# Pre-synthesis simulation
#
(ModelSim can be configured with the set_modelsim_options command)
#------------------------------------------------------------------------------------set SimTime {150 us}
set_modelsim_options \
-use_automatic_do_file 1 \
-sim_runtime
$SimTime \
-tb_module_name
{testbench} \
-tb_top_level_name
{DUT} \
-include_do_file
0 \
-type
{typ} \
-resolution
{1fs} \
-add_vsim_options
{-novopt} \
-display_dut_wave
1 \
-log_all_signals
1 \
-do_file_args
{} \
-dump_vcd
0 \
-vcd_file
{power.vcd}
run_tool -name {SIM_PRESYNTH}
#----------------------------------------------------------# Synthesis and Post synthesis simulation cannot be configured,
#
run them in order.
#----------------------------------------------------------run_tool -name {SYNTHESIZE}
run_tool -name {SIM_POSTSYNTH}
#----------------------------------------------------------# Import pdc file and set it for use.
#----------------------------------------------------------import_files -io_pdc {.\constraints\io_constraints.pdc}
organize_constraints -file {.\Full_flow_example\constraint\io\io_constraints.pdc} \
-mode
\
\
-module
\
-tool
22
{new}
-designer_view {Impl1}
{BASICBLOCK::work}
{designer}
Export Design Information
organize_tool_files -tool
{COMPILE}
\
-file
{.\Full_flow_example\constraint\io\io_constraints.pdc}
-module
{BASICBLOCK::work}
\
\
-input_type {constraint}
#----------------------------------------------------------# Compile the design
#----------------------------------------------------------configure_tool -name
{COMPILE}
\
-params {MERGE_SDC:0}
\
-params {PDC_IMPORT_HARDERROR:0}
\
-params {DISPLAY_FANOUT_LIMIT:10}
\
-params {BLOCK_PLACEMENT_CONFLICTS:ERROR} \
-params {BLOCK_ROUTING_CONFLICTS:ERROR}
\
-params {BLOCK_MODE:0}
\
-params {ENABLE_DESIGN_SEPARATION:0}
run_tool
-name {COMPILE}
#----------------------------------------------------------# Run the placer and router
#----------------------------------------------------------configure_tool -name {PLACEROUTE}
\
-params {TDPR:1}
\
-params {PDPR:0}
\
-params {EFFORT_LEVEL:0} \
-params {INCRPLACEANDROUTE:0}
run_tool
-name {PLACEROUTE}
#----------------------------------------------------------# These tools cannot be configured, run them in order.
#----------------------------------------------------------run_tool -name {SIM_POSTLAYOUT}
run_tool -name {VERIFYTIMING}
run_tool -name {VERIFYPOWER}
#----------------------------------------------------------# Export design files.
#
Examples of all available file formats are shown.
#----------------------------------------------------------configure_tool -name
{EXPORTFPPDC}
\
-params {EXPORT_MODE:PDC_PLACE}
run_tool
-name
{EXPORTFPPDC}
run_tool
-name
{EXPORTIOPDC}
configure_tool -name
{EXPORTPIN}
\
-params {PINRPT_BY_NAME:1} \
-params {PINRPT_BY_NUMBER:1}
run_tool
-name
configure_tool -name
{EXPORTPIN}
{EXPORTNETLIST} \
-params {EXPORT_HDL_TYPE:Verilog}
23
Export Design Information
run_tool
-name
configure_tool -name
{EXPORTNETLIST}
{EXPORTNETLIST} \
-params {EXPORT_HDL_TYPE:VHDL}
run_tool
-name
configure_tool -name
{EXPORTNETLIST}
{EXPORTSDF} \
-params {EXPORT_HDL_TYPE:Verilog} \
-params {DELAY_TYPE:1}
run_tool
-name
configure_tool -name
{EXPORTSDF}
{EXPORTSDF} \
-params {EXPORT_HDL_TYPE:VHDL} \
-params {DELAY_TYPE:1}
run_tool
-name
{EXPORTSDF}
run_tool
-name
{EXPORTSDC}
run_tool
-name
{EXPORTG4IBIS}
run_tool
-name
{EXPORTBSDL}
save_log -file log_file.txt
return 0
24
Support Files
A—Support Files
To recreate this example, recreate the structure pictured with the source files that follow. Run the
short_full_flow.tcl script from the Libero GUI (Project->Execute Script) or from a command line with the
-script parameter.
Figure 1 • Example directory structure
25
Support Files
io_constraints.pdc
# Single Pin Attributes 1 Test - test file number 1
# File created on : Wed Oct 2 2013 12:40
# Generator version 1.2
#
#---------------------------------------# Setting bank : bank0 IO_Type : DDRIO
# Setting Vcci : 1.8
#---------------------------------------set_iobank bank0 -vcci 1.8 -fixed yes
set_io {A_I} -pinname C29 -iostd SSTL18I
-RES_PULL None -FF_IO_STATE TRISTATE
ODT_STATIC On -FF_IO_AVAIL No -SCHMITT_TRIGGER
set_io {B_I} -pinname E27 -iostd LPDDRI
ODT_STATIC Off -LPE Wake_On_1 -IN_DELAY 32
-RES_PULL Down -FF_IO_STATE LAST_VALUE -
set_io {Y_O} -pinname D29 -iostd LVCMOS18
FF_IO_AVAIL No -OUT_DRIVE 4
-OUT_LOAD 5
-RES_PULL Up
basicblock.v
module BASICBLOCK(
A_I,
B_I,
Y_O,
);
input
A_I;
input
B_I;
output Y_O;
wire
a, b, c;
wire
GND_net, VCC_net;
INBUF ABUF(.PAD(A_I), .Y(a));
INBUF BBUF(.PAD(B_I), .Y(b));
AND2
IBD(.A(a), .B(b), .Y(c));
OUTBUF CBUF(.D(c), .PAD(Y_O));
VCC VCC (.Y(VCC_net));
GND GND (.Y(GND_net));
endmodule
testbench.v
`timescale 1 ns/10 ps
`define DLY1 60
`define DLY2 60
`define count 2
26
-
-FF_IO_STATE TRISTATE
-
Support Files
for (i=0; i<`count+2; i=i+1)
begin
c_loop = y;module testbench;
wire a_tb;
wire b_tb;
wire t_tb;
reg [`count-1:0] y;
reg temp1, temp2;
wire p_tb;
wire c_tb;
reg [`count-1:0] c_loop;
integer i = 0;
integer j = 0;
integer err_cnt = 0;
integer pass = 0;
assign a_tb = c_loop[1];
assign b_tb = c_loop[0];
BASICBLOCK DUT (
.A_I(a_tb),
.B_I(b_tb),
.Y_O(p_tb)
);
assign c_tb = a_tb & b_tb;
initial
begin
y = {`count{1'b0}};
#10;
$display ("A=%b,B=%b,Expected=%b, Sampled=%b", c_loop[1], c_loop[0], c_tb, p_tb,
$time);
#( `DLY1 );
temp1 = y[`count - 1];
temp2 = 1'bx;
for (j=0; j<`count+1; j=j+1)
begin
#(`DLY1);
if(c_tb === p_tb )
begin
$display(" ----------PASSED DISPLAY------------\n");
$display ("A=%b,B=%b,Expected=%b, Sampled=%b", c_loop[1], c_loop[0], c_tb, p_tb,
$time);
pass = pass + 1'b1;
end
if(c_tb !== p_tb )
begin
27
Support Files
$display(" ----------FAILED DISPLAY------------");
$display ("A=%b,B=%b,Expected=%b, Sampled=%b", c_loop[1], c_loop[0], c_tb, p_tb,
$time);
err_cnt = err_cnt + 1'b1;
end
c_loop = c_loop << 1;
c_loop[0] = temp2;
temp2 = temp1;
temp1 = c_loop[`count - 1];
end
y = y + 1;
end
if( err_cnt > 0)
$display ("!! TEST RUN FAILED with %0d errors !!",err_cnt);
else if( pass > 0 & err_cnt == 0)
$display ("TESTBENCH SUCCESSFUL with %0d",pass);
else if(pass == 0 & err_cnt == 0)
$display ("TEST RUN FAILED");
$finish;
end
endmodule
28
[Document Title]
B – Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more
information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the website.
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected]
29
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected] Alternatively, within My Cases, select
Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR
web page.
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog
and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
5-02-00579-0/09.14
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