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L7987
61 V 3 A asynchronous step-down switching regulator with
adjustable current limitation
Datasheet - production data
Description
HTSSOP16 (RTH = 40 °C/W)
Features
 3 A DC output current
 4.5 V to 61 V operating input voltage
 RDS,ON = 250 m typ.
 Adjustable fSW (250 kHz - 1.5 MHz)
 Low IQ-SHD (11 µA typ. from VIN)
 Low IQ (1 mA typ. - VIN 24 V - VOUT 3.3 V)
 Output voltage adjustable from 0.8 V to VIN
 Synchronization
 Adjustable soft-start time
 Adjustable current limitation
 Low dropout operation (12 µs max.)
The L7987 device is a step-down monolithic
switching regulator able to deliver up to 3 A DC.
The output voltage adjustability ranges from 0.8 V
to VIN. The wide input voltage range and the
100% duty cycle capability meet the fail safe
specifications for industrial systems. The
embedded switchover feature on the VBIAS pin
maximizes the efficiency at light load. The
adjustable current limitation, designed to select
the inductor RMS current accordingly with the
nominal output current, and the high switching
frequency capability make the size of the
application compact. Pulse-by-pulse current
sensing with digital frequency foldback
implements an effective constant current
protection over the different application
conditions. The peak current foldback decreases
the stress of the power components in heavy
short-circuit condition. The PGOOD open
collector output can also implement output
voltage sequencing during the power-up phase.
Multiple devices can be synchronized sharing the
SYNCH pin to prevent beating noise in low noise
applications like sensors with A/D conversion.
 VBIAS improves efficiency at light load
 PGOOD open collector output
 Output voltage sequencing
 Digital frequency foldback in short-circuit
 Peak current foldback in short-circuit
 Auto-recovery thermal shutdown
Applications
 Designed for 24 V bus
 Fail safe tolerant system
 Programmable logic controllers (PLCs)
March 2015
This is information on a product in full production.
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www.st.com
Contents
L7987
Contents
1
Application schematic and block diagram . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
4.1
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Error amplifier and light-load management . . . . . . . . . . . . . . . . . . . . . . . 16
4.4
Low VIN operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.1
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.2
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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DocID025589 Rev 3
L7987
Contents
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID025589 Rev 3
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37
Application schematic and block diagram
1
L7987
Application schematic and block diagram
Figure 1. Application schematic
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L7987
Pin settings
2
Pin settings
2.1
Pin connection
Figure 3. Pin connection (top view)
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37
Pin settings
2.2
L7987
Pin description
Table 1. Pin description
Number
Pin
Description
1
VBIAS
Auxiliary input that can be used to supply part of the analog circuitry to increase the efficiency
at light load. Typically connected to the regulated output voltage or to an external voltage rail
higher than 3 V. Connect to the signal GND if not used or bypass with a 1 F ceramic capacitor
if supplied by the output voltage or by an auxiliary rail.
2
VIN
DC input voltage
3
VIN
DC input voltage
4
VCC
Filtered DC input voltage to the internal circuitry. Bypass to the signal GND by a 1 F ceramic
capacitor.
5
EN
Active high enable pin. Connect to the VCC pin if not used.
6
SS
An internal current generator (5 µA typ.) charges the external capacitor to implement the softstart.
7
SYNCH Master / slave synchronization
8
COMP
9
FB
10
FSW
A pull-down resistor to GND selects the switching frequency.
11
ILIM
A pull-down resistor to GND selects the peak current limitation.
12
PGOOD
13
LX
Switching node
14
LX
Switching node
15
BOOT
16
GND
Signal GND
-
E.P.
Exposed pad must be connected to signal GND.
6/37
Output of the error amplifier. The designed compensation network is connected at this pin.
Inverting input of the error amplifier.
The PGOOD open collector output is driven low when the output voltage, sensed on the FB
pin, is out of regulation.
Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The gate charge
required to drive the internal n-DMOS is recovered by an internal regulator during the off-time
DocID025589 Rev 3
L7987
2.3
Pin settings
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Description
Min.
Max.
Unit
VIN
-0.3
61
V
VCC
-0.3
61
V
VBOOT - GND
-0.3
65
V
VBOOT - VLX
-0.3
4
V
VBIAS
-0.3
VCC
V
EN
-0.3
VCC
V
PGOOD
-0.3
VCC
V
LX
-0.3
VIN + 0.3
V
SYNCH
-0.3
5.5
V
SS
-0.3
3.6
V
FSW
-0.3
3.6
V
COMP
-0.3
3.6
V
ILIM
-0.3
3.6
V
FB
-0.3
3.6
V
Operating temperature range
-40
150
°C
TSTG
Storage temperature range
-65
150
°C
TLEAD
Lead temperature (soldering 10 sec.)
260
°C
3
A
BOOT
TJ
High-side RMS current
IHS
2.4
Thermal data
Table 3. Thermal data
2.5
Symbol
Parameter
Value
Unit
RthJA
Thermal resistance junction-ambient (device soldered
on the STMicroelectronics® demonstration board)
40
°C/W
Value
Unit
HBM
2
KV
CDM
500
V
ESD protection
Table 4. ESD protection
Symbol
ESD
Test condition
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37
Electrical characteristics
3
L7987
Electrical characteristics
All the population tested at TJ = 25 °C, VIN = VCC = 24 V and VEN =3 V unless otherwise
specified.
Table 5. Electrical characteristics
Symbol
VIN
Parameter
Switching frequency
Selected switching frequency
IPK
ISKIP
VFOLD
Peak current limit
Selected peak current limit
Max.
Unit
61
V
0.2
0.32

0.2
0.42

233
250
267
kHz
225
250
275
kHz
4.5
ISW = 0.5 A
ISW = 0.5 A
(1)
FSW floating
FSW floating
(1)
RSW = 10 k 
Typ.
1350
1500
1650
kHz
ILIM floating; VFB = 0.6 V
(2)
3.4
4.0
4.6
A
RILIM = 100 k VFB = 0.6 V
(2)
0.68
0.85
1.01
A
Pulse skipping peak current
(2)
0.5
A
Feedback foldback level
(3)
400
mV
12
µs
TONMAX
Maximum on time
TONMIN
Minimum on time
TOFFMIN
Min.
(1)
Operating input voltage range
RDSON HS High side RDSON
fSW
Test condition
120
(3)
Minimum off time
150
360
ns
ns
VCC / VBIAS
VCCH
VCCHYST
VCC UVLO rising threshold
(1)
3.85
4.10
4.30
V
VCC UVLO hysteresis
(1)
160
250
340
mV
Switch internal supply from VCC to (1)
VBIAS. VBIAS ramping up from 0 V.
2.84
2.90
2.96
V
VBIAS threshold
Hysteresis
SWO
VCC - VBIAS threshold
(3)
Switch internal supply from VCC to
(1)
VBIAS. VIN = VCC = 24 V, VBIAS
falling from 24 V to GND.
Hysteresis
(3)
80
3.35
4.05
mV
4.90
750
V
mV
Power consumption
ISHTDWN
Shutdown current from VIN
VEN = GND
IQUIESC
Quiescent current from VIN and LX floating, VFB = 1 V,
VCC
VBIAS = GND, FSW floating
Quiescent current from VIN and
LX floating, VFB = 1 V,
VCC
VBIAS = 3.3 V, FSW floating
IQOPVBIAS Quiescent current from VBIAS
IQOPVIN
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11
16
A
2.5
3.4
mA
1.0
1.4
mA
1.6
2.4
mA
L7987
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Enable
VEN
Device OFF level
0.06
0.30
V
Device ON level
0.35
0.90
V
Soft start
TSSSETUP Soft start setup time
ISS CH
CSS charging current
Delay from UVLO rising to
switching activity
(3)
VSS = GND
s
640
4.3
5.0
5.7
A
0.792
0.800
0.808
V
0.788
0.800
0.812
V
3.2
3.35
3.5
V
0.1
V
50
nA
Error amplifier
VFB
VFB
Voltage feedback
(1)
Voltage feedback
VCOMPH
VFB = GND; VSS = 3.2 V
VCOMPL
VFB =1 V; VSS = 3.2 V
IFB
FB biasing current
VFB =GND; SS pin floating;
VCOMP =2 V
IOSOURCE
IOSINK
AV0
VFB =3.6 V
Output stage sinking capability
5
(3)
Unity gain buffer configuration (FB
connected to COMP). COMP
(3)
voltage variation due to IOSINK
injection lower than ± 0.1 · VFB
(3)
Error amplifier gain
Unity gain buffer configuration (FB
connected to COMP). No load on (3)
COMP pin.
GBWP
3.1
mA
5
mA
100
dB
23
MHz
Synchronization (fan out: 5 slave devices max.)
fSYN MIN
Synchronization frequency
VSYNOUT
Master output amplitude
VSYNOW
Output pulse width
VSYNIH
SYNCH slave high level input
threshold
VSYNIL
SYNCH slave low level input
threshold
ISYN
VSYNIW
Slave SYNCH pull-down
current
FSW floating
280
ILOAD = 4 mA
2.45
kHz
ILOAD = 0 A; pin SYNCH floating
3.8
ILOAD = 0 A; pin SYNCH floating
155
225
275
2.0
VSYNCH = 5 V
550
Input pulse width
V
ns
V
750
1.0
V
950
A
200
ns
PGOOD
VPGDTH
PGOOD rising threshold
VPGDHYST PGOOD hysteresis
VFB rising
VFB falling
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(3)
0.70
30
0.73
V
mV
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37
Electrical characteristics
L7987
Table 5. Electrical characteristics (continued)
Symbol
Parameter
VPGDLOW PGOOD low level
IPGDLKG
PGOOD leakage current
Test condition
Min.
IPGD = 1 mA, VFB = GND
Typ.
Max.
30
VPGOOD = 61 V;VFB = 0.8 V
Unit
mV
0.1
A
Thermal shutdown
TSHDWN
THYS
Thermal shutdown temperature
(3)
170
°C
Thermal shutdown hysteresis
(3)
15
°C
1. Specifications referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by
design, characterization and statistical correlation.
2. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
3. Not tested in production.
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L7987
4
Functional description
Functional description
The L7987 device is based on a voltage mode, constant frequency control loop. The output
voltage VOUT, sensed by the feedback pin (FB), is compared to an internal reference
(0.8 V) providing an error signal on the COMP pin. The COMP voltage level is then
compared to a fixed frequency sawtooth ramp, which finally controls the on- and off-time of
the power switch.
The main internal blocks are shown in the block diagram in Figure 2 on page 4 and can be
summarized as follow.
4.1

The fully integrated oscillator that provides the sawtooth ramp to modulate the duty
cycle and the synchronization signal. Its switching frequency can be adjusted by an
external resistor. The input voltage feed-forward is implemented.

The soft-start circuitry to limit inrush current during the start-up phase.

The voltage mode error amplifier.

The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.

The high-side driver for embedded N-channel Power MOSFET switch and bootstrap
circuitry. A dedicated high resistance low-side MOSFET, for anti-boot discharge
management purposes, is also present.

The peak current limit sensing block, with programmable threshold, to handle overload
and short-circuit conditions including current foldback and a thermal shutdown block, to
prevent thermal runaway.

The voltage regulator and internal reference, to supply the internal circuitry and provide
a fixed internal reference. The switchover function from VCC to VBIAS can be
implemented for higher efficiency. This block also implements a voltage monitor
circuitry (UVLO) that checks the input and internal voltages.

The output voltage monitor circuitry which releases the PGOOD signal if the sensed
output voltage is above 87% of the target value.
Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock, whose frequency depends on the resistor externally connected
between the FSW pin and ground.
Figure 4. Oscillator and synchronization
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37
Functional description
L7987
If the FSW pin is left floating, the programmed frequency is 250 kHz (typ.); if FSW pin is
connected to an external resistor the programmed switching frequency can be increased up
to 1.5 MHz, as shown in Figure 5. The required RFSW value (expressed in k) is estimated
by Equation 1:
Equation 1
12500
F SW = 250kHz + ---------------R FSW
Figure 5. Switching frequency programmability
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the input voltage feed-forward is implemented by changing the slope of the
sawtooth ramp, according to the input voltage change (Figure 6 a).
The slope of the sawtooth also changes if the oscillator frequency is programmed by the
external resistor. In this way a frequency feed-forward is implemented (Figure 6 b) in order
to keep the PWM modulator gain constant versus the switching frequency.
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pins together. When SYNCH pins are connected, the device with
a higher oscillator frequency works as master, so the slave device switches at the frequency
of the master but with a delay of half a period. This helps reducing the RMS current flowing
through the input capacitor. Up to five L7987s can be connected to the same SYNCH pin;
however, the clock phase shift from master switching frequency to slaves input clock is
180°.
The L7987 device can be synchronized to work at a higher frequency, in the range 250 kHz
- 1500 kHz, providing an external clock signal on the SYNCH pin. The synchronization
changes the sawtooth amplitude, also affecting the PWM gain (Figure 6 c). This change
must be taken into account when the loop stability is studied. In order to minimize the
change of PWM gain, the free running frequency should be set (with a resistor on the FSW
pin) only slightly lower than the external clock frequency.
This pre-adjusting of the slave IC switching frequency keeps the truncation of the ramp
sawtooth negligible.
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L7987
Functional description
In case two or more (up to five) L7987 SYNCH pins are tied together, the L7987 IC with
higher programmed switching frequency is typically the master device; however, the
SYNCH circuit is also able to synchronize with a slightly lower external frequency, so the
frequency pre-adjustment with the same resistor on the FSW pin, as suggested above, is
required for a proper operation.
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37
Functional description
L7987
Figure 6. Feed-forward
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L7987
4.2
Functional description
Soft-start
The soft-start is essential to assure a correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monotonically.
The soft-start is performed by charging an external capacitor, connected between the SS pin
and ground, with a constant current (5 µA typ.). The SS voltage is used as reference of the
switching regulator and the output voltage of the converter tracks the ramp of the SS
voltage. When the SS pin voltage reaches 0.8 V level, the error amplifier switches to the
internal 0.8 V ± 1% reference to regulate the output voltage.
Figure 7. Soft-start
During the soft-start period the current limit is set to the nominal value.
The dVSS/dt slope is programmed in agreement with Equation 2:
Equation 2
I SS  T SS
5A  T SS
C SS = ------------------------ = --------------------------V REF
0.8V
Before starting the CSS capacitor charge, the soft-start circuitry turns-on the discharge
switch shown in Figure 7 for TSSDISCH minimum time, in order to completely discharge the
CSS capacitor.
As a consequence, the maximum value for the soft-start capacitor, which assures an almost
complete discharge in case of EN signal toggle, is provided by:
Equation 3
T SSDISCH
C SS – MAX  ------------------------------------  270nF
5  R SSDISCH
given TSSDISCH = 530 s and RSSDISCH = 380  typical values.
The enable feature allows to put the device into standby mode. With the EN pin lower than
0.32 V the device is disabled and the power consumption is reduced to less than 11 A
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37
Functional description
L7987
(typ.). With the EN pin higher than 1.16 V, the device is enabled. If the EN pin is left floating,
an internal pull-down current ensures that the voltage at the pin reaches the inhibit threshold
and the device is disabled. The pin is also VCC compatible.
4.3
Error amplifier and light-load management
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non inverting input is internally connected to a 0.8V
voltage reference and its inverting input (FB) and output (COMP) are externally available for
feedback and frequency compensation. In this device the error amplifier is a voltage mode
operational amplifier, therefore, with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are summarized in Table 6.
Table 6. Error amplifier characteristics
Parameters
Value
Low frequency gain (A0)
100 dB
GBWP
23 MHz
Output voltage swing
0 to 3.5 V
Source/sink current capability
2 mA / 5 mA
In continuous conduction working mode (CCM), the transfer function of the power section
has two poles due to the LC filter and one zero due to the ESR of the output capacitor.
Different kinds of compensation networks can be used depending on the ESR value of the
output capacitor.
If the zero introduced by the output capacitor helps to compensate the double pole of the LC
filter, a type II compensation network can be used. Otherwise, a type III compensation
network must be used (see Section 5.4 on page 23 for details on the compensation network
design).
In case of light load (i.e. if the output current is lower than the half of the inductor current
ripple) the L7987 device enters pulse-skipping working mode. The HS MOS is kept off if the
COMP level is below 200 mV (typ.); when this bottom level is reached the integrated switch
is turned on until the inductor current reaches ISKIP value. So, in discontinuous conduction
working mode (DCM), the HS MOS on-time is only related to the time necessary to charge
the inductor up to ISKIP level. Due to current sensing comparator delay, the actual inductor
charge current is slightly impacted by VIN and inductance level.
In order to let the bootstrap capacitor recharge, in case of extremely light load the L7987 is
able to pull-down the LX net through an integrated small LS MOS. In this way the bootstrap
recharge current can flow from VIN through CBOOT, LX and the LS MOS.
This mechanism is activated if the HS MOS has been kept turned-off for more than 3 ms
(typ.).
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L7987
4.4
Functional description
Low VIN operation
In normal operation (i.e. VOUT programmed lower than input voltage) when the HS MOS is
turned off, a minimum off time (TOFFMIN) interval is performed.
In case the input voltage falls close or below the programmed output voltage (low dropout,
LDO) the L7987 control loop is able to increase the duty cycle up to 100%. However, in
order to keep the boot capacitor properly recharged, a maximum HS MOS on time is limited
(TONMAX). When this limit is reached the HS MOS is turned-off and a pull-down resistor
between LX and GND is turned on until one of the following conditions is met:

A negative current limit (300 mA typ.) is reached

A timeout (1 s typ.) is reached.
So doing the L7987 device is able to work in low dropout operation, due to the advanced
boot capacitor management, and the effective maximum duty cycle is about
12 µs / 13 µs = 92%.
4.5
Overcurrent protection
The L7987 device implements an overcurrent protection by sensing the current flowing
through the Power MOSFET. Due to the noise created by the switching activity of the Power
MOSFET, the current sensing circuitry is disabled during the initial phase of the conduction
time. This avoids an erroneous detection of a fault condition. This interval is generally
known as “masking time” or “blanking time”. The masking time is about 120 ns.
If the overcurrent limit is reached, the Power MOSFET is turned off implementing pulse-bypulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses
in order to keep the inductor current constant and equal to the current limit, assuming only a
slight drift due to input and output voltage variation.
If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the
Power MOSFET is turned off and one pulse is skipped. If, at the following switching on,
when the “masking time” ends, the current is still higher than the overcurrent threshold, the
device skips two pulses. This mechanism is repeated and the device can skip up to seven
pulses (refer to Figure 8).
If at the end of the “masking time” the current is lower than the overcurrent threshold, the
number of skipped cycles is decreased by one unit.
As a consequence, the overcurrent/short-circuit protection acts by switching off the Power
MOSFET and reducing the switching frequency down to one eighth of the default switching
frequency, in order to keep constant the output current close to the current limit.
DocID025589 Rev 3
17/37
37
Functional description
L7987
Figure 8. OCP and frequency scaling
If the sensed output voltage, monitored through FB pin, falls below the VFOLD threshold
(400 mV typ.) the peak current limit threshold is reduced to 1/3 of the nominal value. This
additional feature helps to reduce the IC stress in case of output short-circuit.
As soon as the FB pin increases above the VFOLD threshold, the full peak current limit
threshold is restored. This fold back protection is disabled during the soft-start.
This kind of overcurrent protection is effective if the inductor can be completely discharged
during HS MOS turn-off time, in order to avoid the inductor current to run away. In case of
output short-circuit the maximum switching frequency can be computed by Equation 4.
Equation 4
8   V F + R DCR  I LIM 
1
F SW MAX  ----------------------------------------------------------------------  ---------------------V IN –  R ON + R DCR   I LIM T ON MIN
Assuming VF = 0.6 V the freewheeling diode direct voltage, RDCR = 30 m the inductor
parasitic resistance, ILIM = IPK = 1.47 A the peak current limit during foldback protection,
RON = 0.25  the HS MOS resistance and TON,MIN = 120 ns the minimum HS MOS on
duration, the maximum FSW frequency which avoids the inductor current run away in case
of output short-circuit and VIN = 61 V is 708 kHz.
If the programmed switching frequency is higher than the above computed limit, an estimation
of the inductor current in case of output short-circuit fault is provided by Equation 5:
Equation 5
F SW  T ON  V IN – 8  V F
I LIM = ---------------------------------------------------------------------------------------------------------------------8  R DCR + F SW  T ON MIN   R ON + R DCR 
The peak current limit threshold (ILIM) can be programmed in the range 0.85 A - 3.6 A by
selecting the proper RILIM resistor, as suggested in Equation 6:
Equation 6
I PK
R ILIM = 20k  ---------I LIM
IPK is the default L7987 current limit in case of RILIM not mounted, as shown in Table 5 on
page 8.
18/37
DocID025589 Rev 3
L7987
Functional description
Figure 9. Current limit and programming resistor
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The minimum programmed current limit can't be lower than ISKIP = 0.5 A (typical), also in
case of foldback detection.
4.6
Overtemperature protection
It is recommended that the device never exceeds the maximum allowable junction
temperature. This temperature increase is mainly caused by the total power dissipated from
the integrated Power MOSFET.
To avoid any damage to the device when reaching high temperature, the L7987 device
implements a thermal shutdown feature: when the junction temperature reaches 170 °C
(typ.) the device turns off the Power MOSFET and shuts down.
When the junction temperature drops to 155 °C (typ.), the device restarts with a new softstart sequence.
DocID025589 Rev 3
19/37
37
Application information
L7987
5
Application information
5.1
Input capacitor selection
The input capacitor must be rated for the maximum input operating voltage and the
maximum RMS input current.
Since the step-down converters input current is a sequence of pulses from 0 A to IOUT, the
input capacitor must absorb the equivalent RMS current which can be up to the load current
divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these
capacitors must be very high to minimize the power dissipation generated by the internal
ESR, thereby improving system reliability and efficiency.
The RMS input current (flowing through the input capacitor) is roughly estimated by:
Equation 7
I CIN RMS  I OUT  D   1 – D 
Actual DC/DC conversion duty cycle, D = VOUT/VIN, is influenced by a few parameters:
Equation 8
V OUT + V F
D MAX = ---------------------------------------------------V IN MIN – V SW MAX
V OUT + V F
D MIN = ---------------------------------------------------V IN MAX – V SW MIN
where VF is the freewheeling diode forward voltage and VSW the voltage drop across the
internal high-side MOSFET. Considering the range DMIN to DMAX it is possible to determine
the maximum ICIN,RMS flowing through the input capacitor.
The input capacitor value must be dimensioned to safely handle the input RMS current and
to limit the VIN and VCC ramp-up slew-rate to 0.5 V/s maximum, in order to avoid the
device active ESD protections turn-on.
Different capacitors can be considered:

Electrolytic capacitors
These are the most commonly used due to their low cost and wide range of operative
voltage. The only drawback is that, considering ripple current rating requirements, they
are physically larger than other capacitors.

Ceramic capacitors
If available for the required value and voltage rating, these capacitors usually have
a higher RMS current rating for a given physical dimension (due to the very low ESR).
The drawback is their high cost.

Tantalum capacitors
Small, good quality tantalum capacitors with very low ESR are becoming more
available. However, they can occasionally burn if subjected to very high current, for
example when they are connected to the power supply.
The amount of the input voltage ripple can be roughly overestimated by Equation 9.
20/37
DocID025589 Rev 3
L7987
Application information
Equation 9
D   1 – D   I OUT
V IN PP = ---------------------------------------------- + R ES IN  I OUT
C IN  F SW
In case of MLCC ceramic input capacitors, the equivalent series resistance (RES,IN) is
negligible.
In addition to the above considerations, a ceramic capacitor with an appropriate voltage
rating and with a value 1 F or higher should always be placed across VIN and power
ground and across VCC and the IC GND pins, as close as possible to the L7987device. This
solution is necessary for spike filtering purposes.
5.2
Output capacitor selection
The output capacitor is very important in order to satisfy the output voltage ripple
requirement. Using a small inductor value is useful to reduce the size of the choke but
increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is
required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop
gain, which helps to increase the phase margin of the system. If the zero goes to very high
frequency, typical drawback in case of ceramic output capacitor application, a type III
compensation network must be designed.
The current in the output capacitor has a triangular waveform which generates a voltage
ripple across it. This ripple is due to the capacitive component (charge and discharge of the
output capacitor) and the resistive component (due to the voltage drop across its ESR). So
the output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be estimated starting from the current ripple obtained
by the inductor selection. Assuming IL the inductor current ripple, the output voltage ripple
is roughly overestimated by Equation 10.
Equation 10
I L
V OUT PP  I L  R ES OUT + ----------------------------------------8  F SW  C OUT
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR.
The output capacitor is also the key component that provides the current to the load during
a load transient which exceeds the system bandwidth. So, if the high slew rate load
transient is required by the application, the output capacitor must be designed in order to
sustain the load transient or absorbs the energy stored in the inductor until the converter
reacts.
In fact, even if the controller detects immediately the load variation and sets the duty cycle at
100% or 0%, the output current slope is limited by the inductor value, the input and output
voltage.
DocID025589 Rev 3
21/37
37
Application information
L7987
The output voltage has a drop or overshoot that depends on the ESR and capacitive
charge/discharge, as roughly estimated in Equation 11:
Equation 11
L  I OUT
V OUT –LT  I OUT  R ES OUT + I OUT  ---------------------------------------2  C OUT  V L
where VL is the voltage applied to the inductor during the load appliance or load release.
Equation 12
  D MAX   V IN – V OUT 
V L =  
V OUT

MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance that does not minimize the voltage deviation during dynamic load variations.
Electrolytic capacitors, on the other hand, have a large capacitance which minimizes voltage
deviation during load transients whereas they do not show the same ESR values as the
MLCCs, resulting then in higher ripple voltages.
A mix between an electrolytic and MLCC capacitor can be used to minimize ripple as well as
reducing voltage deviation in dynamic mode.
The high bandwidth error amplifier of the L7987 and external compensation feature let
design a wide range of output filter configurations (including all MLCC solutions) and
perform fast transient response.
5.3
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value, in order to have the expected current ripple, must be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In the continuous conduction mode (CCM), the required inductance value can be calculated
by Equation 13:
Equation 13
V OUT
V OUT   1 – --------------

V IN 
L = -------------------------------------------------I L  F SW
In order to guarantee a maximum current ripple in every condition, Equation 13 must be
evaluated in case of maximum input voltage, assuming VOUT fixed.
Increasing the value of the inductance help to reduce the current ripple but, at the same
time, strongly impacts the converter response time to a dynamic load change. The response
time is the time required by the inductor to change its current from the initial to the final
value. Until the inductor has finished its charging (or discharging) time, the output current is
supplied (or recovered) by the output capacitors.
Further, if the compensation network is properly designed, during a load variation the device
is able to properly change the duty cycle so improving the control loop transient response.
When this condition is reached the response time is only limited by the time required to
change the inductor current, basically by VIN, VOUT and L.
Minimizing the response time, at the end, can help to decrease the output filter total cost
and to reduce the application area.
22/37
DocID025589 Rev 3
L7987
5.4
Application information
Compensation network
The compensation network must assure stability and good dynamic performance. The loop
of the L7987 device is based on the voltage mode control. The error amplifier is an
operational amplifier with high bandwidth. So, by selecting the compensation network the
E/A is considered as ideal, that is, its bandwidth is much larger than the system one.
Figure 10. Switching regulator control loop simplified model
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The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to
the LX pin results in an almost constant gain, due to the voltage feed-forward which
generates a sawtooth with amplitude VS directly proportional to the input voltage:
Equation 14
V IN
1
G PWO = --------- = --------- = 30
VS
k FF
The synchronization of the device with an external clock provided through the SYNCH pin
can modify the PWM modulator gain (see Section 4.1 on page 11 to understand how this
gain changes and how to keep it constant in spite of the external synchronization).
DocID025589 Rev 3
23/37
37
Application information
L7987
The transfer function of the power section (i.e. the L-CO filters and the output load) is the
ratio of the parallel of CO and RO and the sum of L and the parallel of CO and RO, including
L and CO parasitics:
Equation 15
1 


CO
s
S
RE
RO
RO

C

RD
S

RO



RE
CO
 1 

C
1 
 


C
D
 

 

RD



L
R
s
S
SRE
RE
CO CO
s CO
s C
S
RD
RE
RO
RO O
C
RO
L
s

S

RE
2
RO
CO
L
s

s
C
GL
︵ ︶

 

given L, RDC, CO, RES and RO the parameters shown in Figure 10. The power section
transfer function can be rewritten as follows:
Equation 16
s
1 + --------------------------2  f zESR
G LC  s  = G LCO  ----------------------------------------------------------------------------2- ;
s
s
1 + ------------------------------- +  --------------------
2  f LC
2  Q  f LC
RO
G LCO = --------------------------  1
R O + R DC
Equation 17
1
f zESR = -------------------------------- ;
2  C O R ES
1
1
f LC = ------------------------------------------------------  ----------------------------------------------------R O + R ES
R O + R ES
2 LC O -------------------------- 2 LC O ------------------------R O + R DC
RO
Equation 18
LC O  R O + R DC  R O + R ES
LC O  R O   R O + R ES 
Q = -----------------------------------------------------------------------------------------------------------  ------------------------------------------------------------------------L + C O   R O R DC + R O R ES + R ES R DC 
L + C O R O R ES
with the assumption that the inductor parasitic resistance, RDC, is negligible compared to
RO. The closed loop gain is then given by:
Equation 19
GLOOP(s) = GLC(s) • GPWO(s)
• GCOMP(s)
As noted in Section 5.2 on page 21, two different kinds of network can compensate the loop,
depending on the value of fzESR, lower or higher than the regulator required bandwidth.
In Section 5.4.1 and Section 5.4.2 the guidelines to select the type II and type III
compensation network are illustrated.
24/37
DocID025589 Rev 3
L7987
5.4.1
Application information
Type II compensation network
If the equivalent series resistance (RES) of the output capacitor introduces a zero with
a frequency lower than the desired bandwidth (that is: 2• RES • CO > 1/BW), this zero
helps stabilize the loop. Electrolytic capacitors show non-negligible ESR (> 30 m typically),
so with this kind of output capacitor the type II network combined with the zero of the ESR
allows to stabilize the loop.
Figure 11. Type II compensation network
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The type II compensation network transfer function, from VOUT to COMP, is computed in
Equation 20.
Equation 20
GCOMPII ( s )  
Z F (s)
1
1  sC F RF



RU
RU s  (C F  C P )  1  sC F  C P RF 
s
2  f Z 1

s 

 1 
2

 f P1 

1
s
2  f P 0
Equation 21
f Z1 
1
;
2  C F  RF
f P0 
1
;
2  C F  C P   RU
f P1 
1
2  C F  C P  RF
The following suggestions can be followed for a quite common compensation strategy,
assuming that CP << CF.

Starting from Equation 19, in case of type II compensation network and electrolytic
output capacitors the control loop gain module at s = 2  • FBW allows to fix the RF/RU
ratio:
Equation 22
1  f LC  RF 1
GLOOP , II ( s  2  f BW ) 



1
k FF f zESR RU f BW
2
DocID025589 Rev 3
25/37
37
Application information
L7987
After choosing the regulator bandwidth (typically FBW < 0.2 • FSW) and a value for RU,
usually between 1 k and 50 k, in order to achieve CF and CP not comparable with
parasitic capacitance of the board, the RF required value is computed by Equation 22.


Select CF in order to place FZ1 below FLC (typically 0.1 • FLC)
Select CP in order to place FP1 at 0.5 • FSW
Equation 23
1
1
C F = ------------------------------------------------ ;C P = ------------------------------------------------2  R F  0.1  f LC
2  R F  0.5  f SW
The resultant control loop and other transfer functions gain are shown in Figure 12.
Figure 12. Type II compensation - bode plot
5.4.2
Type III compensation network
If FzESR is higher than the target loop bandwidth, as usually happens if the output filter is
based on MLCC ceramic capacitors, a type III compensation network must be designed.
26/37
DocID025589 Rev 3
L7987
Application information
Figure 13. Type III compensation network
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The type III compensation network transfer function, from VOUT to COMP, is computed in
Equation 24.
Equation 24

s  
s 
1 
  1 

2  f Z 1   2  f Z 2 
Z F (s)

 1
GCOMPIII ( s)  
RU // Z S ( s)

s
s  
s 
  1 

 1 
2  f P 0  2  f P1   2  f P 2 
In addition to what shown in Equation 21, two more singularities are proper of this
compensation network:
Equation 25
1
f Z2 = ------------------------------------------------------- ;
2  C s   R U + R S 
1
f P2 = ---------------------------2  C S R S
DocID025589 Rev 3
27/37
37
Application information
L7987
The following suggestions can be followed for a quite common compensation strategy,
assuming that CP << CF and RS << RU.

Starting from Equation 19 on page 24, in case of type III compensation network and
MLCC ceramic output capacitors the control loop gain module at s = 2 • FBW allows
to fix the RF/RU ratio:
Equation 26
GLOOP,III ( s  2  f BW ) 
1 f LC RF


1
k FF f BW RU
After choosing the regulator bandwidth (typically FBW < 0.2 • FSW) and a value for RU,
usually between 1 k and 50 k, in order to achieve CF and CP not comparable with
parasitic capacitance of the board, the RF required value is computed by Equation 26.


Select CF in order to place FZ1 below FLC (typically 0.1 • FLC)
Select CP in order to place FP1 at 0.5 • FSW
Equation 27
1
C F = ------------------------------------------------ ;
2  R F  0.1  f LC
1
C P = ------------------------------------------------2  R F  0.5  f SW


Select CS in order to place FZ2 at FLC
Select RS in order to place FP2 at 0.5 • FSW
Equation 28
1
C S = ----------------------------------;
2  R U  f LC
1
R S = -------------------------------------------------2  C S  0.5  f SW
28/37
DocID025589 Rev 3
L7987
Application information
The resultant control loop and other transfer functions gain are shown in Figure 14.
Figure 14. Type III compensation - bode plot
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5.5
Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if junction
temperature goes above 170 °C (typ.). The three different sources of losses within the
device are:

Conduction losses due to the non-negligible RDSON of the power switch; these are
equal to:
Equation 29
PHS,ON = RHS,ON • D
• (IOUT)2
where D is the duty cycle of the application and the maximum RDSON in the full
temperature range is 380 m. Note that the duty cycle is theoretically given by the ratio
between VOUT and VIN, but actually it is quite higher in order to compensate the losses of
the regulator. So the conduction losses increase compared with the ideal case;

Switching losses due to Power MOSFET turn ON and OFF; these can be calculated
as:
Equation 30
 T RISE + T FALL 
P HS SW = V IN  I OUT  -------------------------------------------  f SW  V IN  I OUT  T TR  f SW
2
where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn ON and turn OFF phases.
DocID025589 Rev 3
29/37
37
Application information
L7987
TTR is the equivalent switching time. For this device the typical value for the equivalent
switching time is 20 ns.

Quiescent current losses, calculated as
Equation 31
PQ = VIN • IQOPVIN + VBIAS • IQOPVBIAS
where IQOPVIN and IQOPVBIAS are the L7987 quiescent current in case of separate bias
supply. If the switchover feature is not used, the IC quiescent current is the only one from
VIN, IQUIESC, as summarized in Table 5 on page 8.
The junction temperature TJ can be calculated as:
Equation 32
TJ = TA + Rth,JA • PTOT
where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
RthJA is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The RthJA, measured on the demonstration board described in Section 5.6, is about
40 °C/W for the HTSSOP16 package.
5.6
Layout considerations
The PCB layout of the switching DC/DC regulators is very important to minimize the noise
injected in high impedance nodes and interference generated by the high switching current
loops. Two separated ground areas must be considered: the signal ground and the power
ground.
In a step-down converter the input loop (including the input capacitor, the Power MOSFET
and the freewheeling diode) is the most critical one. This is due to the fact that high value
pulsed currents are flowing through it. In order to minimize the EMI, this loop must be as
short as possible. The input loop, including also the output capacitor, must be referred to the
power ground. All the other components are referred to the signal ground.
The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so the interference can be minimized by placing the routing of the feedback node as far as
possible from the high current paths. To reduce the pick-up noise, the resistor divider must
be placed very close to the device.
To filter the high frequency noise, a small bypass capacitor (1 F or higher) must be added
as close as possible to the input voltage pin of the device for both VIN and VCC pins.
Thanks to the exposed pad of the device, the ground plane helps to reduce the junction to
ambient thermal resistance; so a wide ground plane enhances the thermal performance of
the converter, allowing high power conversion.
The exposed pad must be connected to the signal GND pin. The connection to the ground
plane must be achieved by taking care of the above mentioned input loop, in order to avoid
high current flowing through the signal GND. Refer to Section 6 for the L7987 layout
example.
30/37
DocID025589 Rev 3
L7987
6
Demonstration board
Demonstration board
In this section the L7987 demonstration board is described. The default settings are:

Programmed VOUT = 3.3 V

Max. IOUT = 3 A

FSW = 500 kHz

VBIAS = VOUT

Soft-start 3.5 ms
Figure 15. L7987 demonstration board schematic
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Table 7. L7987 demonstration board component list
Reference
Part
Package
Note
Manufacturer P/N
C1, C2
4.7 F
1210
X7S/100 V/10%
TDK C3225X7S2A475K
C3, C4
1 F
0805
X7S/100 V/10%
TDK C2012X7S2A105K
C5
47 F
1206
X5R/16 V/20%
TDK C3216X5R1C476M
C6
N. M.
C7
100 nF
0603
10 V
C8
10 nF
0603
10 V
C9
33 nF
0603
10 V
C10
22 nF
0603
10 V
C11
1 nF
0603
10 V
R1, R9, R10
N. M.
R2
100 k
0603
R3, R4
0
0603
R5
68 
0603
1% tolerance
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Demonstration board
L7987
Table 7. L7987 demonstration board component list (continued)
Reference
Part
Package
Note
Manufacturer P/N
R6
620 
0603
1% tolerance
R7
6.8 k
0603
1% tolerance
R8
47 k
0603
1% tolerance
R11
2.2 k
0603
1% tolerance
L1
10 H
5x5
4.9 A sat./ 41 m
Coilcraft XAL5050-103
D1
STPS3L60
SMB flat
60 V - 3 A Schottky rectifier
STMicroelectronics STPS3L60
U1
L7987
HTSSOP16
STMicroelectronics L7987
Figure 16. L7987 demonstration board layout (top and bottom)
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Demonstration board
Figure 17. Efficiency vs. output current.
VOUT = 3.3 V, FSW = 500k Hz.
Figure 18. Junction temperature increase vs.
output current. TAMB = 25 °C.
Figure 19. Input quiescent current vs. input
voltage. No load.
Figure 20. Input shutdown current vs. input
voltage
Figure 21. Load regulation.
VOUT = 3.3 V, FSW = 500 kHz.
Figure 22. Line regulation.
VOUT = 3.3 V, FSW = 500 kHz.
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Package information
7
L7987
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
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Package information
Figure 23. HTSSOP16 package outline
Table 8. HTSSOP16 package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
4.90
5.00
5.10
D1
2.80
3.00
3.20
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
2.80
3.00
3.20
e
L
1.05
0.65
0.45
L1
k
1.00
0.60
0.75
1.00
0.00
aaa
8.00
0.10
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Ordering information
8
L7987
Ordering information
Table 9. Order codes
9
Order code
Package
Packaging
L7987
HTSSOP16
Tube
L7987TR
HTSSOP16
Tape and reel
Revision history
Table 10. Document revision history
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Date
Revision
Changes
26-Nov-2013
1
Initial release.
10-Dec-2014
2
Updated Section : Applications on page 1 (added
“tolerant” to “Fail safe system”).
Updated Figure 2: Block diagram on page 4 (replaced
by new figure).
Updated Section 3: Electrical characteristics on page 8
(updated whole Section 3, Table 5: Electrical
characteristics on page 8 replaced by new table, added
notes 2 and 3).
Updated Equation 13: on page 22 (replaced “LL” by
“IL”).
Updated Section 6: Demonstration board on page 31
(added Figure 17 to Figure 22).
04-Mar-2015
3
Updated document status to “production data”.
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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© 2015 STMicroelectronics – All rights reserved
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