NTD110N02R D

NTD110N02R, STD110N02R
Power MOSFET
24 V, 110 A, N−Channel DPAK
Features
•
•
•
•
•
•
•
Planar HD3e Process for Fast Switching Performance
Low RDS(on) to Minimize Conduction Loss
Low Ciss to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(on) TYP
ID MAX
24 V
4.1 mW @ 10 V
110 A
D
N−Channel
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
24
V
Gate−to−Source Voltage − Continuous
VGS
±20
V
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C, Chip
− Continuous @ TC = 25°C
Limited by Package
− Continuous @ TA = 25°C
Limited by Wires
− Single Pulse (tp = 10 ms)
RqJC
PD
1.35
110
°C/W
W
ID
ID
110
110
A
A
ID
32
A
ID
110
A
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
52
2.88
17.5
°C/W
W
A
Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
100
1.5
12.5
°C/W
W
A
TJ, Tstg
−55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL = 15.5 Apk, L = 1.0 mH, RG = 25 W)
EAS
120
mJ
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
TL
260
°C
Operating and Storage Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 11
1
4
1 2
3
DPAK
CASE 369AA
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
AYWW
T
110N2G
Rating
2
1
3
Drain
Gate
Source
A
Y
WW
T110N2
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
Publication Order Number:
NTD110N02R/D
NTD110N02R, STD110N02R
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
24
28
15
Max
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 V, ID = 250 mA)
Positive Temperature Coefficient
Zero Gate Voltage Drain Current
(VDS = 20 V, VGS = 0 V)
(VDS = 20 V, VGS = 0 V, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ±20 V, VDS = 0 V)
IGSS
V
mV/°C
mA
1.5
10
±100
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mA)
Negative Threshold Temperature Coefficient
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 V, ID = 110 A)
(VGS = 4.5 V, ID = 55 A)
(VGS = 10 V, ID = 20 A)
(VGS = 4.5 V, ID = 20 A)
RDS(on)
V
1.0
1.5
5.0
mV/°C
mW
4.1
5.5
3.9
5.5
Forward Transconductance (VDS = 10 V, ID = 15 A) (Note 3)
2.0
4.6
6.2
gFS
44
Mhos
Ciss
2710
3440
Coss
1105
1670
Crss
450
640
td(on)
11
22
tr
39
80
td(off)
27
40
tf
21
40
QT
23.6
28
nC
QGS
5.1
QGD
11
VSD
0.82
0.99
0.65
1.2
V
trr
36.5
ta
30
tb
25
Qrr
0.048
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 20 V, VGS = 0 V, f = 1.0 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VGS = 10 V, VDD = 10 V,
ID = 40 A, RG = 3.0 W)
Fall Time
Gate Charge
(VGS = 4.5 V, ID = 40 A,
VDS = 10 V) (Note 3)
ns
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 20 A, VGS = 0 V) (Note 3)
(IS = 55 A, VGS = 0 V)
(IS = 20 A, VGS = 0 V, TJ = 125°C)
Reverse Recovery Time
(IS = 30 A, VGS = 0 V,
dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge
ns
mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD110N02R, STD110N02R
210
150
5V
4.2 V
4V
3.8 V
3.6 V
3.4 V
3.2 V
100
75
50
3V
2.8 V
2.6 V
2.4 V
25
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VDS ≥ 10 V
4.5 V
6V
125
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
10 V
8V
2
4
8
6
180
150
120
90
TJ = 175°C
60
TJ = 25°C
30
TJ = −55°C
0
10
0
2
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 110 A
TJ = 25°C
0.02
0.01
0
2
6
4
8
10
0.014
TJ = 25°C
0.012
0.01
0.008
VGS = 4.5 V
0.006
0.004
VGS = 10 V
0.002
0
20
40
60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100,000
2.0
VGS = 0 V
ID = 55 A
VGS = 10 V
TJ = 175°C
10,000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
80 100 120 140 160 180 200 220 240
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
1.6
1.4
1.2
1.0
1000
100
TJ = 100°C
0.8
0.6
−50
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.03
1.8
6
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
175
−25
0
25
50
75
100
125
150
175
10
0
5.0
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
25
C, CAPACITANCE (pF)
VDS = 0 V VGS = 0 V
TJ = 25°C
Ciss
4000
3000
Ciss
2000
Crss
Coss
1000
Crss
0
10
0
5
VGS
5
10
15
20
5
20
QT
4
16
VGS
QGS
3
QDS
12
VDS
2
8
1
4
ID = 40 A
TJ = 25°C
0
0
5
VDS
10
15
20
0
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
5000
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTD110N02R, STD110N02R
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
td(off)
tf
100
tr
10
td(on)
1
1
10
100
100
VGS = 0 V
TJ = 25°C
80
60
40
20
0
0.4
0.8
0.6
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
1000
ID, DRAIN CURRENT (AMPS)
t, TIME (ns)
IS, SOURCE CURRENT (AMPS)
120
VDS = 10 V
ID = 55 A
VGS = 10 V
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
1 ms
10 ms
10
dc
RDS(on) Limit
Thermal Limit
Package Limit
1.0
0.1
1.0
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
1.2
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
NTD110N02R, STD110N02R
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.00001
0.0001
0.001
0.01
0.1
1.0
10
t, TIME (s)
Figure 12. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD110N02RT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
STD110N02RT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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5
NTD110N02R, STD110N02R
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
A
E
b3
c2
B
4
L3
Z
D
1
2
H
DETAIL A
3
L4
b2
e
c
b
0.005 (0.13)
M
C
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
2.58
0.101
5.80
0.228
3.0
0.118
1.6
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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6
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For additional information, please contact your local
Sales Representative
NTD110N02R/D