SmartFusion2 and IGLOO2 Macro Library User Guide - Libero SoC v11.5

SmartFusion2 and IGLOO2 Macro Library
Guide
SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - All Macros
AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ARI1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
BIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
BIBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . . 39
BUFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . 41
CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DDR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DFN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN1E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DFN1E1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DFN1E1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DFN1P0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DLN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DLN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DLN1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FCEND_BUFF. . . . . . . . . . . . . . . . . . . . . . . . 19
FCINIT_BUFF . . . . . . . . . . . . . . . . . . . . . . . . 20
GCLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . . 21
GCLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
GCLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . 21
GCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
INBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . . 42
INV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
NAND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
NAND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
NAND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
NOR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
NOR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
NOR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
OR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
OUTBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . 43
RAM1K18 . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RAM64x18 . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RGCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . .
SLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRIBUFF_DIFF . . . . . . . . . . . . . . . . . . . . . . .
UJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
14
15
16
44
44
38
34
35
36
37
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SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - Combinatorial Logic
AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARI1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
17
13
12
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
36
37
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SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - Sequential Logic
DFN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN1E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DFN1E1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DFN1E1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DFN1P0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DLN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DLN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DLN1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - RAM Blocks
RAM1K18 . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RAM64x18. . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - Math Blocks
MACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - I/Os
BIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . .
CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . .
DDR_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . .
GCLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . .
INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . .
OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . .
TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRIBUFF_DIFF . . . . . . . . . . . . . . . . . . . . . . .
UJTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
40
40
41
45
46
21
20
21
42
42
43
43
44
44
38
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SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - Clocking
CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . .
CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . .
GCLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . .
GCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RGCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . .
40
40
41
13
21
20
21
14
14
15
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SmartFusion2 and IGLOO2 Macro Library Guide
Table of Contents - Special
FCEND_BUFF. . . . . . . . . . . . . . . . . . . . . . . . 19
FCINIT_BUFF . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Introduction
This macro library guide supports the SmartFusion2 and IGLOO2 families. See the Microsemi website
for macro guides for other families.
This guide follows a naming convention for sequential macros that is unambiguous and extensible,
making it possible to understand the function of the macros by their name alone.
The first two mandatory characters of the macro name will indicate the basic macro function:
•
DF - D-type flip-flop
•
DL - D-type latch
The next mandatory character indicates the output polarity:
•
I - output inverted (QN with bubble)
•
N - output non-inverted (Q without bubble)
The next mandatory number indicates the polarity of the clock or gate:
•
1 - rising edge triggered flip-flop or transparent high latch (non-bubbled)
•
0 - falling edge triggered flip-flop or transparent low latch (bubbled)
The next two optional characters indicate the polarity of the Enable pin, if present:
•
E0 - active low enable (bubbled)
•
E1 - active high enable (non-bubbled)
The next two optional characters indicate the polarity of the asynchronous Preset pin, if present:
•
P0 - active low asynchronous preset (bubbled)
•
P1 - active high asynchronous preset (non-bubbled)
The next two optional characters indicate the polarity of the asynchronous Clear pin, if present:
•
C0 - active low asynchronous clear (bubbled)
•
C1 - active high asynchronous clear (non-bubbled)
All sequential and combinatorial macros (except MX4 and XOR8) use one logic element in the
SmartFusion2 and IGLOO2 families.
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SmartFusion2 and IGLOO2 Macro Library Guide
AND2
2-Input AND
A
Y
B
Figure 1 • AND2
Inputs
Output
A, B
Y
Truth Table
A
B
Y
X
0
0
0
X
0
1
1
1
AND3
3-Input AND
A
B
Y
C
Figure 2 • AND3
Input
Output
A, B, C
Y
Truth Table
A
B
C
Y
X
X
0
0
X
0
X
0
0
X
X
0
1
1
1
1
11
SmartFusion2 and IGLOO2 Macro Library Guide
AND4
4-Input AND
A
B
Y
C
D
Figure 3 • AND4
Input
Output
A, B, C, D
Y
Truth Table
A
B
C
D
Y
X
X
X
0
0
X
X
0
X
0
X
0
X
X
0
0
X
X
X
0
1
1
1
1
1
BUFF
Buffer
A
Figure 4 • BUFF
Input
Output
A
Y
Truth Table
12
A
Y
0
0
1
1
Y
SmartFusion2 and IGLOO2 Macro Library Guide
BUFD
Buffer. Note that Compile optimization will not remove this macro.
A
Y
Figure 5 • BUFD
Input
Output
A
Y
Truth Table
A
Y
0
0
1
1
CLKINT
Macro used to route an internal fabric signal to global network.
A
Y
Figure 6 • CLKINT
Input
Output
A
Y
Truth Table
A
Y
0
0
1
1
13
SmartFusion2 and IGLOO2 Macro Library Guide
GCLKINT
Gated macro used to route an internal fabric signal to global network. The Enable signal can be used to turn off the
global network to save power.
EN
A
Y
Figure 7 • GCLKINT
Input
Output
A, EN
Y
Truth Table
A
EN
Y
X
0
0
0
X
0
1
1
1
RCLKINT
Macro used to route an internal fabric signal to a row global buffer, thus creating a local clock.
A
Figure 8 • RCLKINT
Input
Output
A
Y
Truth Table
14
A
Y
0
0
1
1
Y
SmartFusion2 and IGLOO2 Macro Library Guide
RGCLKINT
Gated macro used to route an internal fabric signal to a row global buffer, thus creating a local clock. The Enable signal
can be used to turn off the local clock to save power.
EN
A
Y
Figure 9 • RGCLKINT
Input
Output
A, EN
Y
Truth Table
A
EN
Y
X
0
0
0
X
0
1
1
1
15
SmartFusion2 and IGLOO2 Macro Library Guide
SLE
Sequential Logic Element
Q
D
CLK
EN
ALn
ADn
SLn
SD
LAT
Figure 10 • SLE
Input
Output
D, CLK, EN, ALn, ADn, SLn, SD, LAT
Q
Truth Table
ALn
ADn
LAT
CLK
EN
SLn
SD
D
Qn+1
0
ADn
X
X
X
X
X
X
!ADn
1
X
0
Not rising
X
X
X
X
Qn
1
X
0
0
X
X
X
Qn
1
X
0
1
0
SD
X
SD
1
X
0



1
1
X
D
D
1
X
1
0
X
X
X
X
Qn
1
X
1
1
0
X
X
X
Qn
1
X
1
1
1
0
SD
X
SD
1
X
1
1
1
1
X
D
D
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SmartFusion2 and IGLOO2 Macro Library Guide
ARI1
The ARI1 macro is responsible for representing all arithmetic operations in the pre-layout phase
A
B
Y
C
S
D
FCO
FCI
Figure 11 • ARI1
Input
Output
A, B, C, D, FCI
Y, S, FCO
The ARI1 cell has a 20bit INIT string parameter that is used to configure its functionality. The interpretation of the 16
LSB of the INIT string is shown in the table below. F0 is the value of Y when A = 0 and F1 is the value of Y when A = 1.
Table 1 • Interpretation of 16 LSB of the INIT String for ARI1
ADCB
Y
0000
INIT[0]
0001
INIT[1]
0010
INIT[2]
0011
INIT[3]
0100
INIT[4]
0101
INIT[5]
0110
INIT[6]
0111
INIT[7]
1000
INIT[8]
1001
INIT[9]
1010
INIT[10]
1011
INIT[11]
1100
INIT[12]
1101
INIT[13]
1110
INIT[14]
1111
INIT[15]
F0
F1
17
SmartFusion2 and IGLOO2 Macro Library Guide
Table 2 • Truth Table for S
Y
FCI
S
0
0
0
0
1
1
1
0
1
1
1
0
Figure 12 • ARI1 Logic
The 4 MSB of the INIT string controls the output of the carry bits. The carry is generated using carry propagation and
generation bits, which are evaluated according to the tables below.
Table 3 • ARI1 INIT[17:16] String Interpretation
INIT[17]
INIT[16]
G
0
0
0
0
1
F0
1
0
1
1
1
F1
18
SmartFusion2 and IGLOO2 Macro Library Guide
Table 4 • ARI1 INIT[19:18] String Interpretation
INIT[19]
INIT[18]
P
0
0
0
0
1
Y
1
X
1
Table 5 • FCO Truth Table
P
G
FCI
FCO
0
G
X
G
1
X
FCI
FCI
FCEND_BUFF
Buffer, driven by the FCO pin of the last macro in the Carry-Chain.
A
Y
Figure 13 • FCEND_BUFF
Input
Output
A
Y
Truth Table
A
Y
0
0
1
1
19
SmartFusion2 and IGLOO2 Macro Library Guide
FCINIT_BUFF
Buffer, used to initialize the FCI pin of the first macro in the Carry-Chain.
A
Y
Figure 14 • FCINIT_BUFF
Input
Output
A
Y
Truth Table
A
Y
0
0
1
1
GCLKBUF
Gated input I/O macro to global network; the Enable signal can be used to turn off the global network to save power.
EN
PAD
Figure 15 • GCLKBUF
Input
Output
PAD, EN
Y
Truth Table
PAD
EN
Y
X
0
0
Z
1
X
0
X
0
1
1
1
20
Y
SmartFusion2 and IGLOO2 Macro Library Guide
GCLKBUF_DIFF
Gated differential I/O macro to global network; the Enable signal can be used to turn off the global network, Differential
I/O
EN
PADA
Y
PADB
Figure 16 • GCLKBUF_DIFF
Differential
Input
Output
PAD, EN
Y
Truth Table
PADP
PADN
EN
Y
X
X
0
0
Z
Z
1
X
0
0
1
X
1
1
1
X
0
1
1
0
1
0
1
1
GCLKBIBUF
Bidirectional I/O macro with gated input to global network; the Enable signal can be used to turn off the global network
to save power.
E
D
PAD
Y
EN
Figure 17 • GCLKBIBUF
Input
Output
D, E, EN, PAD
Y, PAD
Truth Table
D
E
EN
PAD
Y
X
0
0
X
0
X
0
1
Z
X
21
SmartFusion2 and IGLOO2 Macro Library Guide
D
E
EN
PAD
Y
X
0
1
PAD
PAD
D
1
0
D
0
D
1
1
D
D
DFN1
D-Type Flip-Flop
D
Q
CLK
Figure 18 • DFN1
Input
Output
D, CLK
Q
Truth Table
CLK
D
Qn+1
not Rising
X
Qn

D
D
DFN1C0
D-Type Flip-Flop with active low Clear
Q
D
CLK
CLR
Figure 19 • DFN1C0
Input
Output
D, CLK, CLR
Q
Truth Table
22
CLR
CLK
D
Qn+1
0
X
X
0
SmartFusion2 and IGLOO2 Macro Library Guide
CLR
CLK
D
Qn+1
1
not Rising
X
Qn
1

D
D
DFN1E1
D-Type Flip-Flop with active high Enable
Q
D
E
CLK
Figure 20 • DFN1E1
Input
Output
D, E, CLK
Q
Truth Table
E
CLK
D
Qn+1
0
X
X
Qn
1
not Rising
X
Qn
1

D
D
DFN1E1C0
D-Type Flip-Flop, with active high Enable and active low Clear.
D
Q
E
CLK
CLR
Figure 21 • DFN1E1C0
Input
Output
CLR, D, E, CLK
Q
Truth Table
CLR
E
CLK
D
Qn+1
0
X
X
X
0
23
SmartFusion2 and IGLOO2 Macro Library Guide
24
CLR
E
CLK
D
Qn+1
1
0
X
X
Qn
1
1
not Rising
X
Qn
1
1

D
D
SmartFusion2 and IGLOO2 Macro Library Guide
DFN1E1P0
D-Type Flip-Flop with active high Enable and active low Preset.
PRE
D
Q
E
CLK
Figure 22 • DFN1E1P0
Input
Output
D, E, PRE, CLK
Q
Truth Table
PRE
E
CLK
D
Qn+1
0
X
X
X
1
1
0
X
X
Qn
1
1
not Rising
X
Qn
1
1

D
D
25
SmartFusion2 and IGLOO2 Macro Library Guide
DFN1P0
D-Type Flip-Flop with active low Preset.
PRE
D
Q
CLK
Figure 23 • DFN1P0
Input
Output
D, PRE, CLK
Q
Truth Table
PRE
CLK
D
Qn+1
0
X
X
1
1
not Rising
X
Qn
1

D
D
DLN1
Data Latch
D
G
Figure 24 • DLN1
Input
Output
D, G
Q
Truth Table
26
G
D
Q
0
X
Q
1
D
D
Q
SmartFusion2 and IGLOO2 Macro Library Guide
DLN1C0
Data Latch with active low Clear
Q
D
G
CLR
Figure 25 • DLN1C0
Input
Output
CLR, D, G
Q
Truth Table
CLR
G
D
Q
0
X
X
0
1
0
X
Q
1
1
D
D
DLN1P0
Data Latch with active low Preset
D
PRE
Q
G
Figure 26 • DLN1P0
Input
Output
D, G, PRE
Q
Truth Table
PRE
G
D
Q
0
X
X
1
1
0
X
Q
1
1
D
D
27
SmartFusion2 and IGLOO2 Macro Library Guide
INV
Inverter
A
Y
Figure 27 • INV
Input
Output
A
Y
Truth Table
A
Y
0
1
1
0
INVD
Inverter; note that Compile optimization will not remove this macro.
A
Figure 28 • INVD
Input
Output
A
Y
Truth Table
28
A
Y
0
1
1
0
Y
SmartFusion2 and IGLOO2 Macro Library Guide
MX2
2 to 1 Multiplexer
A
S
Y
B
Figure 29 • MX2
Input
Output
A, B, S
Y
Truth Table
A
B
S
Y
A
X
0
A
X
B
1
B
MX4
4 to 1 Multiplexer
This macro uses two logic modules.
D0
S0
S1
D1
Y
D2
D3
Figure 30 • MX4
Input
Output
D0, D1, D2, D3, S0, S1
Y
Truth Table
D3
D2
D1
D0
S1
S0
Y
X
X
X
D0
0
0
D0
X
X
D1
X
0
1
D1
X
D2
X
X
1
0
D2
D3
X
X
X
1
1
D3
29
SmartFusion2 and IGLOO2 Macro Library Guide
NAND2
2-Input NAND
A
Y
B
Figure 31 • NAND2
Input
Output
A, B
Y
Truth Table
A
B
Y
X
0
1
0
X
1
1
1
0
NAND3
3-Input NAND
A
Y
B
C
Figure 32 • NAND3
Input
Output
A, B, C
Y
Truth Table
30
A
B
C
Y
X
X
0
1
X
0
X
1
0
X
X
1
1
1
1
0
SmartFusion2 and IGLOO2 Macro Library Guide
NAND4
4-input NAND
A
B
Y
C
D
Figure 33 • NAND4
Input
Output
A, B, C, D
Y
Truth Table
A
B
C
D
Y
X
X
X
0
1
X
X
0
X
1
X
0
X
X
1
0
X
X
X
1
1
1
1
1
0
NOR2
2-input NOR
A
Y
B
Figure 34 • NOR2
Input
Output
A, B
Y
Truth Table
A
B
Y
0
0
1
X
1
0
1
X
0
31
SmartFusion2 and IGLOO2 Macro Library Guide
NOR3
3-input NOR
A
Y
B
C
Figure 35 • NOR3
Input
Output
A, B, C
Y
Truth Table
A
B
C
Y
0
0
0
1
X
X
1
0
X
1
X
0
1
X
X
0
NOR4
4-input NOR
A
B
Y
C
D
Figure 36 • NOR4
Input
Output
A, B, C, D
Y
Truth Table
32
A
B
C
D
Y
0
0
0
0
1
1
X
X
X
0
X
1
X
X
0
X
X
1
X
0
X
X
X
1
0
SmartFusion2 and IGLOO2 Macro Library Guide
OR2
2-input OR
A
Y
B
Figure 37 • OR2
Input
Output
A, B
Y
Truth Table
A
B
Y
0
0
0
X
1
1
1
X
1
OR3
3-input OR
A
B
Y
C
Figure 38 • OR3
Input
Output
A, B, C
Y
Truth Table
A
B
C
Y
0
0
0
0
X
X
1
1
X
1
X
1
1
X
X
1
33
SmartFusion2 and IGLOO2 Macro Library Guide
OR4
4-input OR
A
B
Y
C
D
Figure 39 • OR4
Input
Output
A, B, C, D
Y
Truth Table
A
B
C
D
Y
0
0
0
0
0
1
X
X
X
1
X
1
X
X
1
X
X
1
X
1
X
X
X
1
1
XOR2
2-input XOR
A
Y
B
Figure 40 • XOR2
Input
Output
A, B
Y
Truth Table
34
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
SmartFusion2 and IGLOO2 Macro Library Guide
XOR3
3-input XOR
A
B
Y
C
Figure 41 • XOR3
Input
Output
A, B, C
Y
Truth Table
A
B
C
Y
0
0
0
0
1
0
0
1
0
1
0
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
1
35
SmartFusion2 and IGLOO2 Macro Library Guide
XOR4
4-input XOR
A
B
Y
C
D
Figure 42 • XOR4
Input
Output
A, B, C, D
Y
Truth Table
36
A
B
C
D
Y
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
SmartFusion2 and IGLOO2 Macro Library Guide
XOR8
8-input XOR
This macro uses two logic modules.
A
B
C
D
Y
E
F
G
H
Figure 43 • XOR8
Input
Output
A, B, C, D, E, F, G, H
Y
Truth Table
If you have an odd number of inputs that are High, the output is High (1).
If you have an even number of inputs that are High, the output is Low (0).
For example:
A
B
C
D
E
F
G
H
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
37
SmartFusion2 and IGLOO2 Macro Library Guide
UJTAG
The UJTAG macro is a special purpose macro. It allows access to the user JTAG circuitry on board the chip.
You must instantiate a UJTAG macro in your design if you plan to make use of the user JTAG feature. The TMS, TDI,
TCK, TRSTB and TDO pins of the macro must be connected to top level ports of the design.
UTDO
TMS
TDI
TCK
TRSTB
Figure 44 • UJTAG
Input
UTDO
TMS
TDI
TCK
TRSTB
38
Output
URSTB
UDRCK
UDRCAP
UDRSH
UDRUPD
UTDI
UIREG[7:0]
TDO
URSTB
UDRCK
UDRCAP
UDRSH
UDRUPD
UTDI
UIREG[7:0]
SmartFusion2 and IGLOO2 Macro Library Guide
BIBUF
Bidirectional Buffer
E
D
PAD
Y
Figure 45 • BIBUF
Input
Output
D, E, PAD
PAD, Y
Truth Table
MODE
E
D
PAD
Y
OUTPUT
1
D
D
D
INPUT
0
X
Z
X
INPUT
0
X
PAD
PAD
BIBUF_DIFF
Bidirectional Buffer, Differential I/O
E
PADP
D
PADN
Y
Figure 46 • BIBUF_DIFF
Input
Output
D, E, PADP, PADN
PADP, PADN, Y
Truth Table
MODE
E
D
PADP
PADN
Y
OUTPUT
1
0
0
1
0
OUTPUT
1
1
1
0
1
INPUT
0
X
Z
Z
X
INPUT
0
X
0
0
X
INPUT
0
X
1
1
X
INPUT
0
X
0
1
0
INPUT
0
X
1
0
1
39
SmartFusion2 and IGLOO2 Macro Library Guide
CLKBIBUF
Bidirectional Buffer with Input to global network
D
E
PAD
Y
Figure 47 • CLKBIBUF
Input
Output
D, E, PAD
PAD, Y
Truth Table
D
E
PAD
Y
X
0
Z
X
X
0
0
0
X
0
1
1
0
1
0
0
1
1
1
1
CLKBUF
Input Buffer to global network
PAD
Figure 48 • CLKBUF
Input
Output
PAD
Y
Truth Table
40
PAD
Y
0
0
1
1
Y
SmartFusion2 and IGLOO2 Macro Library Guide
CLKBUF_DIFF
Differential I/O macro to global network, Differential I/O
PADP
Y
PADN
Figure 49 • INBUF_DIFF
Input
Output
PADP, PADN
Y
Truth Table
PADP
PADN
Y
Z
Z
Y
0
0
X
1
1
X
0
1
0
1
0
1
41
SmartFusion2 and IGLOO2 Macro Library Guide
INBUF
Input Buffer
PAD
Y
Figure 50 • INBUF
Input
Output
PAD
Y
Truth Table
PAD
Y
Z
X
0
0
1
1
INBUF_DIFF
Input Buffer, Differential I/O
PADP
Y
PADN
Figure 51 • INBUF_DIFF
Input
Output
PADP, PADN
Y
Truth Table
PADP PADN
42
Y
Z
Z
X
0
0
X
1
1
X
0
1
0
1
0
1
SmartFusion2 and IGLOO2 Macro Library Guide
OUTBUF
Output buffer
D
PAD
Figure 52 • OUTBUF
Input
Output
D
PAD
Truth Table
D
PAD
0
0
1
1
OUTBUF_DIFF
Output buffer, Differential I/O
PADP
D
PADN
Figure 53 • OUTBUF_DIFF
Input
Output
D
PADP, PADN
Truth Table
D
PADP PADN
0
0
1
1
1
0
43
SmartFusion2 and IGLOO2 Macro Library Guide
TRIBUFF
Tristate output buffer
E
D
PAD
Figure 54 • TRIBUFF
Input
Output
D, E
PAD
Truth Table
D
E
PAD
X
0
Z
D
1
D
TRIBUFF_DIFF
Tristate output buffer, Differential I/O
E
PADP
D
PADN
Figure 55 • TRIBUFF_DIFF
Input
Output
D, E
PADP, PADN
Truth Table
44
D
E
PADP PADN
X
0
Z
Z
0
1
0
1
1
1
1
0
SmartFusion2 and IGLOO2 Macro Library Guide
DDR_IN
Input DDR Register; input D must be connected to an I/O.
D
QR
CLK
QF
EN
ALn
ADn
SLn
SD
Figure 56 • DDR_IN
Input
Output
D, CLK, EN, ALn, ADn, SLn, SD
QR, QF
Truth Table
ALn
ADn
CLK
EN
SLn
SD
D
QR(n+1)
QF(n+1)
1
X
-
X
X
X
X
QRn
QFn
1
X
0
X
X
X
QRn
QFn
1
X
1
1
X
D
D
QFn
1
X
1
1
X
D
QRn
D
1
X




1
0
SD
X
SD
SD
0
ADn
X
X
X
X
X
!ADn
!ADn
45
SmartFusion2 and IGLOO2 Macro Library Guide
DDR_OUT
DDR Output register; output Q must be connected to an I/O.
DR
Q
DF
CLK
EN
ALn
ADn
SLn
SD
Figure 57 • DDR_OUT
Input
Output
DR, DF, CLK, EN, ALn, ADn, SLn, SD
Q
Truth Table
ALn
ADn
CLK
EN
SLn
SD
DR
DF
Qr
Qf
Q
0
ADn
X
X
X
X
X
X
!ADn
!ADn
!ADn
1
X
0
X
X
X
X
X
Qr
Qf
Qf
1
X
1
X
X
X
X
X
Qr
Qf
Qr
1
X
0
X
X
X
X
Qr
Qf
Qr
1
X
1
0
SD
X
X
SD
SD
SD
1
X



1
1
X
DR
DF
DR
DF
DR
46
SmartFusion2 and IGLOO2 Macro Library Guide
RAM1K18
The RAM1K18 block contains 18,432 memory bits and is a true dual-port memory. The RAM1K18 memory can also be
configured in two-port mode. All read/write operations to the RAM1K18 memory are synchronous. To improve the read
data delay, an optional pipeline register at the output is available. A feed-through write mode is also available to enable
immediate access to the write data. The RAM1K18 memory has two data ports which can be independently configured
in any combination shown below.
1. Dual-Port RAM with the following configurations:
–
1Kx18, 1Kx16
–
2Kx9, 2Kx8
–
4Kx4
–
8Kx2
–
16Kx1
2. Two-Port RAM with the following configurations:
–
512x36, 512x32
–
1Kx18, 1Kx16
–
2Kx9, 2Kx8
–
4Kx4
–
8Kx2
–
16Kx1
The main features of the RAM1K18 memory block are as follows:
•
A RAM1K18 block has 18,432 bits.
•
A RAM1K18 block provides two independent data ports A and B.
•
RAM1K18 has a true dual-port mode, for which both ports have word widths less than or equal to 18 bits.
•
In true dual-port mode, each port can be independently configured to any of the following depth/width: 1Kx18,
1Kx16, 2Kx9, 2Kx8, 4Kx4, 8Kx2, and 16Kx1.
•
The widths of each port can be different, but one needs to be a multiple of the other. There are 29 unique
combinations of true dual-port aspect ratios:
–
1Kx18/1Kx18, 1Kx18/2Kx9,
–
1Kx16/1Kx16, 1Kx16/2Kx8, 1Kx16/4Kx4, 1Kx16/8Kx2, 1Kx16/16Kx1,
–
2Kx9/1Kx18, 2Kx9/2Kx9,
–
2Kx8/1Kx16, 2Kx8/2Kx8, 2Kx8/4Kx4, 2Kx8/8Kx2, 2Kx8/16Kx1,
–
4Kx4/1Kx16, 4Kx4/2Kx8, 4Kx4/4Kx4, 4Kx4/8Kx2, 4Kx4/16Kx1,
–
8Kx2/1Kx16, 8Kx2/2Kx8, 8Kx2/4Kx4, 8Kx2/8Kx2, 8Kx2/16Kx1,
–
16Kx1/1Kx16, 16Kx1/2Kx8, 16Kx1/4Kx4, 16Kx1/8Kx2, 16Kx1/16Kx1
•
RAM1K18 also has a two-port mode. In this case, Port A will become the read port and Port B becomes the
write port.
•
In two-port mode, each port can be independently configured to any of the following depth/width: 512x36,
512x32, 1Kx18, 1Kx16, 2Kx9, 2Kx8, 4Kx4, 8Kx2 and 16Kx1.
•
The widths of each port can be different, but one needs to be a multiple of the other. There are 45 unique
combinations of two-port aspect ratios:
–
512x36/512x36, 512x36/1Kx18, 512x36/2Kx9,
–
512x32/512x32, 512x32/1Kx16, 512x32/2Kx8, 512x32/4Kx4, 512x32/8Kx2, 512x32/16Kx1,
–
1Kx18/512x36, 1Kx18/1Kx18, 1Kx18/2Kx9,
–
1Kx16/512x32, 1Kx16/1Kx16, 1Kx16/2Kx8, 1Kx16/4Kx4, 1Kx16/8Kx2, 1Kx16/16Kx1,
–
2Kx9/512x36, 2Kx9/1Kx18, 2Kx9/2Kx9,
–
2Kx8/512x32, 2Kx8/1Kx16, 2Kx8/2Kx8, 2Kx8/4Kx4, 2Kx8/8Kx2, 2Kx8/16Kx1,
–
4Kx4/512x32, 4Kx4/1Kx16, 4Kx4/2Kx8, 4Kx4/4Kx4, 4Kx4/8Kx2, 4Kx4/16Kx1,
–
8Kx2/512x32, 8Kx2/1Kx16, 8Kx2/2Kx8, 8Kx2/4Kx4, 8Kx2/8Kx2, 8Kx2/16Kx1,
47
SmartFusion2 and IGLOO2 Macro Library Guide
–
16Kx1/512x32, 16Kx1/1Kx16, 16Kx1/2Kx8, 16Kx1/4Kx4, 16Kx1/8Kx2, 16Kx1/16Kx1
•
RAM1K18 performs synchronous operation for setting up the address as well as writing and reading the data.
The address, data, block port select and write-enable inputs are registered.
•
An optional pipeline register with a separate enable, synchronous-reset and asynchronous-reset is available at
the read data port to improve the clock-to-out delay.
•
There is an independent clock for each port. The memory will be triggered at the rising edge of the clock.
•
The true dual-port mode supports an optional feed-through write mode, where the write data also appears on
the corresponding read data port.
•
Read from both ports at the same location is allowed.
•
Read and write on the same location at the same time results in unknown data to be read. There is no
collision prevention or detection. However, correct data is expected to be written into the memory.
Figure 58 shows a simplified block diagram of the RAM1K18 memory block and Table 6 gives the port descriptions.
The simplified block diagram illustrates the two independent data ports, the pipeline registers, and the feed-through
multiplexors.
Figure 58 • Simplified Block Diagram of RAM1K18
Table 6 • Port RAM List for RAM1K18
Pin Name
Pin
Direction
Type1
Description
A_ADDR[13:0]
Input
Dynamic Port A address
A_BLK[2:0]
Input
Dynamic Port A block selects
A_CLK
Input
Dynamic Port A clock
A_DIN[17:0]
Input
Dynamic Port A write data
Output
Dynamic Port A read data
A_DOUT[17:0]
48
Polarity
High
Rising
SmartFusion2 and IGLOO2 Macro Library Guide
Table 6 • Port RAM List for RAM1K18
Pin Name
Pin
Direction
Type1
Description
Polarity
A_WEN[1:0]
Input
Dynamic Port A write enables (per byte)
A_WIDTH[2:0]
Input
Static
Port A width/depth mode select
A_WMODE
Input
Static
Port A feed-through write select
A_ARST_N
Input
Dynamic Port A reset (must be tied to 1)
Low
A_DOUT_LAT
Input
Static
Low
A_DOUT_ARST_N
Input
Dynamic Port A pipeline register asynchronous reset
A_DOUT_CLK
Input
Dynamic
A_DOUT_EN
Input
Dynamic Port A pipeline register enable
High
A_DOUT_SRST_N
Input
Dynamic Port A pipeline register synchronous reset
Low
B_ADDR[13:0]
Input
Dynamic Port B address
B_BLK[2:0]
Input
Dynamic Port B block selects
B_CLK
Input
Dynamic Port B clock
B_DIN[17:0]
Input
Dynamic Port B write data
Output
Dynamic Port B read data
B_DOUT[17:0]
Port A pipeline register select
Port A pipeline register clock (must be tied to
A_CLK or 1)
High
High
Low
Rising
High
Rising
B_WEN[1:0]
Input
Dynamic Port B write enables (per byte)
B_WIDTH[2:0]
Input
Static
Port B width/depth mode select
B_WMODE
Input
Static
Port B Feed-through write select
B_ARST_N
Input
Dynamic Port B reset (must be tied to 1)
Low
B_DOUT_LAT
Input
Static
Low
B_DOUT_ARST_N
Input
Dynamic Port B pipeline register asynchronous reset
B_DOUT_CLK
Input
Dynamic Port B pipeline register clock (must be tied to
B_CLK or 1)
B_DOUT_EN
Input
Dynamic Port B pipeline register enable
High
B_DOUT_SRST_N
Input
Dynamic Port B pipeline register synchronous reset
Low
A_EN
Input
Static
Port A power down (must be tied to 1)
Low
B_EN
Input
Static
Port B power down (must be tied to 1)
Low
SII_LOCK
Input
Static
Lock access to SII
High
BUSY
Output
Port B pipeline register select
Dynamic Busy signal from SII
High
High
Low
Rising
High
49
SmartFusion2 and IGLOO2 Macro Library Guide
Note: Static inputs are defined at design time and need to be tied to 0 or 1.
Signal Descriptions for RAM1K18
A_WIDTH and B_WIDTH
Table 7 lists the width/depth mode selections for each port. Two-port mode is in effect when the width of at least one
port is 36, and A_WIDTH indicates the read width while B_WIDTH indicates the write width. Also, when the write width
is 36, the read width must also be 36.
Table 7 • Width/Depth Mode Selection
Depth x Width
A_WIDTH/B_WIDTH
16Kx1
000
8Kx2
001
4Kx4
010
2Kx8, 2Kx9
011
1Kx16, 1Kx18
100
512x32, 512x36
(Two-port)
101
11x
A_WEN and B_WEN
Table 8 lists the write/read control signals for each port. Two-port mode is in effect when the width of at least one port
is 36, and read operation is always enabled. Also, when the write width is 36, both A_WEN and B_WEN must be static.
Table 8 • Write/Read Operation Select
Depth x Width
Result
16Kx1, 8Kx2, 4Kx4,
2Kx8, 2Kx9,
1Kx16, 1Kx18
00
Perform a read operation
16Kx1,
8Kx2,
4Kx4,
2Kx8,
2Kx9
01
Perform a write operation
01
Write [7:0]
10
Write [16:9]
11
Write [16:9], [7:0]
01
Write [8:0]
10
Write [17:9]
11
Write [17:0]
1Kx16
1Kx18
50
A_WEN/B_WEN
SmartFusion2 and IGLOO2 Macro Library Guide
Table 8 • Write/Read Operation Select
Depth x Width
512x32
(Two-port write)
512x36
(Two-port write)
A_WEN/B_WEN
Result
B_WEN[0] = 1
Write B_DIN[7:0]
B_WEN[1] = 1
Write B_DIN[16:9]
A_WEN[0] = 1
Write A_DIN[7:0]
A_WEN[1] = 1
Write A_DIN[16:9]
B_WEN[0] = 1
Write B_DIN[8:0]
B_WEN[1] = 1
Write B_DIN[17:9]
A_WEN[0] = 1
Write A_DIN[8:0]
A_WEN[1] = 1
Write A_DIN[17:9]
A_ADDR and B_ADDR
Table 9 address buses for the two ports. Fourteen bits are needed to address the 16K independent locations in x1
mode. In wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be
tied to 0. A_ADDR is synchronized by A_CLK while B_ADDR is synchronized to B_CLK. Two-port mode is in effect
when the width of at least one port is 36, and A_ADDR provides the read address while B_ADDR provides the write
address.
Table 9 • Address Bus Used and Unused Bits
A_ADDR/B_ADDR
Depth x Width
Used Bits
Unused Bits
(must be tied to 0)
16Kx1
[13:0]
None
8Kx2
[13:1]
[0]
4Kx4
[13:2]
[1:0]
2Kx8, 2Kx9
[13:3]
[2:0]
1Kx16, 1Kx18
[13:4]
[3:0]
512x32,
512x36 (Two-port)
[13:5]
[4:0]
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SmartFusion2 and IGLOO2 Macro Library Guide
A_DIN and B_DIN
Table 10 lists the data input buses for the two ports. The required bits are LSB justified and unused MSB bits must be
tied to 0. Two-port mode is in effect when the width of at least one port is 36, and A_DIN provides the MSB of the write
data while B_DIN provides the LSB of the write data.
Table 10 • Data Input Buses Used and Unused Bits
A_DIN/B_DIN
Depth x Width
Used Bits
Unused Bits
(must be tied to 0)
16Kx1
[0]
[17:1]
8Kx2
[1:0]
[17:2]
4Kx4
[3:0]
[17:4]
2Kx8
[7:0]
[17:8]
2Kx9
[8:0]
[17:9]
1Kx16
[16:9] is [15:8]
[7:0] is [7:0]
[17]
[8]
1Kx18
[17:0]
None
512x32
(Two-port write)
A_DIN[16:9] is [31:24]
A_DIN[7:0] is [23:16]
B_DIN[16:9] is [15:8]
B_DIN[7:0] is [7:0]
A_DIN[17]
A_DIN[8]
B_DIN[17]
B_DIN[8]
512x36
(Two-port write)
A_DIN[17:0] is [35:18]
B_DIN[17:0] is [17:0]
None
A_DOUT and B_DOUT
Table 11 lists the data output buses for the two ports. The required bits are LSB justified. Two-port mode is in effect
when the width of at least one port is 36, and A_DOUT provides the MSB of the read data while B_DOUT provides the
LSB of the read data.
Table 11 • Data Output Buses Used and Unused Bits
A_DOUT/B_DOUT
Depth x Width
Used Bits
52
Unused Bits
16Kx1
[0]
[17:1]
8Kx2
[1:0]
[17:2]
4Kx4
[3:0]
[17:4]
2Kx8
[7:0]
[17:8]
2Kx9
[8:0]
[17:9]
1Kx16
[16:9] is [15:8]
[7:0] is [7:0]
[17]
[8]
1Kx18
[17:0]
None
SmartFusion2 and IGLOO2 Macro Library Guide
Table 11 • Data Output Buses Used and Unused Bits
A_DOUT/B_DOUT
Depth x Width
Used Bits
Unused Bits
512x32
(Two-port read)
A_DOUT[16:9] is [31:24]
A_DOUT[7:0] is [23:16]
B_DOUT[16:9] is [15:8]
B_DOUT[7:0] is [7:0]
A_DOUT[17]
A_DOUT[8]
B_DOUT[17]
B_DOUT[8]
512x36
(Two-port read)
A_DOUT[17:0] is [35:18]
B_DOUT[17:0] is [17:0]
None
A_BLK and B_BLK
Table 12 lists the block port select control signals for the two ports. A_BLK is synchronized by A_CLK while B_BLK is
synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is 36, and A_BLK controls the
read operation while B_BLK controls the write operation
Table 12 • Block Port Select
Block Port
Select Signal
Value
Result
Perform read or write operation on Port A. In 36 width mode,
perform a read operation from both ports A and B
A_BLK[2:0]
111
A_BLK[2:0]
No operation in memory from Port A. Port A read data will be forced
Any one bit is 0 to 0. In 36 width mode, the read data from both ports A and B will be
forced to 0.
B_BLK[2:0]
111
B_BLK[2:0]
No operation in memory from Port B. Port B read data will be forced
Any one bit is 0 to 0, unless it is a 36 width mode and write operation to both ports A
and B is gated.
Perform read or write operation on Port B. In 36 width mode,
perform a write operation to both ports A and B.
A_WMODE and B_WMODE
In true dual-port write mode, each port has a feed-through write option:
•
Logic 0 = Read data port holds the previous value.
•
Logic 1 = Feed-through, i.e. write data appears on the corresponding read data port. This setting is invalid when
the width of at least one port is 36 and the two-port mode is in effect.
A_CLK and B_CLK
All signals in ports A and B are synchronous to the corresponding port clock. All address, data, block port select and
write enable inputs must be set up before the rising edge of the clock. The read or write operation begins with the rising
edge. Two-port mode is in effect when the width of at least one port is 36, and A_CLK provides the read clock while
B_CLK provides the write clock.
A_DOUT_LAT and B_DOUT_LAT
A_DOUT_CLK and B_DOUT_CLK
A_DOUT_ARST_N and B_DOUT_ARST_N
A_DOUT_EN and B_DOUT_EN
A_DOUT_SRST_N and B_DOUT_SRST_N
The A_DOUT_LAT and B_DOUT_LAT signals select the pipeline registers for the respective port. Two-port mode is in
effect when the width of at least one port is 36, and the A_DOUT register signals control the MSB of the read data
while the B_DOUT register signals control the LSB of the read data.
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SmartFusion2 and IGLOO2 Macro Library Guide
The pipeline registers have rising edge clock inputs for each port, which must be tied to the respective port clock when
used. When the pipeline registers are not being used, they are forced into latch mode and the clock signals should be
tied to 1, which makes them transparent.
Table 13 describes the functionality of the control signals on the A_DOUT and B_DOUT pipeline registers.
Table 13 • Truth Table for A_DOUT and B_DOUT Registers
_ARST_N
_LAT
_CLK
_EN
_SRST_N
D
0
X
X
X
X
X
0
1
0
Not rising
X
X
X
Qn
1
0

0
X
X
Qn
1
0

1
0
X
0
1
0

1
1
D
D
1
1
0
X
X
X
Qn
1
1
1
0
X
X
Qn
1
1
1
1
0
X
0
1
1
1
1
1
D
D
A_EN and B_EN
These are active low, power down configuration bits for each port. They must be tied to 1.
A_ARST_N and B_ARST_N
Always tie these signals to 1.
SII_LOCK
Control signal, when 1 locks the entire RAM1K18 memory from being accessed by the SII.
BUSY
This output indicates that the RAM1K18 memory is being accessed by the SII.
54
Qn+1
SmartFusion2 and IGLOO2 Macro Library Guide
RAM64x18
The RAM64x18 block contains 1,152 memory bits and is a three-port memory providing one write port and two read
ports. Write operations to the RAM64x18 memory are synchronous. Read operations can be asynchronous or
synchronous for either setting up the address and/or reading out the data. Enabling synchronous operation at the read
address port improves setup timing for the read address and its enable signals. Enabling synchronous operation at the
read data port improves clock-to-out delay. Each data port on the RAM64x18 memory can be independently
configured in any combination shown below.
•
64x18, 64x16
•
128x9, 128x8
•
256x4
•
512x2
•
1Kx1
The main features of the RAM64x18 memory block are as follows
•
There are two independent read data ports A and B, and one write data port C.
•
The write operation is always synchronous. The write address, write data, C block port select and write enable
inputs are registered.
•
For both read data ports, setting up the address can be synchronous or asynchronous.
•
The two read data ports have address registers with a separate enable, synchronous-reset and asynchronousreset for synchronous mode operation, which can also be configured to be transparent latches for
asynchronous mode operation.
•
The two read data ports have output registers with a separate enable, synchronous-reset and asynchronousreset for pipeline mode operation, which can also be configured to be transparent latches for asynchronous
mode operation.
•
Therefore, there are four read operation modes for ports A and B:
–
•
Synchronous read address without pipeline registers (sync-async)
–
Synchronous read address with pipeline registers (sync-sync)
–
Asynchronous read address without pipeline registers (async-async)
–
Asynchronous read address with pipeline registers (async-sync)
Each data port on the RAM64x18 memory can be independently configured in any of the following
combinations: 64x18, 64x16, 128x9, 128x8, 256x4, 512x2, and 1Kx1.
•
The widths of each port can be different, but they need to be multiples of one another.
•
There is an independent clock for each port. The memory will be triggered at the rising edge of the clock.
•
Read from both ports A and B at the same location is allowed.
•
Read and write on the same location at the same time results in unknown data to be read. There is no
collision prevention or detection. However, correct data is expected to be written into the memory.
Figure 59 shows a simplified block diagram of the RAM64x18 memory block and Table 14 gives the port descriptions.
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SmartFusion2 and IGLOO2 Macro Library Guide
The simplified block diagram illustrates the three independent read/write ports and the pipeline registers on the read
port.
Figure 59 • Simplified Block Diagram of RAM64x18
Table 14 • Port List for RAM64x18
Pin Name
Pin
Direction
Type1
Description
Polarity
A_ADDR[9:0]
Input
Dynamic
Port A address
A_BLK[1:0]
Input
Dynamic
Port A block selects
A_WIDTH[2:0]
Input
Static
Port A width/depth mode selection
A_DOUT[17:0]
Output
Dynamic
Port A read data
A_DOUT_ARST_N Input
Dynamic
Port A pipeline register asynchronous reset Low
A_DOUT_CLK
Input
Dynamic
Port A pipeline register clock
Rising
A_DOUT_EN
Input
Dynamic
Port A pipeline register enable
High
A_DOUT_LAT
Input
Static
Port A pipeline register select
Low
A_DOUT_SRST_N Input
Dynamic
Port A pipeline register synchronous reset
Low
A_ADDR_CLK
Input
Dynamic
Port A address register clock
Rising
A_ADDR_EN
Input
Dynamic
Port A address register enable
High
A_ADDR_LAT
Input
Static
Port A address register select
Low
A_ADDR_SRST_N Input
Dynamic
Port A address register synchronous reset
Low
A_ADDR_ARST_N Input
Dynamic
Port A address register asynchronous reset Low
56
High
SmartFusion2 and IGLOO2 Macro Library Guide
Table 14 • Port List for RAM64x18
Pin Name
Pin
Direction
Type1
Description
Polarity
B_ADDR[9:0]
Input
Dynamic
Port B address
B_BLK[1:0]
Input
Dynamic
Port B block selects
B_WIDTH[2:0]
Input
Static
Port B width/depth mode selection
B_DOUT[17:0]
Output
Dynamic
Port B read data
B_DOUT_ARST_N Input
Dynamic
Port B pipeline register asynchronous reset Low
B_DOUT_CLK
Input
Dynamic
Port B pipeline register clock
Rising
B_DOUT_EN
Input
Dynamic
Port B pipeline register enable
High
B_DOUT_LAT
Input
Static
Port B pipeline register select
Low
B_DOUT_SRST_N Input
Dynamic
Port B pipeline register synchronous reset
Low
B_ADDR_CLK
Input
Dynamic
Port B address register clock
Rising
B_ADDR_EN
Input
Dynamic
Port B address register enable
High
B_ADDR_LAT
Input
Static
Port B address register select
Low
B_ADDR_SRST_N Input
Dynamic
Port B address register synchronous reset
Low
B_ADDR_ARST_N Input
Dynamic
Port B address register asynchronous reset Low
C_ADDR[9:0]
Input
Dynamic
Port C address
C_CLK
Input
Dynamic
Port C clock
C_DIN[17:0]
Input
Dynamic
Port C write data
C_WEN
Input
Dynamic
Port C write enable
High
C_BLK[1:0]
Input
Dynamic
Port C block selects
High
C_WIDTH[2:0]
Input
Static
Port C width/depth mode selection
A_EN
Input
Static
Port A power down (must be tied to 1)
Low
B_EN
Input
Static
Port B power down (must be tied to 1)
Low
C_EN
Input
Static
Port C power down (must be tied to 1)
Low
SII_LOCK
Input
Static
Lock access to SII
High
BUSY
Output
Dynamic
Busy signal from SII
High
High
Rising
Note: Static inputs are defined at design time and need to be tied to 0 or 1.
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SmartFusion2 and IGLOO2 Macro Library Guide
Signal Descriptions for RAM64x18
A_WIDTH, B_WIDTH and C_WIDTH
Table 15 lists the width/depth mode selections for each port.
Table 15 • Width/Depth Mode Selection
Depth x Width
1Kx1
000
512x2
001
256x4
010
128x8, 128x9
011
64x16, 64x18
1xx
C_WEN
This is the write enable signal for port C.
58
A_WIDTH/B_WIDTH/C_WIDTH
SmartFusion2 and IGLOO2 Macro Library Guide
A_ADDR, B_ADDR and C_ADDR
Table 16 lists the address buses for each port. 10 bits are required to address 1K independent locations in x1 mode. In
wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be tied to 0.
Table 16 • Address Buses Used and Unused Bits
A_ADDR/B_ADDR/C_ADDR
Depth x
Width
Unused Bits
(must be tied to zero)
Used Bits
1Kx1
[9:0]
None
512x2
[9:1]
[0]
256x4
[9:2]
[1:0]
128x8, 128x9
[9:3]
[2:0]
64x16, 64x18
[9:4]
[3:0]
C_DIN
Table 17 lists the write data input for port C. The required bits are LSB justified and unused MSB bits must be tied to 0.
Table 17 • Data Input Bus Used and Unused Bits
C_DIN
Depth x Width
Used Bits
Unused Bits
(must be tied to 0)
1Kx1
[0]
[17:1]
512x2
[1:0]
[17:2]
256x4
[3:0]
[17:4]
128x8
[7:0]
[17:8]
128x9
[8:0]
[17:9]
64x16
[16:9]
[7:0]
[17]
[8]
64x18
[17:0]
None
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SmartFusion2 and IGLOO2 Macro Library Guide
A_DOUT and B_DOUT
Table 18 lists the read data output buses for ports A and B. The required bits are LSB justified.
Table 18 • Data Output Used and Unused Bits
A_DOUT/B_DOUT
Depth x Width
Used Bits
Unused Bits
1Kx1
[0]
[17:1]
512x2
[1:0]
[17:2]
256x4
[3:0]
[17:4]
128x8
[7:0]
[17:8]
128x9
[8:0]
[17:9]
64x16
[16:9] [7:0]
[17] [8]
64x18
[17:0]
None
A_BLK, B_BLK and C_BLK
Table 19 lists the block port select control signals for the ports.
Table 19 • Block Port Select
Block Port Select
Signal
Value
Result
Any one bit is 0
Port A is not selected and its read data will be forced
to zero.
11
Perform read operation from port A.
Any one bit is 0
Port B is not selected and its read data will be forced
to zero.
11
Perform read operation from port B.
Any one bit is 0
Port C is not selected.
11
Perform write operation to port C.
A_BLK[1:0]
B_BLK[1:0]
C_BLK[1:0]
C_CLK
All signals on port C are synchronous to this clock signal. All write address, write data, C block port select and write
enable inputs must be set up before the rising edge of the clock. The write operation begins with the rising edge.
A_DOUT_LAT, A_ADDR_LAT, B_DOUT_LAT and B_ADDR_LAT
A_DOUT_CLK, A_ADDR_CLK, B_DOUT_CLK and B_ADDR_CLK
A_DOUT_ARST_N, A_ADDR_ARST_N, B_DOUT_ARST_N and B_ADDR_ARST_N
A_DOUT_EN, A_ADDR_EN, B_DOUT_EN and B_ADDR_EN
A_DOUT_SRST_N, A_ADDR_SRST_N, B_DOUT_SRST_N and B_ADDR_SRST_N
The _LAT signals select the registers for the respective port.
The address and pipeline registers have rising edge clock inputs for ports A and B. When both the address and
pipeline registers for a port are in use, their clock signals must be tied together. When the registers are not being used,
they are forced into latch mode and the clock signals should be tied to 1, which makes them transparent.
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SmartFusion2 and IGLOO2 Macro Library Guide
Table 20 describes the functionality of the control signals on the A_ADDR, B_ADDR, A_DOUT and B_DOUT registers.
Table 20 • Truth Table for A_ADDR, B_ADDR, A_DOUT and B_DOUT Registers
_ARST_N
_LAT
_CLK
_EN
_SRST_N
D
Qn+1
0
X
X
X
X
X
0
1
0
Not rising
X
X
X
Qn
1
0

0
X
X
Qn
1
0

1
0
X
0
1
0

1
1
D
D
1
1
0
X
X
X
Qn
1
1
1
0
X
X
Qn
1
1
1
1
0
X
0
1
1
1
1
1
D
D
A_EN, B_EN and C_EN
Active low, power down configuration bits for each port. They must be tied to 1.
SII_LOCK
Control signal, when 1 locks the entire RAM64X18 memory from being accessed by the SII.
BUSY
Output indicates that the RAM64X18 memory is being accessed by the SII.
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SmartFusion2 and IGLOO2 Macro Library Guide
MACC
18 bit x 18 bit multiply-accumulate MACC block
The MACC block can accumulate the current multiplication product with a previous result, a constant, a dynamic value,
or a result from another MACC block. Each MACC block can also be configured to perform a Dot-product operation. All
the signals of the MACC block (except CDIN and CDOUT) have optional registers.
Figure 60 • MACC Ports
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SmartFusion2 and IGLOO2 Macro Library Guide
Table 21 • Ports
Port Name
Direction
Type
Polarity
Dot-product mode.
When DOTP = 1, MACC block performs Dotproduct of two pairs of 9-bit operands.
When DOTP = 0, it is called the normal mode.
DOTP
Input
Static
SIMD
Input
Static
Reserved. Must be 0.
Rising
Dynamic edge
Input clocks.
• CLK[1] is the clock for A[17:9], B[17:9],
C[43:18], P[43:18], OVFL_CARRYOUT,
ARSHFT17, CDSEL, FDBKSEL and SUB
registers.
CLK[1:0]
Input
High
Description
•
CLK[0] is the clock for A[8:0], B[8:0],
C[17:0], CARRYIN and P[17:0].
In normal mode, ensure CLK[1] = CLK[0].
A[17:0]
Input
Dynamic High
Input data A.
Bypass data A registers.
• A_BYPASS[1] is for A[17:9]. Connect to 1,
if not registered.
A_BYPASS[1:0]
Input
Static
High
•
A_BYPASS[0] is for A[8:0]. Connect to 1, if
not registered.
In normal mode, ensure
A_BYPASS[0] = A_BYPASS[1].
Asynchronous reset for data A registers.
• A_ARST_N[1] is for A[17:9]. Connect to 1,
if not registered.
A_ARST_N[1:0]
Input
Dynamic Low
•
A_ARST_N[0] is for A[8:0]. Connect to 1, if
not registered.
In normal mode, ensure
A_ARST_N[1] = A_ARST_N[0].
Synchronous reset for data A registers.
• A_SRST_N[1] is for A[17:9]. Connect to 1,
if not registered.
A_SRST_N[1:0]
Input
Dynamic Low
•
A_SRST_N[0] is for A[8:0]. Connect to 1, if
not registered.
In normal mode, ensure
A_SRST_N[1] = A_SRST_N[0].
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SmartFusion2 and IGLOO2 Macro Library Guide
Table 21 • Ports
Port Name
A_EN[1:0]
Direction
Input
Type
Polarity
Dynamic High
Description
Enable for data A registers.
• A_EN[1] is for A[17:9]. Connect to 1, if not
registered.
•
A_EN[0] is for A[8:0]. Connect to 1, if not
registered.
In normal mode, ensure A_EN[1] = A_EN[0].
B[17:0]
Input
Dynamic High
Input data B.
Bypass data B registers.
• B_BYPASS[1] is for B[17:9]. Connect to 1,
if not registered.
B_BYPASS[1:0]
Input
Static
High
•
B_BYPASS[0] is for B[8:0]. Connect to 1, if
not registered.
In normal mode, ensure
B_BYPASS[0] = B_BYPASS[1].
Asynchronous reset for data B registers.
• B_ARST_N[1] is for B[17:9]. Connect to 1,
if not registered.
B_ARST_N[1:0]
Input
Dynamic Low
•
B_ARST_N[0] is for B[8:0]. Connect to 1, if
not registered.
In normal mode, ensure
B_ARST_N[1] = B_ARST_N[0].
Synchronous reset for data B registers.
• B_SRST_N[1] is for B[17:9]. Connect to 1,
if not registered.
B_SRST_N[1:0]
Input
Dynamic Low
•
B_SRST_N[0] is for B[8:0]. Connect to 1, if
not registered.
In normal mode, ensure
B_SRST_N[1] = B_SRST_N[0].
B_EN[1:0]
Input
Dynamic High
Enable for data B registers.
• B_EN[1] is for B[17:9]. Connect to 1, if not
registered.
•
B_EN[0] is for B[8:0]. Connect to 1, if not
registered.
In normal mode, ensure B_EN[1] = B_EN[0].
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SmartFusion2 and IGLOO2 Macro Library Guide
Table 21 • Ports
Port Name
Direction
Type
Polarity
Description
Result data.
Normal mode
• P = D + (CARRYIN + C) + (A * B), when
SUB = 0
•
P[43:0]
Output
High
P = D + (CARRYIN + C) - (A * B), when
SUB = 1
Dot-product mode
• P = D + (CARRYIN + C) + 512 * ((AL * BH)
+ (AH * BL)), when SUB = 0
•
P = D + (CARRYIN + C) - 512 * ((AL * BH) +
(AH * BL)), when SUB = 1
Notation:
• AL = A[8:0], AH = A[17:9]
•
BL = B[8:0], BH = B[17:9]
Refer to Table 24 on page 70 to see how
operand D is obtained from P, CDIN or 0.
OVFL_CARRYOUT
Output
High
Overflow or CarryOut
• Overflow when OVFL_CARRYOUT_SEL =
0
OVFL_CARRYOUT = (SUM[45] ^
SUM[44]) | (SUM[44] ^ SUM[43])
•
P_BYPASS[1:0]
Input
Static
High
CarryOut when OVFL_CARRYOUT_SEL =
1
OVFL_CARRYOUT = C[43] ^ D[43] ^
SUM[44]
Bypass result P registers.
• P_BYPASS[1] is for P[43:18] and
OVFL_CARRYOUT. Connect to 1, if not
registered.
•
P_BYPASS[0] is for P[17:0]. Connect to 1,
if not registered.
In normal mode, ensure
P_BYPASS[0] = P_BYPASS[1].
P_ARST_N[1:0]
Input
Dynamic Low
Asynchronous reset for result P registers.
• P_ARST_N[1] is for P[43:18] and
OVFL_CARRYOUT. Connect to 1, if not
registered.
•
P_ARST_N[0] is for P[17:0]. Connect to 1,
if not registered.
In normal mode, ensure
P_ARST_N[1] = P_ARST_N[0].
65
SmartFusion2 and IGLOO2 Macro Library Guide
Table 21 • Ports
Port Name
P_SRST_N[1:0]
Direction
Input
Type
Polarity
Dynamic Low
Description
Synchronous reset for result P registers.
• P_SRST_N[1] is for P[43:18] and
OVFL_CARRYOUT. Connect to 1, if not
registered.
•
P_SRST_N[0] is for P[17:0]. Connect to 1,
if not registered.
In normal mode, ensure
P_SRST_N[1] = P_SRST_N[0].
P_EN[1:0]
Input
Dynamic High
Enable for result P registers.
• P_EN[1] is for P[43:18] and
OVFL_CARRYOUT. Connect to 1, if not
registered.
•
P_EN[0] is for P[17:0]. Connect to 1, if not
registered.
In normal mode, ensure P_EN[1] = P_EN[0].
CDOUT[43:0]
Output
Cascade High
Cascade output of result P.
CDOUT is the same as P. The entire bus must
either be dangling or drive an entire CDIN of
another MACC block in cascaded mode.
CARRYIN
Input
Dynamic High
CarryIn for operand C.
C[43:0]
Input
Dynamic High
Routed input for operand C.
In Dot-product mode, connect C[8:0] to the
CARRYIN.
Bypass data C registers.
• C_BYPASS[1] is for C[43:18]. Connect to
1, if not registered.
C_BYPASS[1:0]
Input
Static
High
•
C_BYPASS[0] is for C[17:0] and CARRYIN.
Connect to 1, if not registered.
In normal mode, ensure
C_BYPASS[0] = C_BYPASS[1].
Asynchronous reset for data C registers.
• C_ARST_N[1] is for C[43:18] . Connect to
1, if not registered.
C_ARST_N[1:0]
Input
Dynamic Low
•
C_ARST_N[0] is for C[17:0] and CARRYIN.
Connect to 1, if not registered.
In normal mode, ensure
C_ARST_N[1] = C_ARST_N[0].
66
SmartFusion2 and IGLOO2 Macro Library Guide
Table 21 • Ports
Port Name
Direction
Type
Polarity
Description
Synchronous reset for data C registers.
• C_SRST_N[1] is for C[43:18]. Connect to
1, if not registered.
C_SRST_N[1:0]
Input
Dynamic Low
•
C_SRST_N[0] is for C[17:0] and CARRYIN.
Connect to 1, if not registered.
In normal mode, ensure
C_SRST_N[1] = C_SRST_N[0].
C_EN[1:0]
Input
Dynamic High
Enable for data C registers.
• C_EN[1] is for C[43:18]. Connect to 1, if not
registered.
•
C_EN[0] is for C[17:0] and CARRYIN.
Connect to 1, if not registered.
In normal mode, ensure C_EN[1] = C_EN[0].
CDIN[43:0]
Input
Cascade High
Cascaded input for operand D.
The entire bus must be driven by an entire
CDOUT of another MACC block. In Dotproduct mode the CDOUT must also be
generated by a MACC block in Dot-product
mode.
Refer to Table 24 on page 70 to see how CDIN
is propagated to operand D.
ARSHFT17
Input
ARSHFT17_BYPASS Input
Dynamic High
Arithmetic right-shift for operand D.
When asserted, a 17-bit arithmetic right-shift is
performed on operand D going into the
accumulator.
Refer to Table 24 on page 70 to see how
operand D is obtained from P, CDIN or 0.
Static
Bypass ARSHFT17 register. Connect to 1, if
not registered.
High
ARSHFT17_AL_N
Input
Dynamic Low
Asynchronous load for ARSHFT17 register.
Connect to 1, if not registered.
When asserted, ARSHFT17 register is loaded
with ARSHFT17_AD.
ARSHFT17_AD
Input
Static
Asynchronous load data for ARSHFT17
register.
ARSHFT17_SL_N
Input
Dynamic Low
Synchronous load for ARSHFT17 register.
Connect to 1, if not registered. See Table 22
on page 69.
ARSHFT17_SD_N
Input
Static
Synchronous load data for ARSHFT17
register. See Table 22 on page 69.
ARSHFT17_EN
Input
Dynamic High
High
Low
Enable for ARSHFT17 register. Connect to 1,
if not registered. See Table 22 on page 69.
67
SmartFusion2 and IGLOO2 Macro Library Guide
Table 21 • Ports
Port Name
Direction
Type
Polarity
Description
CDSEL
Input
Dynamic High
Select CDIN for operand D.
When CDSEL = 1, propagate CDIN.
When CDSEL = 0, propagate 0 or P
depending on FDBKSEL.
Refer to Table 22 on page 69 to see how
operand D is obtained from P, CDIN or 0.
CDSEL_BYPASS
Input
Static
Bypass CDSEL register. Connect to 1, if not
registered.
High
CDSEL_AL_N
Input
Dynamic Low
Asynchronous load for CDSEL register.
Connect to 1, if not registered.
When asserted, CDSEL register is loaded with
CDSEL_AD.
CDSEL_AD
Input
Static
High
Asynchronous load data for CDSEL register.
CDSEL_SL_N
Input
Dynamic Low
Synchronous load for CDSEL register.
Connect to 1, if not registered. See Table 22
on page 69.
CDSEL_SD_N
Input
Static
Synchronous load data for CDSEL register.
See Table 22 on page 69.
CDSEL_EN
Input
Dynamic High
Enable for CDSEL register. Connect to 1, if not
registered. See Table 22 on page 69.
Low
FDBKSEL
Input
Dynamic High
Select the feedback from P for operand D.
When FDBKSEL = 1, propagate the current
value of result P register. Ensure
P_BYPASS[1] = 0 and CDSEL = 0.
When FDBKSEL = 0, propagate 0. Ensure
CDSEL = 0.
Refer to Table 24 on page 70 to see how
operand D is obtained from P, CDIN or 0.
FDBKSEL_BYPASS
Input
Static
Bypass FDBKSEL register. Connect to 1, if
not registered.
High
FDBKSEL_AL_N
Input
Dynamic Low
Asynchronous load for FDBKSEL register.
Connect to 1, if not registered.
When asserted, FDBKSEL register is loaded
with FDBKSEL_AD.
FDBKSEL_AD
Input
Static
Asynchronous load data for FDBKSEL
register.
FDBKSEL_SL_N
Input
Dynamic Low
Synchronous load for FDBKSEL register.
Connect to 1, if not registered. See Table 22
on page 69.
FDBKSEL_SD_N
Input
Static
Low
Synchronous load data for FDBKSEL register.
See Table 22 on page 69.
FDBKSEL_EN
Input
Dynamic High
Enable for FDBKSEL register. Connect to 1, if
not registered. See Table 22 on page 69.
68
High
SmartFusion2 and IGLOO2 Macro Library Guide
Table 21 • Ports
Port Name
Direction
Type
Polarity
Description
SUB
Input
Dynamic High
Subtract operation.
SUB_BYPASS
Input
Static
Bypass SUB register. Connect to 1, if not
registered.
High
SUB_AL_N
Input
Dynamic Low
Asynchronous load for SUB register. Connect
to 1, if not registered.
When asserted, SUB register is loaded with
SUB_AD.
SUB_AD
Input
Static
Asynchronous load data for SUB register.
SUB_SL_N
Input
Dynamic Low
Synchronous load for SUB register. Connect
to 1, if not registered. See Table 22.
SUB_SD_N
Input
Static
Synchronous load data for SUB register. See
Table 22.
SUB_EN
Input
Dynamic High
High
Low
Enable for SUB register. Connect to 1, if not
registered. See Table 22.
Table 22 • Truth Table for Control Registers ARSHFT17, CDSEL, FDBKSEL and SUB
_AL_N
_AD
_BYPASS
_CLK
_EN
_SL_N
_SD_N
D
Qn+1
0
AD
X
X
X
X
X
X
AD
1
X
0
Not rising
X
X
X
X
Qn
1
X
0

0
X
X
X
Qn
1
X
0

1
0
SDn
X
!SDn
1
X
0

1
1
X
D
D
1
X
1
X
0
X
X
X
Qn
1
X
1
X
1
0
SDn
X
!SDn
1
X
1
X
1
1
X
D
D
69
SmartFusion2 and IGLOO2 Macro Library Guide
Table 23 • Truth Table - Data Registers A, B, C, CARRYIN, P and OVFL_CARRYOUT
_ARST_N _BYPASS
_CLK
_EN
_SRST_N
Qn+1
0
X
X
X
X
X
0
1
0
Not rising
X
X
X
Qn
1
0

0
X
X
Qn
1
0

1
0
X
0
1
0

1
1
D
D
1
1
X
0
X
X
Qn
1
1
X
1
0
X
0
1
1
X
1
1
D
D
Table 24 • Truth Table - Propagating Data to Operand D
FDBKSEL CDSEL ARSHFT17
70
D
Operand D
0
0
x
44'b0
x
1
0
CDIN[43:0]
x
1
1
{{17{CDIN[43]}},CDIN[43:17]}
1
0
0
P[43:0]
1
0
1
{{17{P[43]}},P[43:17]}
A – Product Support
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This appendix contains information about contacting Microsemi SoC Products Group and using these
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You can browse a variety of technical and non-technical information on the SoC home page, at
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The technical support email address is [email protected]
71
My Cases
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Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
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