AN4836 Application note STEVAL-ISA174V1: VIPer0P 7 W double output non-isolated flyback Introduction The STEVAL-ISA174V1 is a 7 W double output power supply (-5 V/+7 V) set in a non-isolated flyback topology using VIPer0P, STMicroelectronics latest innovative IC for building smart power supplies with energy green management. The evaluation board has the following characteristics: Zero-power input consumption ratified as per IEC62301 Clause 4.5 (PIN_ZPM < 5 mW @ 230 VAC) Five-star energy efficiency when operating under no load (PIN_no_load < 10 mW @ 230 VAC) Compliant with the ErP Lot 6 Tier 2 requirements for household and office equipment in off mode Compliant with the 10% load efficiency and 4-point average active-mode efficiency targets prescribed by the European CoC ver. 5 Tier 2 Meets European regulation 1275/2008 regarding eco-design requirements for standby and offmode electric power consumption for household and office equipment Meets IEC55022 Class B conducted EMI even with reduced EMI filter, thanks to the frequency jittering feature RoHS compliant These targets are achieved because of the following features of the VIPer0P: 800 V avalanche rugged Power MOSFET Embedded HV start-up Zero-Power Mode function Pulse frequency modulation (PFM) and ultra-low standby consumption of the internal circuitry under light load conditions 60 kHz fixed switching frequency with jittering Other VIPer0P features facilitating system design with minimum component counts are: On-board trans-conductance error amplifier internally referenced to 1.2 V ± 2% with separate ground to easily set a negative output Self-biasing option to avoid auxiliary winding and bias components Current mode PWM controller with drain current limit protection for easy compensation Enhanced system reliability is ensured by the built-in soft start function and by the following set of protections: Pulse skip mode to avoid flux-runaway delayed overload protection (OLP) max. duty cycle counter VCC clamp thermal shutdown All protections are auto restart mode, except for pulse-skip mode. April 2016 DocID029032 Rev 1 1/47 www.st.com Contents AN4836 Contents 1 Adapter features ............................................................................. 7 2 Circuit description .......................................................................... 8 3 Schematic and bill of materials ..................................................... 9 3.1 Schematic diagram .......................................................................... 9 3.2 Bill of material................................................................................. 10 4 Transformer .................................................................................. 12 5 Testing the board ......................................................................... 14 6 7 5.1 Efficiency ........................................................................................ 14 5.2 Light load performances ................................................................. 15 5.3 Typical waveforms ......................................................................... 16 ICs features ................................................................................... 18 6.1 Soft start ......................................................................................... 18 6.2 Overload protection ........................................................................ 18 6.3 Pulse skip mode ............................................................................. 19 6.4 VCC clamp protection .................................................................... 21 6.5 Max duty cycle counter protection .................................................. 22 6.6 Overtemperature protection ........................................................... 23 6.7 Zero power mode ........................................................................... 24 Feedback loop calculation guidelines ........................................ 27 7.1 Transfer function ............................................................................ 27 7.2 Compensation procedure ............................................................... 28 8 Thermal measurements ............................................................... 31 9 EMI measurements ....................................................................... 33 10 Immunity tests .............................................................................. 34 10.1 SURGE immunity test (IEC 61000-4-5).......................................... 34 10.2 ESD immunity test (IEC 61000-4-2) ............................................... 36 10.3 Burst immunity test (IEC 61000-4-4) .............................................. 37 10.4 Summary and conclusion ............................................................... 37 11 Board layout ................................................................................. 40 12 Conclusion .................................................................................... 41 2/47 DocID029032 Rev 1 AN4836 Contents 13 Appendix A: Test equipment and measurement of efficiency and low load performance .................................................................... 42 14 References .................................................................................... 45 15 Revision history ........................................................................... 46 DocID029032 Rev 1 3/47 List of tables AN4836 List of tables Table 1: STEVAL-ISA174V1 electrical specification .................................................................................. 7 Table 2: Bill of material ............................................................................................................................. 10 Table 3: Transformer characteristics ........................................................................................................ 12 Table 4: Transformer characteristics ........................................................................................................ 14 Table 5: CoC5 requirement and performance at 10% output load ........................................................... 15 Table 6: CoC5 Energy consumption criteria for no load & evaluation board performances .................... 15 Table 7: Light load performance ............................................................................................................... 15 Table 8: Efficiency @ PIN = 1 W................................................................................................................ 16 Table 9: Classification of the tests ............................................................................................................ 34 Table 10: Common mode surge test results ............................................................................................. 36 Table 11: Differential mode surge test results .......................................................................................... 36 Table 12: ESD contact discharge test results ........................................................................................... 36 Table 13: ESD air discharge test results .................................................................................................. 36 Table 14: Burst test results ....................................................................................................................... 37 Table 15: EMC summary .......................................................................................................................... 39 Table 16: Document revision history ........................................................................................................ 46 4/47 DocID029032 Rev 1 AN4836 List of figures List of figures Figure 1: STEVAL-ISA174V1 top view ....................................................................................................... 7 Figure 2: STEVAL-ISA174V1 bottom view ................................................................................................. 7 Figure 3: STEVAL-ISA174V1 schematic diagram ...................................................................................... 9 Figure 4: VCC waveforms external biasing (diode D3 connected)............................................................. 11 Figure 5: VCC waveforms self-biasing (diode D3 not connected) ............................................................. 11 Figure 6: Transformer: electric and pins diagram (a) ............................................................................... 12 Figure 7: Transformer: electric and pins diagram (b) ............................................................................... 12 Figure 8: Transformer size (bottom view) ................................................................................................. 13 Figure 9: Transformer size (top view) ....................................................................................................... 13 Figure 10: Output load connection of STEVAL-ISA174V1 for board performances evaluation ............... 14 Figure 11: Drain current/voltage @ 115VAC, max load ............................................................................. 16 Figure 12: Drain current/voltage @ 230VAC, max load ............................................................................. 16 Figure 13: Drain current/voltage @ 90VAC, max load ............................................................................... 17 Figure 14: Drain current/voltage @ 265VAC, max load ............................................................................. 17 Figure 15: Soft start .................................................................................................................................. 18 Figure 16: OLP: fault applied during steady state operation; tOVL............................................................. 19 Figure 17: OLP: fault applied during steady state operation; tRESTART ...................................................... 19 Figure 18: OLP: fault maintained; tSS and tOVL .......................................................................................... 19 Figure 19: OLP: fault removed and autorestart ........................................................................................ 19 Figure 20: VIN = 265VAC, D4 and D5 shorted, steady-state ...................................................................... 20 Figure 21: VIN = 265VAC, D4 and D5 shorted, steady-state ...................................................................... 20 Figure 22: VIN = 265VAC, D4 and D5 shorted, zoom ................................................................................. 21 Figure 23: VIN = 265VAC, D4 and D5 shorted, steady-state ...................................................................... 21 Figure 24: VCC clamp protection: tripping.................................................................................................. 22 Figure 25: VCC clamp protection: tripping, autorestart and resume operation after fault removal ............ 22 Figure 26: Shut down by max. duty cycle counter (first tripping and restart) ........................................... 23 Figure 27: Shut down by max. duty cycle counter (steady state) ............................................................. 23 Figure 28: Shut down by max. duty cycle counter (zoom of Figure 27) ................................................... 23 Figure 29: First of the 10 consecutive switching cycles at max. duty cycle (zoom of Figure 28) ............. 23 Figure 30: OTP tripping and steady-state ................................................................................................. 24 Figure 31: Turn on for thermal check during OTP .................................................................................... 24 Figure 32: Entering ZPM ........................................................................................................................... 25 Figure 33: entering ZPM (zoom) ............................................................................................................... 25 Figure 34: Exiting ZPM ............................................................................................................................. 25 Figure 35: Exiting ZPM (zoom) ................................................................................................................. 25 Figure 36: Exiting ZPM: tDEB_ON and pulse skip mode ............................................................................... 26 Figure 37: Exiting ZPM: pulse skip mode ................................................................................................. 26 Figure 38: Control loop block diagram ...................................................................................................... 27 Figure 39: Thermal camera @ VIN = 90VAC, max load, TAMB = 25 °C, VIPer0P side ................................ 31 Figure 40: Thermal camera @ VIN = 90VAC, max load, TAMB = 25 °C, transformer side ........................... 31 Figure 41: Thermal camera @ VIN = 115VAC, max load, TAMB = 25 °C, VIPer0P side .............................. 31 Figure 42: Thermal camera @ VIN = 115VAC, max load, TAMB = 25 °C, transformer side ......................... 31 Figure 43: Thermal camera @ VIN = 230VAC, max load, TAMB = 25 °C, VIPer0P side .............................. 32 Figure 44: Thermal camera @ VIN = 230VAC, max load, TAMB = 25 °C, transformer side ......................... 32 Figure 45: Thermal camera @ VIN = 265VAC, max load, TAMB = 25 °C, VIPer0P side .............................. 32 Figure 46: Thermal camera @ VIN = 265VAC, max load, TAMB = 25 °C, transformer side ......................... 32 Figure 47: Average measurements @ 115 VAC, full load, TAMB = 25 °C ................................................... 33 Figure 48: Average measurements @ 230 VAC, full load, TAMB = 25 °C ................................................... 33 Figure 49: STEVAL-ISA174V1 surge-improved schematic ...................................................................... 35 Figure 50: STEVAL-ISA174V1 filtering to pass EMC tests ...................................................................... 38 Figure 51: Board layout - complete........................................................................................................... 40 Figure 52: Board layout - top layer + top overlay...................................................................................... 40 Figure 53: Board layout - bottom layer + top overlay ............................................................................... 40 DocID029032 Rev 1 5/47 List of figures AN4836 Figure 54: Connections of the UUT to the wattmeter for power measurements ...................................... 43 Figure 55: Switch in position 1 - setting for standby measurements ........................................................ 43 Figure 56: Switch in position 2 - setting for efficiency measurements ...................................................... 44 6/47 DocID029032 Rev 1 AN4836 1 Adapter features Adapter features The electrical specifications of the evaluation board are listed in the following table. Table 1: STEVAL-ISA174V1 electrical specification Parameter Symbol Value Input voltage range VIN [85VAC; 265VAC] Output voltage 1 VOUT1 -5 V Max output current 1 IOUT1 0.84 A Output voltage 2 VOUT2 +7 V Max output current 2 IOUT2 0.4 A Total output power (POUT1+POUT2) POUT_tot 7W Precision of output 1 regulation ΔVOUT1_LF ± 5% High frequency output 1 voltage ripple ΔVOUT1_HF 50 mV Max ambient operating temperature TAMB 60 °C Switching frequency FOSC 60 kHz Figure 1: STEVAL-ISA174V1 top view Figure 2: STEVAL-ISA174V1 bottom view DocID029032 Rev 1 7/47 Circuit description 2 AN4836 Circuit description The power supply is set in non-isolated flyback topology, schematic is given in Figure 3: "STEVAL-ISA174V1 schematic diagram", bill of materials in Table 2: "Bill of material" . The input section includes a resistor R1 for inrush current limiting, a diode D1 and a Pi filter for EMC suppression. The FB pin is the inverting input of an error amplifier and is an accurate 1.2 V voltage reference respect to EAGND. This pin is a separate ground which can float down to -12.5 V with respect to the ground of the device (SGND). This allows the negative output voltage VOUT1 to be set and tightly regulated by simply connecting EAGND to the negative rail and a voltage divider between FB, EAGND and SGND, according to the following formula (with reference to the schematic in Figure 3: "STEVAL-ISA174V1 schematic diagram"): Equation 1 The secondary output VOUT2 is semi-regulated to +7 V by magnetic coupling through the turn ratio of the two output windings. The C-R-C network from COMP (the output of the error amplifier) to SGND pin provides frequency compensation to the feedback loop that regulates the voltage of the main output. PGND, the ground reference of the power section, is connected to SGND with the shortest track and with the lowest impedance, in order to avoid mismatches between the ground references of the signal part and the power part of the IC. At power-up, as VDRAIN exceeds VHVSTART, the internal HV current generator charges the VCC capacitor, C5, to VCCon, the Power MOSFET starts switching, the current generator is turned off and the IC is powered by the energy stored in C5. Generally speaking, the VIPer0P can be self-biased or externally biased. If VCC can fall down to VCSon, the IC biasing is referred to as "self-biasing"; as soon as this happens, the HV source is activated until VCC is recharged to VCCon; this results in a sawtooth VCC shape between VCSon and VCCon (see Figure 5: "VCC waveforms self-biasing (diode D3 not connected)"). The use of self-biasing allows ommitting the transformer auxiliary winding and auxiliary rectifier (only a capacitor across VCC and SGND is needed), at the expense of higher power dissipation and worse standby performance. If VCC is prevented from falling down to VCSon, the IC biasing is referred to as "external biasing". Since the maximum value of VCSon (from the VIPer0P datasheet) is 4.5 V, this is easily obtained by simply connecting the small signal diode D3 from the +7 V output, VOUT2, to VCC (see Figure 4: "VCC waveforms external biasing (diode D3 connected)") . The HV current source is never activated and, thanks to the low consumption of the internal blocks of the VIPer0P and to an adequate design, very low input power consumption in no load condition is reached (less than 10 mW @ 230VAC). Another key feature of the IC is Zero-Power-Mode: an idle state during which the device is totally shut down and the residual consumption from the mains @ 230 V AC is kept below 5 mW. The IC enters ZPM by forcing OFF to SGND for more than 10 ms, and exits ZPM (resuming normal switching) forcing ON to SGND for more than 20 µs. This function can be tested by pressing the tactile switches connected across ON and OFF vs SGND. 8/47 DocID029032 Rev 1 AN4836 Schematic and bill of materials 3 Schematic and bill of materials 3.1 Schematic diagram - 5 V - 800 mA C12 GND 1 2 3 ZERO POWER D2 C17 C7 COMP + 2 IN 1 R1 D6 D1 R4 C1 + R3 L2 L1 C6 6 FB C5 Vcc 5 R5 4 IC1 8 9 7 ON D3 2 TR1 OFF C4 0 C15 10 D5 0 ON 1 7 13 14 15 16 C2 + 1 8 OFF EAGND Drain Drain Drain Drain C3 2 SGND PGND R2 4 1 3 C16 D4 C8 1 C9 L3 2 R6 + C11 + 7V - 400 mA C10 OUT 1 2 3 Figure 3: STEVAL-ISA174V1 schematic diagram GSPG2303161005SG DocID029032 Rev 1 9/47 Schematic and bill of materials 3.2 AN4836 Bill of material Table 2: Bill of material Ref Part number Manufacturer Description Package R1 ROX1SJ10R TE Connectivity 10 Ω 1 W flameproof Ø3 mm - p9 mm R2 ERJ-P08J224V Panasonic 220 kΩ±5% - 0.33 W - 200 V 1206 R3 ERJP03F1002V Panasonic 10 kΩ±1% - 0.2 W 0603 R4 ERJP03F3301V Panasonic 3.3 kΩ ±1% - 0.2 W 0603 R5 ERJP03F8202V Panasonic 82 kΩ ±1% - 0.2 W 0603 C1 UVC2G150MPD Nichicon Elcap 15 µF - 400 V Ø10 mm - p5 mm - h18 mm C2 UVC2G150MPD Nichicon Elcap 15 µF - 400 V Ø10 mm - p5 mm - h18 mm C3 C3216C0G2J102J085AA TDK MLCC capacitor 1 nF - 630 V 1206 C4 GRM1885C1H101JA01D Murata MLCC capacitor 100 pF - 50 V 0603 C5 C2012X5R1E106K125AB TDK MLCC capacitor 10 µF - 25 V 0805 C6 C1608C0G1H102J080AA TDK MLCC capacitor 1 nF - 50 V 0603 C7 06035C153KAT2A AVX MLCC capacitor 15 nF - 50 V 0603 C8 16ZLJ470M8X11.5 Rubycon Elcap 470 µF - 16 V Ø8 mm - p5 mm - h11.5 mm C9 16ZLK470M8X16 Rubycon Elcap 470 µF - 16 V Ø8 mm - p5 mm - h16 mm C10 GRM188C81E105KAADD Murata MLCC capacitor 1 µF - 25 V 0603 C11 16YXF100M6.3X11 Rubycon MLCC capacitor 100 µF - 16 V Ø6.3 mm - p2.5 mm - h11 mm C12 GRM188C81E105KAADD Murata MLCC capacitor 1 µF - 25 V 0603 C15 C0805C221J5GACTU Kemet MLCC capacitor 220 pF 50 V 0603 C16 C0805C221J5GACTU Kemet MLCC capacitor 220 pF 50 V 0603 C17 C0805C221J5GACTU Kemet MLCC capacitor 220 pF 50 V 0603 D1 MRA4007T3G ON Semiconductor 1 A-1000 V Power rectifier diode SMA D2 MRA4007T3G ON Semiconductor 1 A-1000 V Power rectifier diode SMA D3 BAT41ZFILM STMictroelectronics 0.15 A-100 V Signal schottky SOD-123 D4 STPS1L60A STMictroelectronics 1 A-60 V Power schottky SMA D5 STPS2L60A STMictroelectronics 2 A-60 V Power schottky SMA D6 MRA4007T3G ON Semiconductor 1 A-1000 V Power rectifier diode SMA L1 B82144A2105J Epcos 1 mH axial inductor L2 B82144A2105J Epcos 1 mH axial inductor L3 74404042033 Wurth Power induction 3.3 µA (4x4x1.8) mm IC1 VIPer0PL STMicroelectronics Power Switcher SO-16 TF 750314288 Rev0 Wurth Elektronik Flyback transformer E16 R6 10/47 DocID029032 Rev 1 AN4836 Schematic and bill of materials Figure 4: VCC waveforms external biasing (diode D3 connected) Figure 5: VCC waveforms self-biasing (diode D3 not connected) DocID029032 Rev 1 11/47 Transformer 4 AN4836 Transformer The transformer characteristics are listed in the table below. Table 3: Transformer characteristics Parameter Value Test conditions Manufacturer WURTH Part number 750314288 Rev0 Primary inductance (pins 3 - 4) 2.5 mH ±10% Meas. at 10 kHz, 0.1VAC Leakage inductance 42 µH to 84 µH Meas. at 10 kHz, 0.1VAC Primary to sec 1 turn ratio (4 - 2)/(8 - 7) (14.23):(1.00), ±1% Primary to sec 2 turn ratio (4 - 2)/(10 - 9) (10.27):(1.00), ±1% The following images show the transformer electric diagram, size and pin distances (in mm) Figure 6: Transformer: electric and pins diagram (a) 12/47 Figure 7: Transformer: electric and pins diagram (b) DocID029032 Rev 1 AN4836 Transformer Figure 8: Transformer size (bottom view) DocID029032 Rev 1 Figure 9: Transformer size (top view) 13/47 Testing the board AN4836 5 Testing the board 5.1 Efficiency The active mode efficiency is defined as the average of the efficiencies measured at 25%, 50%, 75% and 100% maximum load, at nominal input voltages (VIN = 115 VAC and VIN = 230 VAC ). External power supplies (in a separate housing from the devices they are powering) need to comply with the code of conduct, version 5 "Active mode efficiency" criterion requiring, for a power throughput of 7 W, an active mode efficiency higher than 77% (CoC5 tier1, effective since January 2014) and 80% (CoC5 tier2, starting from January 2016). Another applicable standard is the United States Department of Energy (DOE) recommendation, whose active mode efficiency requirement for the same power throughput is 79.8%. The abovementioned requirements only refer to single output converters, which is not the case for the STEVAL-ISA174V1, which has two outputs. However, just to give an indication of its performance, the measurements were conducted on the equivalent single-output 12 V/7 W converter, simply obtained by connecting the load across the V OUT1 and VOUT2 lines, as shown in the following figure. Figure 10: Output load connection of STEVAL-ISA174V1 for board performances evaluation D3 D4 +7V + C8 R6 C10 OUT = 12V/0.58A GND C9 D5 C11 C12 L3 -5V GSPG0504160955SG From the following table, the equivalent single-output SMPS is code of conduct 5 (Tier1 and Tier2) and DOE compliant, despite its efficiency being adversely affected by the double voltage drop across D4 and D5. In a true 12 V/7 W SMPS (with a single secondary rectifier) it is reasonable to expect 3-4% higher efficiency values. Table 4: Transformer characteristics Active mode efficiency CoC5 requirements (POUT = 7 W) 14/47 Tier 1 Tier 2 77% 80% DOE requirement (POUT = 7 W) 79.80% DocID029032 Rev 1 Board performance VIN= 115VAC 81.60% VIN= 230VAC 81.50% AN4836 5.2 Testing the board Light load performances CoC5 also has efficiency requirements when the output load is 10% of the nominal output power. The equivalent single-output SMPS is compliant with both Tier 1 and Tier2 requirements, as shown in the following table. Table 5: CoC5 requirement and performance at 10% output load Minimum efficiency requirement at 10% of full load VIN Board performance 115 VAC 78.01% 230 VAC 71.40% CoC5 requirements for POUT = 7 W Tier 1 Tier 2 66.7% 70.0% In version 5 of the code of conduct, the power consumption of the power supply when it is not loaded is also considered. The compliance criteria for EPS converters with nominal output power below 49 W and the no-load input power consumption measurements of the evaluation board at nominal input voltages (115 VAC and 230 VAC), are given in the following table. The performance results are well above both Tier 1 and Tier 2 requirements. In the same table the consumption in Zero Power Mode (ZPM) is also given (see Section 6.7: "Zero power mode"). Table 6: CoC5 Energy consumption criteria for no load & evaluation board performances Max PIN req. in no load (0.3 W < Pno < 49 W) Tier 1 Tier 2 150 mW 75 mW Evaluation board PIN consumption No load ZPM VIN = 115VAC 6.5 mW 0.8 mW VIN = 230VAC 9.1 mW 3.5 mW Depending on the equipment being powered, there may be several criteria for measuring converter performance. In particular, one requirement for light load performance (EuP lot 6) is that the input power should be less than 500 mW when the converter is loaded with 250 mW. The evaluation board can satisfy this requirement, as it can be seen from following table, where the efficiencies measured under other light load conditions, P OUT = 25 mW and POUT = 50 mW, are also provided. Table 7: Light load performance VIN [VAC] eff [%] @ POUT = 25 mW @ POUT = 50 mW @ POUT = 250 mW 115 55.6 60.8 72.2 230 51.3 57.0 66.3 Another criterion is the measurement of the output power (or the efficiency) when the input power is equal to one watt (see following table). DocID029032 Rev 1 15/47 Testing the board AN4836 Table 8: Efficiency @ PIN = 1 W 5.3 VIN [VAC] eff @ PIN = 1 W[%] 115 78.3 230 71.1 Typical waveforms Drain voltage and current waveforms under full load conditions for the two nominal input voltages are reported in Figure 11: "Drain current/voltage @ 115VAC, max load " and Figure 12: "Drain current/voltage @ 230VAC, max load ", and for minimum and maximum input voltage in Figure 13: "Drain current/voltage @ 90VAC, max load " and Figure 14: "Drain current/voltage @ 265VAC, max load " respectively. Figure 11: Drain current/voltage @ 115VAC, max load 16/47 Figure 12: Drain current/voltage @ 230VAC, max load DocID029032 Rev 1 AN4836 Testing the board Figure 13: Drain current/voltage @ 90VAC, max load Figure 14: Drain current/voltage @ 265VAC, max load DocID029032 Rev 1 17/47 ICs features 6 ICs features 6.1 Soft start AN4836 An internal soft-start function progressively increases the cycle-by-cycle current limitation point from zero up to IDLIM in eight 50 mA steps. In this way, the drain current is limited during the output voltage increase, thus reducing the stress on the secondary diode. The soft-start time tSS (the time needed for the current limitation point to reach its final value) is internally fixed at 8 ms. This function is activated at any converter startup attempt and after a fault event. The soft start phase is shown in the following figure. Figure 15: Soft start 6.2 Overload protection In case of overload or short circuit, the drain current value reaches I DLIM. For every cycle where this condition is met, an internal OCP counter is incremented; if the overload continues for the time tOVL (50 ms typical, internally fixed), the protection is triggered (Figure 16: "OLP: fault applied during steady state operation; tOVL"); the power section is turned off and the converter is disabled for a tRESTART time (1 s typical). After this time has elapsed, the IC resumes switching and, if the fault is still present, the protection persists indefinitely in the same way (Figure 17: "OLP: fault applied during steady state operation; tRESTART"). This ensures restart attempts of the converter at a low repetition rate so that it works safely with extremely low power throughput and avoids IC overheating due to repeated overload events. Furthermore, for any startup following a triggered protection, the internal soft start-up function is invoked (Figure 18: "OLP: fault maintained; tSS and tOVL") to reduce the stress on the secondary diode. After the fault removal, the IC resumes working normally. If the fault is removed during tSS or tOVL (before the protection is triggered), the counter counts on a cycle-by-cycle basis down to zero and the protection is not tripped. If the short circuit is removed during tRESTART, the IC still waits for tRESTART to elapse before resuming switching (Figure 19: "OLP: fault removed and autorestart"). 18/47 DocID029032 Rev 1 AN4836 ICs features Figure 16: OLP: fault applied during steady state operation; tOVL Figure 17: OLP: fault applied during steady state operation; tRESTART Figure 18: OLP: fault maintained; tSS and tOVL Figure 19: OLP: fault removed and autorestart 6.3 Pulse skip mode Any time the drain peak current, IDRAIN, exceeds IDLIM within the minimum on-time tON_MIN, one switching cycle is skipped. The check is made on a cycle-by-cycle basis, and the cycles can be skipped down to the minimum switching frequency F OSC_MIN (15 kHz, typ). If the above condition persists indefinitely, when the internal OCP counter reaches its end-ofcount, the IC is stopped for tRESTART (1 s, typical) and activated again, with a soft-start phase. Whenever IDRAIN does not exceed IDLIM within tON_MIN, one switching cycle is restored. The check is made on a cycle-by-cycle basis, and the cycles can be restored until reaching the nominal switching frequency, FOSC. DocID029032 Rev 1 19/47 ICs features AN4836 Providing, when needed, an inductor discharge time longer than what would be allowed at nominal switching frequency, the protection helps limit the so called "flux runaway" effect, often present at converter startup when the primary MOSFET, charged during the minimum on-time through the input voltage, cannot discharge the same amount during the off-time because the output voltage is very low. The result is a net increase of average inductor current, that can reach dangerously high values where the output capacitor is not charged enough to ensure the inductor discharge rate needed for the volt-second balance. In order to test this protection, the secondary diodes D4 and D5 were shorted while the converter was operated at 265VAC. In Figure 20: "VIN = 265VAC, D4 and D5 shorted, steady-state" and Figure 21: "VIN = 265VAC, D4 and D5 shorted, steady-state", the first part of the protection intervention is captured. In figure Figure 21: "VIN = 265VAC, D4 and D5 shorted, steady-state": IDLIM is exceeded in the first cycle so the next one is skipped, resulting in a 30 kHz switching frequency IDLIM is exceeded again and the switching frequency is further halved to 15 kHz IDLIM is exceeded again and the switching frequency is kept at 15 kHz indefinitely. Figure 20: VIN = 265VAC, D4 and D5 shorted, steadystate Figure 21: VIN = 265VAC, D4 and D5 shorted, steadystate A magnification of one of the switching cycles of Figure 21: "VIN = 265VAC, D4 and D5 shorted, steady-state" shows the DRAIN current rising very quickly so as to exceed I DLIM within tON_MIN (Figure 22: "VIN = 265VAC, D4 and D5 shorted, zoom"). The converter will operate indefinitely at 15 kHz and the OCP internal counter will increment at every switching cycle. As it is designed to reach its end of count (defining t OVL) after 50 ms at 60 kHz operation, the overload time will be incremented to 200 ms, as shown in Figure 23: "VIN = 265VAC, D4 and D5 shorted, steady-state". 20/47 DocID029032 Rev 1 AN4836 ICs features Figure 22: VIN = 265VAC, D4 and D5 shorted, zoom 6.4 Figure 23: VIN = 265VAC, D4 and D5 shorted, steady-state VCC clamp protection VCC clamp protection can be used as an overvoltage protection of sorts. In fact, if the IC is supplied by a diode from the output voltage (or by auxiliary winding as well), an output overvoltage will produce a VCC increase. If VCC reaches the clamp voltage VCCclamp (30 V min. with respect to EAGND), the current ICC injected into the pin is monitored and, if it exceeds the internal threshold Iclamp_max (30mA, typ.) for more than tclamp_max (5 ms, typ.), the IC is stopped for tRESTART (1 s, typ.) and then activated again with soft-start phase until the fault is removed. During tRESTART, VCC is maintained between the VCSon and VCCon levels by the HV current source periodical activation. If the fault is removed during t RESTART, the IC has to wait for tRESTART to elapse before resume switching. The protection is disabled during the soft start time. In this evaluation board, the output overvoltage and consequent protection activation was produced by shorting R4 to EAGND. The resulting operation is shown in Figure 24: "VCC clamp protection: tripping" and Figure 25: "VCC clamp protection: tripping, autorestart and resume operation after fault removal ". DocID029032 Rev 1 21/47 ICs features AN4836 Figure 24: VCC clamp protection: tripping 6.5 Figure 25: VCC clamp protection: tripping, autorestart and resume operation after fault removal Max duty cycle counter protection The IC embeds a max. duty-cycle counter, which disables the PWM if the MOSFET is turned off by maximum duty cycle (70% min., 80% max.) for ten consecutive switching cycles. Following protection tripping, the PWM is disabled for t RESTART and reactivated with soft-start phase until the fault condition is removed. In some cases (e.g., breaking of the loop at low input voltage) even if V COMP is saturated high, the OLP cannot be triggered because, at every switching cycle, the PWM is turned off by the max. duty cycle before the DRAIN peak current can reach IDLIM. As a result, the output voltage VOUT may increase uncontrollably and be maintained indefinitely at a value far higher than the nominal one, with the risk of damaging the output capacitor, the output diode and the IC itself, as the 800 V breakdown threshold may be exceeded. The max. duty cycle counter protection prevents this kind of failure. To test this protection, heavy load and low input voltage were selected. The IC is protected in autorestart mode for tRESTART (1 s typ.), then attempts startup with soft-start phase until the fault condition is removed (Figure 26: "Shut down by max. duty cycle counter (first tripping and restart) " and Figure 27: "Shut down by max. duty cycle counter (steady state) "). 22/47 DocID029032 Rev 1 AN4836 ICs features Figure 26: Shut down by max. duty cycle counter (first tripping and restart) Figure 27: Shut down by max. duty cycle counter (steady state) In Figure 28: "Shut down by max. duty cycle counter (zoom of Figure 27) ", the ten cycles causing the protection intervention are highlighted; in Figure 29: "First of the 10 consecutive switching cycles at max. duty cycle (zoom of Figure 28)" the magnification of one of them is shown, with the duty cycle measurement: 11.4 / (11.4 + 4.2) = 73.1%. Figure 28: Shut down by max. duty cycle counter (zoom of Figure 27) 6.6 Figure 29: First of the 10 consecutive switching cycles at max. duty cycle (zoom of Figure 28) Overtemperature protection If the VIPer0P junction temperature rises higher than the internal threshold T SD (160 °C, typ.), the PWM is disabled for tRESTART. Following this, a single switching cycle is performed, during which the temperature sensor embedded in the Power MOSFET section is checked. DocID029032 Rev 1 23/47 ICs features AN4836 If the measured junction temperature is still above T SD, the PWM is kept disabled for tRESTART time (Figure 30: "OTP tripping and steady-state" and Figure 31: "Turn on for thermal check during OTP"). On the evaluation board, overheating was produced after several minutes at low input voltage (60 VDC) and heavy load (12 V / 0.55 A). The IC shuts down when a case temperature of approximately 152 °C is measured (through a thermal camera). As the load is decreased, the converter restarts with the soft start phase when the case temperature reaches about 120 °C. Figure 30: OTP tripping and steady-state 6.7 Figure 31: Turn on for thermal check during OTP Zero power mode The Zero power mode is an idle state of the converter characterized by the following features: no switching activity, and so no voltage nor power available at the output the HV current source charges the VCC voltage at 13 V and does not perform its usual functions all the IC circuits except those needed to exit ZPM are turned off, reducing controller consumption to very low values In ZPM, the power supply can draw less than 5 mW @ 230VAC from the mains, which is regarded as a “zero power consumption” condition. The IC enters ZPM when, by pressing on the relevant tactile switch in Figure 3: "STEVAL-ISA174V1 schematic diagram", the OFF pin is forced to SGND for more than tDEB_OFF (10 ms typ.): switching is stopped, VCC is charged to 13 V (see Figure 32: "Entering ZPM" and Figure 33: "entering ZPM (zoom)"). 24/47 DocID029032 Rev 1 AN4836 ICs features Figure 32: Entering ZPM Figure 33: entering ZPM (zoom) The IC exits ZPM when, by pressing the relevant tactile switch in Figure 3: "STEVALISA174V1 schematic diagram", the ON pin is forced to SGND for more than tDEB_ON (20 μs typ.); the device resumes switching (with soft start phase) and the delivery of power to the output (see Figure 34: "Exiting ZPM" and Figure 35: "Exiting ZPM (zoom)") resumes. At startup, the pulse skip mode may also be invoked (Figure 36: "Exiting ZPM: tDEB_ON and pulse skip mode" and Figure 37: "Exiting ZPM: pulse skip mode"). Figure 34: Exiting ZPM Figure 35: Exiting ZPM (zoom) DocID029032 Rev 1 25/47 ICs features AN4836 Figure 36: Exiting ZPM: tDEB_ON and pulse skip mode Figure 37: Exiting ZPM: pulse skip mode In real appliances such as dishwashers or washing machines, ZPM can be managed by a microcontroller (MCU), supervising the operation of the appliance and entering OFF mode when the end of the working cycle is recognized. Once in this state, the SMPS delivers no voltage at its output terminals (consuming less than 5 mW from the power line at 230 V AC) and waits for a manual restart from the user. If the MCU is rated for a 3.3 V supply voltage and features an ultra-low consumption standby mode, it can be powered during ZPM also using the resistive pull-up available at the ON pin (RON, 41 kΩ typ.). In this case, the MCU shuts the SMPS down by pulling the OFF pin low and wakes it up by pulling the ON pin low. 26/47 DocID029032 Rev 1 AN4836 Feedback loop calculation guidelines 7 Feedback loop calculation guidelines 7.1 Transfer function In the following diagram, the set PWM modulator plus power stage is indicated by G1(f), while C(f) is the controller; i.e., the network which ensures the stability of the system. Figure 38: Control loop block diagram The mathematical expression of the power system G1(f) is: Equation 2 fp is the pole due to the output load and fz the zero due to the ESR of the output capacitor: Equation 3 Equation 4 where COUT_eq, ESR_eq and ROUT_eq are obtained referencing the output capacitance, ESR and output resistance of the unregulated output, VOUT2, to the regulated output, VOUT1, through the turn ratio of the transformer: Equation 5 Equation 6 DocID029032 Rev 1 27/47 Feedback loop calculation guidelines AN4836 Equation 7 The mathematical expression of the compensator C(f) is: Equation 8 where: Equation 9 Equation 10 Equation 11 are to be chosen in order to censure the stability of the overall system. G M is the VIPer0P transconductance, HCOMP = (VCOMPH - VCOMPL)/(IDLIM – IDLIM_PFM) is the slope of the VCOMP vs IDRAIN characteristic. 7.2 Compensation procedure The first step is to choose the pole and zero of the compensator and the crossing frequency: Equation 12 Equation 13 28/47 DocID029032 Rev 1 AN4836 Feedback loop calculation guidelines Equation 14 where x and y are arbitrarily chosen. G1(fcross) can be calculated from equation (2) and, since by definition │C(fcross)*G1(fcross)│= 1, C0 is obtained from equation (8) thus: Equation 15 At this point the bode diagram of G1(f)*C(f) can be plotted to check the phase margin for stability. If the margin is not sufficiently high, alternative values should be chosen for fZc, fPc and fcross and the procedure repeated. Once stability is achieved, the values of the schematic components to implement C(f) are chosen as follows: R3 is set in the range of some ten kohms R4 is calculated from (1) Equation 16 C6 is calculated combining (9), (10) and (11): Equation 17 C7 is obtained from the combination of (10) and (11): Equation 18 DocID029032 Rev 1 29/47 Feedback loop calculation guidelines AN4836 Finally, R5 is derived from (11) Equation 19 After selecting commercial values for R3, R4, C6, C7 and R5, the actual values of C 0, fZc and fPc should be calculated using equations (9), (10) and (11), to obtain C0_act , fZc_act and fPc_act respectively. Substituting these values in equation (8), the actual compensator, C_act(f), is obtained. The Bode diagram of G1(f)*C_act(f) can be plotted to check whether the phase margin for the stability is still ensured. 30/47 DocID029032 Rev 1 AN4836 8 Thermal measurements Thermal measurements A thermal analysis of the board was performed using an IR camera for 90 VAC, 115 VAC, 230 VAC and 265 VAC mains input, under full load condition. The results are shown in the following figures. Figure 39: Thermal camera @ VIN = 90VAC, max load, TAMB = 25 °C, VIPer0P side Figure 40: Thermal camera @ VIN = 90VAC, max load, TAMB = 25 °C, transformer side Figure 41: Thermal camera @ VIN = 115VAC, max load, TAMB = 25 °C, VIPer0P side Figure 42: Thermal camera @ VIN = 115VAC, max load, TAMB = 25 °C, transformer side DocID029032 Rev 1 31/47 Thermal measurements AN4836 Figure 43: Thermal camera @ VIN = 230VAC, max load, TAMB = 25 °C, VIPer0P side Figure 44: Thermal camera @ VIN = 230VAC, max load, TAMB = 25 °C, transformer side Figure 45: Thermal camera @ VIN = 265VAC, max load, TAMB = 25 °C, VIPer0P side Figure 46: Thermal camera @ VIN = 265VAC, max load, TAMB = 25 °C, transformer side 32/47 DocID029032 Rev 1 AN4836 9 EMI measurements EMI measurements A pre-compliance test against the EN55022 (Class B) European normative with average detector was performed using an EMC analyzer and a LISN. The results are shown in the following figures. Figure 47: Average measurements @ 115 VAC, full load, TAMB = 25 °C Figure 48: Average measurements @ 230 VAC, full load, TAMB = 25 °C DocID029032 Rev 1 33/47 Immunity tests 10 AN4836 Immunity tests The board has been submitted to immunity tests according IEC61000 and the results are presented in the following sections. The results are classified according the criterions reported in the standard and listed in the following table: Table 9: Classification of the tests 10.1 A Normal performance B Temporary degradation or loss of function or performance, with automatic return to normal operation C Temporary degradation or loss of function with external intervention to re-cover normal operation D Degradation or loss of function, need substitution of damaged components to recover normal operation SURGE immunity test (IEC 61000-4-5) The surge test conditions are as below: Repetition rate: 1 minute (5 positive and 5 negative surges) Applied to: input lines vs. EARTH – Common Mode Applied to: both input line (L vs. N) – Differential Mode Reference plane connected to Protected Earth according to the normative In order to pass the test, the STEVAL-ISA174V1 schematic has been modified with the additions highlighted in the following figure, consisting of an input filter made up of a 275 VAC varistor and two 2.2 nF Y1 capacitor in series. The common point of the capacitors is the Protected Earth, which during the tests is to be connected to the reference plane, according to the normative recommendation. 34/47 DocID029032 Rev 1 AN4836 Immunity tests -5 V -800 mA D2 R2 C17 C7 COMP 3 + R3 D6 275Vac C0a C0b R1 D1 R4 C1 + L2 L1 C6 6 FB Vcc 5 R5 4 IC1 ON C5 C15 OFF C4 ON 1 7 0 13 14 15 16 + 18 OFF 0 EAGND Drain Drain Drain Drain C3 2 C16 SGND PGND C2 4 1 2 1 2 3 ZERO POWER 7 8 9 TR1 D3 10 D5 D4 C8 1 C9 L3 2 + C11 GND C12 C10 R6 +7 V -400 mA OUT 1 2 3 Figure 49: STEVAL-ISA174V1 surge-improved schematic IN 2 2 1 1 GSPG0604161415SG The input voltage has been set to 230 VAC and the output at 10% of full load, proper operation has been checked through a current probe connected on the output.The test results are listed in the following tables. DocID029032 Rev 1 35/47 Immunity tests AN4836 Table 10: Common mode surge test results Noise injection Surge level Polarity Result Criterion L vs. PE 2 kV Positive PASS A N vs. PE 2 kV Positive PASS A L vs. PE 2 kV Negative PASS A N vs. PE 2 kV Negative PASS A Table 11: Differential mode surge test results Noise injection Surge level Polarity Result Criterion L vs. N 2 kV Positive PASS A L vs. N 2 kV Negative PASS A Performed tests show that the tested board is able to withstand the lightning disturbances applied to input line in Common Mode and Differential Mode for each severity level. 10.2 ESD immunity test (IEC 61000-4-2) The test conditions are as below: Contact discharge and Air discharge methods Discharge circuit: 150 pF / 330 ohm Polarity: positive / negative The setting of Figure 49: "STEVAL-ISA174V1 surge-improved schematic" allows ESD to be passed as well . The key point is the filtering of the sensitive pins ON, OFF and EAGND through 220 pF ceramic capacitors to SGND. The purpose of the input filter (varistor + series of the 2.2 nF Y1 capacitors C0a and C0b) is only to provide the Protected Earth (common point of the capacitors) for the correct coupling of the ESD signal according to the IEC 61000-4-2 normative. The input voltage has been set to 230 VAC and the output at 10% of full load, proper operation has been checked through a current probe connected on the output.The test results are listed in the following tables. Table 12: ESD contact discharge test results Noise injection ESD level Polarity Result Criterion L vs. PE 10 kV Positive PASS A L vs. PE 10 kV Negative PASS A N vs. PE 10 kV Positive PASS A N vs. PE 10 kV Negative PASS A Table 13: ESD air discharge test results 36/47 Noise injection ESD level Polarity Result Criterion Horizontal coupling plane 20 kV Positive PASS A Horizontal coupling plane 20 kV Negative PASS A Vertical coupling plane 20 kV Positive PASS A Vertical coupling plane 20 kV Negative PASS A DocID029032 Rev 1 AN4836 10.3 Immunity tests Burst immunity test (IEC 61000-4-4) The test conditions are as below: Polarity: positive/negative Burst duration: 15 ms ± 20 % at 5 kHz Burst period: 300 ms ± 20 % Duration time: 1 minute Applied to: AC lines through integrated capacitive coupling clamp The tests can be passed with the original setting (Figure 3: "STEVAL-ISA174V1 schematic diagram"), the key point is the filtering of the sensitive pins ON, OFF and EAGND through 220 pF ceramic capacitors to SGND . The input voltage has been set to 230 VAC and the output at 10% of full load, proper operation has been checked through a current probe connected on the output. The test results are listed in the following table. Table 14: Burst test results 10.4 Noise injection Burst level Polarity Result Criterion L / PE 8 kV Positive PASS B N / PE 8 kV Positive PASS B L/N 8 kV Positive PASS B L / PE 8 kV Negative PASS B N / PE 8 kV Negative PASS B L/N 8 kV Negative PASS B Summary and conclusion In the following Figure and Table, the EMC board behavior with the above mentioned filters is summarized. DocID029032 Rev 1 37/47 IN 2 1 275Vac C0b Added VR, C0a and C0b to improve immunity against: - Surge (IEC61000-4-5) - ESD (IEC61000-4-2) Filter 1 2 C0a D6 D1 R4 L2 R3 C1 + L1 C6 C7 C4 COMP FB C5 + R5 6 5 C2 + 3 1 R1 C15 Vcc ON C3 D2 ON 1 7 0 OFF 18 OFF 0 DocID029032 Rev 1 2 C16 R2 EAGND Drain Drain Drain Drain 13 14 15 16 SGND PGND 38/47 C17 4 1 IC1 4 2 7 8 9 10 1 2 3 D5 D4 1 C8 C9 L3 2 Added C15, C16 and C17 to improve immunity against: - Burst (IEC61000-4-4) - ESD (IEC61000-4-2) Filter 2 ZERO POWER TR1 D3 C11 -5 V -800 mA + GND R6 C12 C10 +7 V -400 mA OUT 1 2 3 Immunity tests Figure 50: STEVAL-ISA174V1 filtering to pass EMC tests AN4836 GSPG0104161410SG AN4836 Immunity tests Table 15: EMC summary VIPer0P + Filter 1 + Filter 2 air discharge EN/IEC 61000-4-2 (Applicative ESD) EN/IEC 61000-4-4 (BURST simulation) EN/IEC 61000-4-5 (SURGE simulation) 20 kV contact discharge (1) 10 kV (1) common mode 6 kV (1) 8 kV 10 kV (1) differential mode (2) 6 kV (1) 8 kV (2) common mode differential mode 2 kV (1) 2 kV (1) Notes: (1) criterion A: normal performance. (2) criterion B: temporary degradation or loss of function or performance, with automatic return to normal operation. criterion C: temporary degradation or loss of function, with external intervention to re-cover normal operation. criterion D: degradation or loss of function, substitution of damaged components is needed to recover normal operation. DocID029032 Rev 1 39/47 Board layout 11 AN4836 Board layout Figure 51: Board layout - complete Figure 52: Board layout - top layer + top overlay Figure 53: Board layout - bottom layer + top overlay 40/47 DocID029032 Rev 1 AN4836 12 Conclusion Conclusion The STEVAL-ISA174V1 two-output converter set in flyback non-isolated topology, demonstrates that the VIPer0P facilitates the design of a non-isolated converter compliant with the most stringent energy regulations, with relatively few external components. The STEVAL-ISA174V1 in fact consumes less than 10 mW at 230 VAC mains under no load condition and even less than 5 mW in the special ZPM idle state that can be optionally managed by a microcontroller. The 800 V avalanche rugged Power MOSFET and the embedded protections add reliability to the power converter, making VIPer0P the ideal choice when both robustness and energy saving performance are required. DocID029032 Rev 1 41/47 Appendix A: Test equipment and measurement of efficiency and low load performance 13 AN4836 Appendix A: Test equipment and measurement of efficiency and low load performance The converter input power was measured using a wattmeter. The wattmeter simultaneously measures the converter input current (using its internal ammeter) and voltage (using its internal voltmeter). Being a digital instrument, it samples the current and voltage at 20 kHz frequency (or higher, depending on the instrument) and converts them into digital forms. Digital samples are then multiplied to give the instantaneous measured power. The display provides the average measured power, averaging the instantaneous measured power in a short period of time (1 s typ.). Figure 54: "Connections of the UUT to the wattmeter for power measurements" shows how the wattmeter is connected to the UUT (unit under test) and to the AC source and the wattmeter internal block diagram. An electronic load is connected to the output of the power converter (UUT), allowing the setting and measurement of the converter load current, while the output voltage is measured by a voltmeter. The output power is the product between load current and output voltage. The ratio between the output power, calculated as previously mentioned, and the input power, measured by the wattmeter, represents the converter efficiency. The measurements were taken under different input/output conditions set on the AC source and on the electronic load. Measuring input power notes: With reference to Figure 54: "Connections of the UUT to the wattmeter for power measurements" , the UUT input current causes a voltage drop across the ammeter internal shunt resistance (the ammeter is not ideal so it has an internal resistance higher than zero) and across the cables connecting the wattmeter to the UUT. If the switch of Figure 54: "Connections of the UUT to the wattmeter for power measurements" is in position 1 (see the simplified schematic in Figure 55: "Switch in position 1 - setting for standby measurements") this voltage drop causes an input measured voltage higher than the input voltage at the UUT input which, of course, affects the measured power. The voltage drop is generally negligible if the UUT input current is low (e.g., when we are measuring the input power of UUT under light load condition). In case of high UUT input current, the voltage drop can be significant (compared to the UUT real input voltage); if this is the case, the switch in Figure 54: "Connections of the UUT to the wattmeter for power measurements" can be set to position 2 (see simplified schematic in Figure 56: "Switch in position 2 - setting for efficiency measurements") where the UUT input voltage is measured directly at the UUT input terminal and the input current does not affect the measured input voltage. The voltage across the voltmeter causes a leakage current inside the voltmeter itself (which is not ideal and so doesn’t have an infinite input resistance). If the switch in Figure 54: "Connections of the UUT to the wattmeter for power measurements" is in position 2 the voltmeter leakage current is measured by the ammeter together with the UUT input current, causing a measurement error. The error is negligible when the UUT input current is much higher than the voltmeter leakage. If not, it may be preferable to set the switch in Figure 54: "Connections of the UUT to the wattmeter for power measurements" to position 1. If you are not certain which measurement scheme less affects the result, you can try both and record the lower input power value. As noted in IEC 62301, instantaneous measurements are appropriate when power readings are stable. The UUT should be operated at 100% of the nameplate output current output for at least 30 minutes (warm up period) immediately prior to conducting efficiency measurements. After this warm-up period, the AC input power is monitored for a period of 5 42/47 DocID029032 Rev 1 AN4836 Appendix A: Test equipment and measurement of efficiency and low load performance minutes to assess the stability of the UUT. If the power level does not drift by more than 5% of the maximum observed value, the UUT is considered stable and the measurements can be recorded at the end of the 5 minute period. If the AC input power is not stable over a 5 minute period, the average power or accumulated energy is measured over time for both AC input and DC output. Some wattmeter models allow the integration of the measured input power over a time interval and then measure the energy absorbed by the UUT during the integration time. Dividing by this very integration time gives the calculated average input power. Figure 54: Connections of the UUT to the wattmeter for power measurements Switch 1 WATT METER U.U.T (Unit Under test) Voltmeter AC SOURCE + V Multiplier 2 A X Ammeter INPUT OUTPUT AVG DISPLAY GSPG0504161630SG Figure 55: Switch in position 1 - setting for standby measurements Wattmeter Ammeter AC SOURCE ~ A + V - U.U.T. AC INPUT UUT Voltmeter GSPG0504161635SG DocID029032 Rev 1 43/47 Appendix A: Test equipment and measurement of efficiency and low load performance AN4836 Figure 56: Switch in position 2 - setting for efficiency measurements Wattmeter Ammeter A AC SOURCE + ~ V - U.U.T. AC INPUT UUT Voltmeter GSPG0504161640SG 44/47 DocID029032 Rev 1 AN4836 14 References References 1. 2. 3. 4. VIPER0P – datasheet IEC 61000-4-2 IEC 61000-4-4 IEC 61000-4-5 DocID029032 Rev 1 45/47 Revision history 15 AN4836 Revision history Table 16: Document revision history 46/47 Date Version Changes 15-Apr-2016 1 Initial release. DocID029032 Rev 1 AN4836 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID029032 Rev 1 47/47