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VIPER38
VIPerPlus family: peak power high-voltage converter
Datasheet - production data
• Output overvoltage protection with tight
tolerance and digital noise filter
• Soft-start reduces the stress during startup and
increases IC lifetime
• Automatic restart after a fault condition
• Thermal shutdown increases system reliability
and IC lifetime
Applications
• Auxiliary power supply for consumer and home
equipment
Figure 1. Typical application
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• Power supply for energy meters and data
concentrators
• Adapters
Description
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Features
• 800 V avalanche-rugged power MOSFET
allowing ultra wide range input Vac to be
achieved
• Embedded HV start-up and sense FET
• PWM current-mode controller
• OCP with selectable threshold (IDlim) and 2nd
OCP with higher value (IDMAX) to protect the IC
from transformer saturation or short-circuit of
the secondary diode
The device is a high-voltage converter that
smartly integrates an 800 V rugged power
MOSFET with PWM current-mode control. The
power MOSFET allows a very high input Vac to be
applied, just limited from its breakdown voltage.
This IC is capable of meeting more stringent
energy-saving standards as it has very low
consumption and operates in burst mode under
light load.
The device features an adjustable extra power
timer (EPT) that enables the IC to sustain
overload conditions for a few seconds.
The integrated HV startup, sense FET and
oscillator with jitter allow the advantage of using
minimal components in the application.
The device features high-level protections like
dual-level OCP, output overvoltage, short-circuit,
and thermal shutdown with hysteresis. After the
removal of a fault condition, the IC is
automatically restarted.
• 30 mW no-load consumption at 230 Vac
• Two operating frequencies:
– 60 kHz (L type) or 115 kHz (H type)
• Jittered frequency reduces the EMI
• Extra power timer (EPT) blanks the overload
current for few seconds
July 2015
This is information on a product in full production.
DocID025703 Rev 2
1/31
www.st.com
Contents
VIPER38
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
7.1
Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2
High-voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3
Power-up and soft startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5
Auto-restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.6
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.7
Current mode conversion with adjustable current limit setpoint . . . . . . . . 18
7.8
Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.9
About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.10
Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 20
7.11
Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 23
7.12
Extra power timer (EPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.13
2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1
SDIP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.2
SO16 Narrow package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
Order code
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DocID025703 Rev 2
VIPER38
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Avalanche ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CONT pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SDIP10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO16 narrow mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID025703 Rev 2
3/31
31
List of figures
VIPER38
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
4/31
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Minimum turn-on time test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
OVP threshold test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IDlim vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FOSC vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDRAIN_START vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IDD0 vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IDD1 vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Main FET RDSON vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Main FET VBVDSS vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IDlim vs. RLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Basic flyback application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Full-featured flyback application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IDD current during startup and burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 16
Soft-start: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing diagram: behavior after short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OVP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CONT pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FB pin configuration (option 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FB pin configuration (option 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Burst mode timing diagram, light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EPT timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SDIP10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO16 Narrow package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID025703 Rev 2
VIPER38
1
Block diagram
Block diagram
Figure 2. Block diagram
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Typical power
Table 1. Typical power
230 VAC
Nominal power
85-265 VAC
Adapter(1)
Open frame(2)
Adapter(1)
Open frame(2)
18 W
20 W
13 W
15 W
VIPER38
28 W
(peak)(3)
30 W
(peak)(3)
23 W
(peak)(3)
25 W (peak)(3)
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking.
3. Maximum practical peak power at 50 °C ambient, with adequate heat sinking for 2 sec (max).
DocID025703 Rev 2
5/31
31
Pin settings
3
VIPER38
Pin settings
Figure 3. Connection diagram (top view)
&15
&15
Note:
The copper area for heat dissipation has to be designed under the DRAIN pins.
Table 2. Pin description
SO16N
Name
1, 2
GND
Device ground and source of the power MOSFET.
3
N.C.
Not connected.
4
N.A.
Not available for user. This pin is mechanically connected to the
controller die pad of the frame. In order to improve the noise immunity,
is highly recommended connect it to GND (pin 1-2).
5
VDD
Supply voltage of the control section. This pin also provides the charging
current of the external capacitor during startup.
6
Control pin. The following functions can be selected:
1. current limit setpoint adjustment. The default value (set internally) of the cycleby-cycle current limit can be reduced by connecting an external resistor to ground.
CONT
2. output voltage monitoring. A voltage exceeding the VOVP threshold (see
Table 8: Controller section on page 9) shuts the IC down, reducing device
consumption. This function is strobed and digitally filtered for high noise immunity.
Control input for duty cycle control. The internal current generator provides bias
current for loop regulation. A voltage below the threshold VFBbm activates burstmode operation. A level close to the threshold VFBlin means that we are
approaching the cycle-by-cycle overcurrent setpoint.
7
FB
8
EPT
This pin allows the connection of an external capacitor for extra power
management. If the function is not used, the pin has to be connected to GND.
9...12
N.C.
Not connected.
13...16
6/31
Function
High-voltage drain pin. The built-in high-voltage switched startup bias current is
DRAIN drawn from this pin too. These pins are connected to the metal frame to facilitate
heat dissipation.
DocID025703 Rev 2
VIPER38
4
Electrical characteristics
Electrical characteristics
Table 3. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
VDRAIN Drain-to-source (ground) voltage
800
V
3
A
IDRAIN
Pulse drain current (limited by TJ = 150 °C)
VCONT
Control input pin voltage
-0.3
6
V
VFB
Feedback voltage
-0.3
5.5
V
VEPT
EPT input pin voltage
-0.3
5
V
VDD
Supply voltage (IDD = 25 mA)
-0.3
Self limited
V
IDD
Input current
25
mA
Power dissipation at TA < 60 °C
1.5
W
PTOT
TJ
TSTG
Operating junction temperature range
-40
150
°C
Storage temperature
-55
150
°C
Table 4. Thermal data
Max
Symbol
Parameter
Unit
SDIP10
SO16N
RthJP
Thermal resistance junction pin
(dissipated power = 1 W)
35
35
°C/W
RthJA
Thermal resistance junction-to-ambient
(dissipated power = 1 W)
100
110
°C/W
RthJA
Thermal resistance junction-to-ambient (1)
(dissipated power = 1 W)
85
80
°C/W
1. When mounted on a standard, single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 µm thick).
‘
Table 5. Avalanche ratings
Symbol
Parameter
Test condition
IAS
Avalanche current
Repetitive or non repetitive
(pulse width limited by TJmax)
EAS
Single pulse avalanche
energy(1)
ID = IAS, VDS=100 V
starting TJ = 25°C
Value
Unit
1.15
A
5
mJ
1. Specification assured by design and characterization.
DocID025703 Rev 2
7/31
31
Electrical characteristics
VIPER38
TJ = -25 to 125 °C, VDD= 14 V; unless otherwise specified (adjust VDD above VDDon startup
threshold before setting to 14 V).
Table 6. Power section
Symbol
Parameter
VBVDSS Breakdown voltage
IOFF
RDS(on)
COSS
Test condition
Min Typ Max Unit
IDRAIN = 1 mA, VFB = GND, TJ = 25 °C
800
V
OFF-state drain current
VDRAIN = max rating,VFB = GND, TJ = 25°C
60
µA
Drain-source on-state
resistance
IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 25 °C
4.5
Ω
IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 125 °C
9
Ω
Effective (energy related)
output capacitance
VDRAIN = 0 to 640 V, TJ = 25°C
17
pF
Table 7. Supply section
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
60
80
100
V
-2
-3
-4
mA
-0.4
-0.6
-0.8
mA
23.5
V
Voltage
VDRAIN_START
Drain-source start voltage
VDRAIN = 120 V, VEPT = GND,
IDDch1
Startup charging current
IDDch2
Restart charging current
(after fault)
VDRAIN = 120 V, VEPT = GND,
VDD
Operating voltage range
After turn-on
8.5
VDD clamp voltage
IDD = 20 mA
23.5
VDDclamp
VDDon
VDD startup threshold
VDDoff
VDD undervoltage shutdown
threshold
VDD(RESTART) VDD restart voltage threshold
VFB = GND, VDD = 4 V
VFB = GND, VDD = 4 V
VDRAIN = 120 V, VEPT = GND,
VFB = GND
VDRAIN = 120 V, VEPT = GND,
VFB = GND
V
13
14
15
V
7.5
8
8.5
V
4
4.5
5
V
Current
IDD0
Operating supply current, not
switching
VFB = GND, FOSC = 0 kHz
VEPT = GND, VDD = 10 V
0.7
mA
Operating supply current,
switching
VDRAIN = 120 V, FOSC = 60 kHz
2.5
mA
IDD1
VDRAIN = 120 V,FOSC = 115 kHz
3.5
mA
IDD_FAULT
Operating supply current, with
protection tripping
VDD = 10 V
400
uA
IDD_OFF
Operating supply current with
VDD < VDD_OFF
VDD = 7 V
270
uA
8/31
DocID025703 Rev 2
VIPER38
Electrical characteristics
Table 8. Controller section
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Feed-back pin
VFBolp
Overload shutdown threshold
4.5
4.8
5.2
V
VFBlin
Overload detection threshold
3.2
3.5
3.7
V
VFBbm
Burst mode threshold
Voltage falling
0.54
0.6
0.66
V
VFBbmhys
Burst mode hysteresis
Voltage rising
IFB1
Feedback sourced current
VFB = 0.3 V
IFB2
Feedback current-OLP
delay
VFBlin < VFB < VFBolp
Dynamic resistance
VFB < 3.3 V
RFB(DYN)
HFB
∆VFB / ∆ID
90
-150
-200
mV
-280
-3
uA
uA
14
21
kΩ
0.5
2
V/A
CONT pin
VCONT_l
Low-level clamp voltage
ICONT = -100 µA
VCONT_h
High-level clamp voltage
ICONT = 1 mA
0.4
0.5
0.6
V
5
5.5
6
V
1.07
1.15
1.23
A
7.6
8.5
9.4
ms
220
400
480
ns
Current limitation
IDlim
Max drain current limitation
tSS
Soft-start time
tON_MIN
td
tLEB
ID_BM
VFB = 4 V, ICONT = -10 µA
TJ = 25 °C
Minimum turn-on time
Propagation delay
(1)
20
ns
Leading edge blanking
(1)
380
ns
Peak drain current during burst
mode
VFB = 0.6 V
115
190
265
mA
VIPER38L
54
60
66
kHz
VIPER38H
103
115
127
kHz
Oscillator section
FOSC
FD
VFB = 1 V
VIPER38L
±4
kHz
VIPER38H
±8
kHz
Modulation depth
FM
Modulation frequency
830
DMAX
Maximum duty cycle
70
920
1010
Hz
80
%
Overcurrent protection (2nd OCP)
IDMAX
Second overcurrent threshold
1.7
A
Overvoltage protection
VOVP
tSTROBE
Overvoltage protection threshold
2.7
3
3.3
V
Overvoltage protection strobe time
1.5
2
2.5
µs
DocID025703 Rev 2
9/31
31
Electrical characteristics
VIPER38
Table 8. Controller section (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Extra power management
Drain current limit with EPT
function
IDLIM_EPT
VEPT(STOP)
85%
IDlim
(1)
EPT shutdown threshold
ICONT < -10 µA
VEPT(RESTART) EPT restart threshold
IEPT
A
3.6
4
4.4
V
0.4
0.6
0.8
V
4
5
6
µA
150
160
°C
30
°C
Sink/source current
Thermal shutdown
TSD
THYST
Thermal shutdown temperature
(1)
Thermal shutdown hysteresis
(1)
1. Specification assured by design, characterization and statistical correlation.
Figure 4. Minimum turn-on time test circuit
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Note:
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Adjust VDD above VDDon startup threshold before setting to 14 V.
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5
Typical electrical characteristics
Typical electrical characteristics
Figure 6. IDlim vs. TJ
Figure 7. FOSC vs. TJ
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Figure 8. VDRAIN_START vs. TJ
Figure 9. IDD0 vs. TJ
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Figure 10. IDD1 vs. TJ
Figure 11. Main FET RDSON vs. TJ
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Typical electrical characteristics
VIPER38
Figure 12. Main FET VBVDSS vs. TJ
Figure 13. IDlim vs. RLIM
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Figure 14. Thermal shutdown
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6
Typical circuit
Typical circuit
Figure 15. Basic flyback application
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Figure 16. Full-featured flyback application
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Operation
7
VIPER38
Operation
The device is a high-performance low-voltage PWM controller chip with an 800 V, avalanche
rugged power section.
The controller includes the oscillator with jitter, startup circuit with soft-start, PWM logic,
current limiting circuit with adjustable setpoint, second overcurrent circuit, burst mode
management, extra power timer circuit, UVLO circuit, auto-restart circuit and thermal
protection circuit.
The current limit setpoint is set by the CONT pin. Burst mode operation guarantees high
performance in standby mode and contributes to meeting energy-saving standards.
All the fault protections are built in auto-restart mode with very low repetition rate to prevent
the IC from overheating.
7.1
Power section and gate driver
The power section is implemented with an avalanche-rugged N-channel MOSFET, which
guarantees safe operation within the specified energy rating as well as high dv/dt capability.
The power section has a BVDSS of 800 V min. and a typical RDS(on) of 4.5 Ω at 25 °C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common-mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the power section cannot be turned on
accidentally.
7.2
High-voltage startup generator
The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than the VDRAIN_START threshold, 80 V DC typically.
When the HV current generator is ON, the IDDch1 current (3 mA typical value) is delivered to
the capacitor on the VDD pin. During auto-restart mode after a fault event, the current is
reduced to IDDch2 (0.6 mA, typ) in order to have a slow duty cycle during the restart phase.
7.3
Power-up and soft startup
When the input voltage rises to the device start threshold, VDRAIN_START, the VDD voltage
begins to grow due to the IDDch1 current (see Table 7: Supply section) coming from the
internal high-voltage startup circuit. If the VDD voltage reaches the VDDon threshold, the
power MOSFET starts switching and the HV current generator is turned OFF.
The IC is powered by the energy stored in the capacitor on the VDD pin, CVDD, until the selfsupply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.
The CVDD capacitor must be correctly sized to avoid fast discharge and keep the required
voltage higher than the VDDoff threshold. In fact, an insufficient capacitance value could
terminate the switching operation before the controller receives any energy from the
auxiliary winding.
14/31
DocID025703 Rev 2
VIPER38
Operation
The following formula can be used for the CVDD capacitor calculation:
Equation 1
I DDch1 × t SSaux
C VDD = ----------------------------------------V DDon – V DDoff
The parameter tSSaux is the time needed for the steady state of the auxiliary voltage. This
time represents an estimate of the user’s application according to the output stage
configurations (transformer, output capacitances, etc.).
During the converter startup time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of the startup converter or after a fault.
Figure 17. IDD current during startup and burst mode
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Operation
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Figure 18. Timing diagram: normal power-up and power-down sequences
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Figure 19. Soft-start: timing diagram
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7.4
Operation
Power-down
At converter power-down, the system loses its ability to regulate as soon as the decreasing
input voltage is low enough for the peak current limitation to be reached. The VDD voltage
drops and when it falls below the VDDoff threshold (see Table 7: Supply section) the power
MOSFET is switched OFF, the energy transfers to the IC is interrupted and, consequently,
the VDD voltage decreases (Table 19: Soft-start: timing diagram), the startup sequence is
inhibited and the power-down is completed. This feature is useful as it prevents the
converter from attempting a restart and ensures monotonic output voltage decay during
system power-down.
7.5
Auto-restart
Every time a protection is tripped, the IC is automatically restarted after a duration that
depends on the discharge and recharge of the CVDD capacitor. As shown in Figure 20:
Timing diagram: behavior after short-circuit, after a fault the IC is stopped and,
consequently, the VDD voltage decreases because of the IC's consumption. As soon as the
VDD voltage falls below the threshold VDD(RESTART) and if the DC input voltage is higher
than VDRAIN_START threshold, the internal HV current source is turned ON and it starts to
charge the CVDD capacitor with the current IDDch2 (0.6 mA, typ). As soon as the VDD voltage
reaches the threshold VDD(ON), the IC restarts.
Figure 20. Timing diagram: behavior after short-circuit
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7.6
Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both cases the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115 kHz
version) at 920 Hz (typical) rate, so that the resulting spread-spectrum action distributes the
energy of each harmonic of the switching frequency over a number of side-band harmonics
having the same energy on the whole, but smaller amplitudes.
DocID025703 Rev 2
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Operation
7.7
VIPER38
Current mode conversion with adjustable current limit
setpoint
The device is a current mode converter. The drain current is sensed and converted to
voltage that is applied to the non-inverting pin of the PWM comparator. This voltage is
compared with the one on the feedback pin through a voltage divider on a cycle-by-cycle
basis.
The device has a default current limit value, IDlim, that can be adjusted according to the
electrical specification, by the RLIM resistor connected to the CONT pin.
The CONT pin has a minimum current sunk needed to activate the IDlim adjustment. Without
RLIM or with high RLIM (i.e. 100 kΩ) the current limit is set to the default value (see IDlim,
Table 8: Controller section).
7.8
Overvoltage protection (OVP)
The device has an integrated logic for the monitoring of the output voltage using as an input
signal the voltage VCONT during the OFF time of the power MOSFET. This is the time when
the voltage from the auxiliary winding tracks the output voltage, through the turn ratio.
The CONT pin has to be connected to the auxiliary winding through the diode DOVP and the
resistors ROVP and RLIM as shown in Figure 22: CONT pin configuration. When, during the
OFF time, the voltage VCONT exceeds four consecutive times the reference voltage VOVP
(see Table 8: Controller section), the overvoltage protection will stop the power MOSFET
and the converter enters auto-restart mode.
In order to bypass the noise immediately after the turn-off of the power MOSFET, the
voltage VCONT is sampled inside a short window after the time TSTROBE, see Table 8:
Controller section and the Figure 21: OVP timing diagram. The sampled signal, if higher
than VOVP, triggers the internal OVP digital signal and increments the internal counter. The
same counter is reset every time the signal OVP is not triggered in one oscillator cycle.
Referring to Figure 22: CONT pin configuration, the resistor divider ratio kOVP will be given
by:
Equation 2
V OVP
k OVP = --------------------------------------------------------------------------------------------------N AUX
-------------- ⋅ ( V OUTOVP + VDSEC ) – V DAUX
N SEC
Equation 3
R LIM
k OVP = ---------------------------------R LIM + R OVP
18/31
DocID025703 Rev 2
VIPER38
Operation
Where:
•
VOVP is the OVP threshold (see Table 8: Controller section)
•
VOUT OVP is the converter output voltage value to activate the OVP set by the designer
•
NAUX is the number of the auxiliary winding turns
•
NSEC is the number of the secondary winding turns
•
VDSEC is the secondary diode forward voltage
•
VDAUX is the auxiliary diode forward voltage
•
ROVP together with RLIM constitute the output voltage divider
Then, fixing RLIM according to the desired IDlim, the ROVP can be calculated by:
Equation 4
1 – k OVP
R OVP = R LIM × ----------------------k OVP
The resistor values will be such that the current sourced and sunk by the CONT pin are
within the rated capability of the internal clamp.
Figure 21. OVP timing diagram
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Operation
7.9
VIPER38
About CONT pin
Referring to Figure 22: CONT pin configuration, the CONT pin is used to configure the:
1.
reduction of the OCP setpoint (IDlim)
2.
output overvoltage protection (OVP)
Table 9: CONT pin configurations lists the external components needed to activate one or
more of the CONT pin functions.
Figure 22. CONT pin configuration
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Table 9. CONT pin configurations
Function / component
RLIM
ROVP
DAUX
IDlim reduction
See Figure 13: IDlim vs. RLIM
No
No
OVP
≥ 80 kΩ
See Equation 4
Yes
IDlim reduction and OVP(1)
See Figure 13: IDlim vs. RLIM
See Equation 4
Yes
1. Select RLIM then ROVP.
7.10
Feedback and overload protection (OLP)
The device is a current-mode converter. The feedback pin controls PWM operation as well
as burst mode and activates the overload protection. Figure 23: FB pin configuration (option
1) and Figure 24: FB pin configuration (option 2) show the internal current-mode structure.
With the feedback pin voltage between VFBbm and VFBlin, (see Table 8: Controller section)
the drain current is sensed and converted to voltage that is applied to the non-inverting pin
of the PWM comparator.
This voltage is compared to the voltage on the feedback pin through a voltage divider on a
cycle-by-cycle basis. When these two voltages are equal, the PWM logic orders the switchoff of the power MOSFET. The drain current is always limited to the value of IDlim.
20/31
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VIPER38
Operation
When the feedback pin voltage reaches the threshold VFBlin, an internal current generator
starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the
VFBolp threshold, the converter is turned off and the automatic restart is activated.
During startup, when the output voltage is still low, if the feedback network is not properly
dimensioned, the feedback voltage could rise up to the overload threshold (VFBolp)
generating the switching off of the IC itself. Taking into account that the feedback network
also fixes the loop stability, two options can be considered for this network.
The time from the overload detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp)
must be set by CFB (or CFB1) using the formula:
Equation 5
V FBolp – V FBlin
T OLP – delay = C FB × ---------------------------------------I FB2
In the option 1 shown in Figure 23: FB pin configuration (option 1), the capacitor CFB has a
dual function: guaranteeing the loop compensation and fixing the overload delay time as
calculated in Equation 5.
Owing to the above considerations, the OLP delay time must be long enough to bypass the
initial output voltage transient and check the overload condition only when the output
voltage is in steady state. The output transient time depends on the value of the output
capacitor and on the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
shown in Figure 24: FB pin configuration (option 2).
Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole
is usually used to compensate the high-frequency zero due to the ESR (equivalent series
resistor) of the output capacitance of the flyback converter.
The mathematical expressions of these poles and zero frequency are:
1
f ZFB = ----------------------------------------------2 ⋅ π ⋅ C FB1 ⋅ R FB1
Equation 6
R FB ( DYN ) + R FB1
f PFB = ------------------------------------------------------------------------------2 ⋅ π ⋅ C FB ⋅ ( R FB ( DYN ) ⋅ RFB1 )
Equation 7
fPFB
1
=
1
2 ⋅ π ⋅ C FB 1 ⋅ R FB 1 + R FB ( DYN
(
)
)
The RFB(DYN) is the dynamic resistance seen by the FB pin.
DocID025703 Rev 2
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Operation
VIPER38
The CFB1 capacitor fixes the OLP delay and usually CFB1 results in a much higher value
than CFB. Equation 5 can be still used to calculate the OLP delay, but CFB1 has to be
considered instead of CFB. Using the compensation network shown in option 2, in all cases
the loop stability can be set as well as a sufficient OLP delay.
Figure 23. FB pin configuration (option 1)
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Figure 24. FB pin configuration (option 2)
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7.11
Operation
Burst-mode operation at no load or very light load
When the load decreases, the feedback loop reacts by lowering the feedback pin voltage. If
it falls below the burst mode threshold, VFBbm, the power MOSFET is no longer allowed to
be switched on. After the MOSFET stops, the feedback pin voltage increases and when it
exceeds the level, VFBbm + VFBbmhys, the power MOSFET starts switching again. The burst
mode thresholds are provided in Table 8: Controller section and Figure 25: Burst mode
timing diagram, light load shows this behavior. The system alternates between a period of
time where the power MOSFET is switching to a period of time where the power MOSFET is
not switching. This mode of operation is the burst mode. The advantage of burst mode
operation is an average switching frequency much lower than the normal operation
frequency, up to several hundred hertz, minimizing all frequency-related losses. In order to
prevent audible noise, during burst mode the drain current peak is clamped to the level,
ID_BM, given in Table 8: Controller section.
Figure 25. Burst mode timing diagram, light load
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7.12
Extra power timer (EPT)
The extra power timer feature allows the setting of a blanking time inside which an overload
current can be admitted. The timer is set through a capacitor (CEPT) connected to the EPT
pin. Its duration is in the range of a few seconds and is limited by thermal constraints.
The extra power timer (EPT) is started as soon as the drain current reaches the threshold
IDLIM_EPT (typ. 85% of IDlim) and its duration is defined by the time needed to charge the
capacitor CEPT up to the value VEPT(STOP) (4V, typ). The charging current is IEPT (-5 uA,
typ).
If the EPT starts, the IC sustains the overload and continues to operate normally if the drain
current falls below the threshold IDLIM_EPT (85% of IDlim) before the EPT voltage reaches the
value VEPT(STOP). The capacitor CEPT is discharged through the current IEPT (5 uA, typ) and
the next EPT is inhibited until the EPT voltage is higher than VEPT(RESTART) (0.6 V, typ). If
the EPT starts and the EPT voltage reaches the value VEPT(STOP), the IC stops and it is
automatically restarted. The CVDD capacitor is then discharged down to the value
VDD(RESTART) (4.5 V, typ) and is recharged, through the HV current source, up to the value
VDDon (14 V, typ). Also in this case the capacitor CEPT is discharged through the IEPT
current. See Figure 26: EPT timing diagram and Table 7: Supply section. The EPT pin has
DocID025703 Rev 2
23/31
31
Operation
VIPER38
to be connected to GND if the function is not used.
Figure 26. EPT timing diagram
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7.13
2nd level overcurrent protection and hiccup mode
The device is protected against short-circuit of the secondary rectifier, short-circuit on the
secondary winding or a hard-saturation of the flyback transformer. This type of anomalous
condition is invoked when the drain current exceeds the threshold IDMAX, see Table 8:
Controller section.
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal is tripped. If, in the subsequent switching
cycles, the signal is not tripped, a temporary disturbance is assumed and the protection
logic will be reset in its idle state; otherwise if the IDMAX threshold is exceeded for two
consecutive switching cycles, a real malfunction is assumed and the power MOSFET is
turned OFF.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding, hence the voltage on the CVDD capacitor
decays until the VDD undervoltage threshold (VDDoff), which clears the latch.
The startup HV current generator is still off, until the VDD voltage falls below its restart
voltage, VDD(RESTART). After this condition the CVDD capacitor is charged again by the
IDDch2 current, and the converter switching restarts if VDDon occurs. If the fault condition is
not removed, the device enters auto-restart mode. This behavior results in a low-frequency
intermittent operation (hiccup-mode operation), with very low stress on the power circuit.
24/31
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8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
8.1
SDIP10 package information
Figure 27. SDIP10 package outline
DocID025703 Rev 2
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Package information
VIPER38
Table 10. SDIP10 mechanical data
mm
Dim.
Min.
Typ.
A
5.33
A1
0.38
A2
2.92
4.95
b
0.36
0.56
b2
0.51
1.15
c
0.2
0.36
D
9.02
10.16
E
7.62
8.26
E1
6.1
7.11
E2
7.62
E3
10.92
e
L
26/31
Max.
1.77
2.92
DocID025703 Rev 2
3.81
VIPER38
8.2
Package information
SO16 Narrow package information
Figure 28. SO16 Narrow package outline
DocID025703 Rev 2
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31
Package information
VIPER38
Table 11. SO16 Narrow mechanical data
mm
Dim.
Min.
Typ.
A
1.75
A1
0.1
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
9.8
9.9
10
E
5.8
6
6.2
E1
3.8
3.9
4
e
0.25
1.27
h
0.25
0.5
L
0.4
1.27
k
0
8
ccc
28/31
Max.
0.1
DocID025703 Rev 2
VIPER38
9
Order code
Order code
Table 12. Order code
Order code
Package
Packing
VIPER38LE
SDIP10
VIPER38HE
Tube
VIPER38HD
VIPER38LD
SO16 narrow
VIPER38HDTR
Tape and reel
VIPER38LDTR
DocID025703 Rev 2
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Revision history
10
VIPER38
Revision history
Table 13. Document revision history
Date
Revision
19-Mar-2014
1
Initial release
2
Updated title, features and description in cover page.
Added SO16 narrow package.
Removed Device summary table.
Updated Section 2: Typical power, Section 3: Pin settings,
and Section 7: Operation.
Added Section 8.2: SO16 Narrow package information and
Section 9: Order code .
Minor text changes.
14-Jul-2015
30/31
Changes
DocID025703 Rev 2
VIPER38
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