LC2MOS Quad SPST Switches ADG441/ADG442/ADG444 Data Sheet FUNCTIONAL BLOCK DIAGRAM 44 V supply maximum ratings VSS to VDD analog signal range Low on resistance (<70 Ω) Low ΔRON (9 Ω max) Low RON match (3 Ω max) Low power dissipation Fast switching times tON < 110 ns tOFF < 60 ns Low leakage currents (3 nA max) Low charge injection (6 pC max) Break-before-make switching action Latch-up proof A grade Plug-in upgrade for DG201A/ADG201A, DG202A/ADG202A, DG211/ADG211A Plug-in replacement for DG441/DG442/DG444 APPLICATIONS Audio and video switching Automatic test equipment Precision data acquisition Battery-powered systems Sample-and-hold systems Communication systems S1 IN1 D1 S2 IN2 D1 S2 IN2 ADG441 ADG444 D2 S3 IN3 ADG442 D2 S3 IN3 D3 S4 IN4 D3 S4 IN4 D4 SWITCHES SHOWN FOR A LOGIC 1 INPUT D4 Figure 1. Each switch conducts equally well in both directions when ON and has an input signal range that extends to the power supplies. In the OFF condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is the low charge injection for minimum transients when switching the digital inputs. PRODUCT HIGHLIGHTS 1. GENERAL DESCRIPTION The ADG441, ADG442, and ADG444 are monolithic CMOS devices that comprise of four independently selectable switches. They are designed on an enhanced LC2MOS process that provides low power dissipation yet gives high switching speed and low on resistance. The on resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. High switching speed also makes the parts suitable for video signal switching. CMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments. The ADG441, ADG442, and ADG444 contain four independent SPST switches. Each switch of the ADG441 and ADG444 turns on when a logic low is applied to the appropriate control input. The ADG442 switches are turned on with logic high on the appropriate control input. The ADG441 and ADG444 switches differ in that the ADG444 requires a 5 V logic power supply that is applied to the VL pin. The ADG441 and ADG442 do not have a VL pin, the logic power supply is generated internally by an on-chip voltage generator. Rev. B S1 IN1 05233-001 FEATURES 2. 3. 4. 5. 6. Extended signal range. The ADG441A/ADG442A/ ADG444A are fabricated on an enhanced LC2MOS, trench-isolated process, giving an increased signal range that extends to the supply rails. Low power dissipation. Low RON. Trench isolation guards against latch-up for A grade parts. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Break-before-make switching. This prevents channel shorting when the switches are configured as a multiplexer. Single-supply operation. For applications where the analog signal is unipolar, the ADG441/ADG442/ADG444 can be operated from a single-rail power supply. The parts are fully specified with a single 12 V power supply. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1994–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADG441/ADG442/ADG444 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5 Applications ....................................................................................... 1 ESD Caution...................................................................................5 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 Product Highlights ........................................................................... 1 Test Circuits........................................................................................9 Revision History ............................................................................... 2 Terminology .................................................................................... 11 Specifications..................................................................................... 3 Trench Isolation .............................................................................. 12 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 13 Single Supply ................................................................................. 4 Ordering Guide .......................................................................... 14 REVISION HISTORY 5/14—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 5/05—Rev. 0 to Rev. A Changes to Format ............................................................. Universal Deleted CERDIP Package and T Grade .......................... Universal Changes to Features and Product Highlights ............................... 1 Changes to Test Conditions in Table 2 .......................................... 4 Changes to Figure 11 ........................................................................ 8 Changes to Trench Isolation Section ........................................... 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 4/94–Revision 0: Initial Version Rev. B | Page 2 of 16 Data Sheet ADG441/ADG442/ADG444 SPECIFICATIONS DUAL SUPPLY1 VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range RON +25°C B Version −40°C to +85°C VSS to VDD 40 70 ∆RON RON Match 85 4 9 1 3 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) ±0.01 ±3 Drain OFF Leakage ID (OFF) ±0.5 ±0.01 ±0.5 ±0.08 ±0.5 ±3 Channel ON Leakage ID, IS (ON) tOFF tOPEN Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ADG441/ADG442 ADG444 ISS IL (ADG444 Only) 1 2 V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments VD = ±8.5 V, IS = −10 mA VDD = +13.5 V, VSS = −13.5 V −8.5 V ≤ VD ≤ +8.5 V VD = 0 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON Unit 85 110 45 60 30 1 6 60 100 4 4 16 nA typ VD = ±15.5 V, VS = ∓15.5 V See Figure 15 VD = ±15.5 V, VS = ∓15.5 V See Figure 15 VS = VD = ±15.5 V See Figure 16 ±3 nA max nA typ nA max 2.4 0.8 V min V max ±0.00001 ±0.5 µA typ µA max VIN = VINL or VINH ns typ ns max ns typ ns max ns typ pC typ pC max dB typ dB typ pF typ pF typ pF typ RL = 1 kΩ, CL = 35 pF; VS = ±10 V; see Figure 17 RL = 1 kΩ, CL = 35 pF; VS = ±10 V; see Figure 17 RL = 1 kΩ, CL = 35 pF; VS = 0 V, RS = 0 Ω, CL = 1 nF; VDD = +15 V, VSS = –15 V; see Figure 18 RL = 50 Ω, CL = 5 pF; f = 1 MHz; see Figure 19 RL = 50 Ω, CL = 5 pF; f= 1 MHz; see Figure 20 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +16.5 V, VSS = −16.5 V Digital Inputs = 0 V or 5 V 170 80 80 0.001 1 0.0001 1 0.001 1 nA max nA typ 2.5 2.5 2.5 µA max µA typ µA max µA typ µA max µA typ µA max Temperature range is: B Version: −40°C to +85°C. Guaranteed by design, not subject to production test. Rev. B | Page 3 of 16 VL = 5.5 V ADG441/ADG442/ADG444 Data Sheet SINGLE SUPPLY1 VDD = +12 V ± 10%, VSS = 0 V, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range RON +25°C 0 to VDD 70 110 ∆RON RON Match LEAKAGE CURRENT Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) ±0.01 ±0.5 ±0.01 ±0.5 ±0.08 ±0.5 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF tOPEN Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ADG441/ADG442 ADG444 IL (ADG444 Only) 1 2 B Version −40°C to +85°C 105 150 40 60 50 2 6 60 100 7 10 16 V Ω typ Ω max Ω typ Ω max Ω typ Ω max 130 4 9 1 3 Test Conditions/Comments VD = +3 V, +8 V, IS = −5 mA VDD = 10.8 V 3 V ≤ VD ≤ 8 V VD = +6 V, IS = −5 mA VDD = 13.2 V VD = 12.2 V/1 V, VS = 1 V/12.2 V See Figure 15 VD = 12.2 V/1 V, VS = 1 V/12.2 V See Figure 15 VS = VD = 12.2 V/1 V Figure 16 ±3 nA typ nA max nA typ nA max nA typ nA max 2.4 0.8 V min V max ±0.00001 ±0.5 µA typ µA max VIN = VINL or VINH ns typ ns max ns typ ns max ns typ pC typ pC max dB typ dB typ pF typ pF typ pF typ RL = 1 kΩ, CL = 35 pF VS = 8 V; Figure 17 RL = 1 kΩ, CL = 35 pF VS = 8 V; Figure 17 RL = 1 kΩ, CL = 35 pF VS = 6 V, RS = 0 Ω, CL = 1 nF VDD = 12 V, VSS = 0 V; see Figure 18 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 13.2 V Digital Inputs = 0 V or 5 V ±3 ±3 220 100 80 0.001 1 0.001 1 Unit 2.5 2.5 µA max µA typ µA max µA typ µA max Temperature range is: B Version: −40°C to +85°C. Guaranteed by design, not subject to production test. Rev. B | Page 4 of 16 VL = 5.5 V Data Sheet ADG441/ADG442/ADG444 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog, Digital Inputs Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Lead Temperature, Soldering (10 sec) Plastic Package, Power Dissipation θJA, Thermal Impedance Lead Temperature, Soldering (10 sec) SOIC Package, Power Dissipation θJA, Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating 44 V −0.3 V to +25 V +0.3 V to −25 V −0.3 V to VDD + 0.3 V VSS − 2 V to VDD + 2 V or 30 mA, Whichever Occurs First 30 mA 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Truth Table ADG441/ADG444 IN 0 1 ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 300°C 470 mW 177°C/W 260°C 600 mW 77°C/W 215°C 220°C Rev. B | Page 5 of 16 ADG442 IN 1 0 Switch Condition ON OFF ADG441/ADG442/ADG444 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN1 1 16 IN2 D1 2 15 D2 S1 3 ADG441 ADG442 VSS 4 14 S2 13 VDD GND 5 12 NC TOP VIEW S4 6 (Not to Scale) 11 S3 10 D3 9 05233-002 D4 7 IN4 8 IN3 NC = NO CONNECT Figure 2. ADG441/ADG442 (DIP/SOIC) Table 5. ADG441/ADG442 Pin Function Descriptions Pin No. 1, 8, 9, 16 2, 7, 10, 15 3, 6, 11, 14 4 Mnemonic IN1 to IN4 D1 to D4 S1 to S4 VSS 5 12 13 GND NC VDD Description Logic Control Input. Drain Terminal. May be an input or output. Source Terminal. May be an input or output. Most Negative Power Supply Potential in Dual Supplies. In single-supply applications, it may be connected to ground. Ground (0 V) Reference. No Connect. Most Positive Power Supply Potential. IN1 1 16 IN2 D1 2 15 D2 S1 3 ADG444 14 S2 VSS 4 S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 05233-003 13 VDD TOP VIEW GND 5 (Not to Scale) 12 VL Figure 3. ADG444 (DIP/SOIC) Table 6. ADG444 Pin Function Descriptions Pin No. 1, 8, 9, 16 2, 7, 10, 15 3, 6, 11, 14 4 Mnemonic IN1 to IN4 D1 to D4 S1 to S4 VSS 5 12 13 GND VL VDD Description Logic Control Input. Drain Terminal. May be an input or output. Source Terminal. May be an input or output. Most Negative Power Supply Potential in Dual Supplies. In single-supply applications, it may be connected to ground. Ground (0 V) Reference. Logic Power Supply (5 V). Most Positive Power Supply Potential. Rev. B | Page 6 of 16 Data Sheet ADG441/ADG442/ADG444 TYPICAL PERFORMANCE CHARACTERISTICS 100 0.02 VDD = +5V VSS = –5V TA = 25°C LEAKAGE CURRENT (nA) RON (Ω) 80 VDD = +12V VSS = –12V 60 VDD = +10V VSS = –10V 40 VDD = +15V VSS = –15V TA = 25°C ID (OFF) 0.01 0 ID (ON) IS (OFF) –0.01 –10 –5 0 VD (VS) (V) 5 10 15 –0.02 –15 05233-005 20 –15 Figure 4. RON as a Function of VD (VS): Dual Supply 170 0 VS (VD) (V) 5 10 15 Figure 7. Leakage Currents as a Function of VS (VD) VDD = +15V VSS = –15V TA = 25°C 110 130 100 CROSSTALK 110 VDD = 10V VSS = 0V 90 VDD = 12V VSS = 0V 90 dB 80 70 OFF ISOLATION 70 50 VDD = 15V VSS = 0V 10 0 3 6 9 12 15 VD (VS) (V) 50 1k 100k FREQUENCY (Hz) 1M 10M 12 Figure 8. Crosstalk and Off Isolation vs. Frequency Figure 5. RON as a Function of VD (VS): Single Supply 100 10k 05233-009 60 05233-006 30 05233-010 RON (Ω) –5 120 VDD = 5V VSS = 0V 150 –10 05233-008 VDD = +15V VSS = –15V 120 VDD = +15V VSS = –15V VDD = 12V VSS = 0V 100 80 125°C 125°C RON (Ω) 85°C 25°C 60 85°C 40 40 25°C 20 –15 –10 –5 0 VD (VS) (V) 5 10 15 05233-007 RON (Ω) 80 60 Figure 6. RON as a Function of VD (VS) for Different Temperatures 20 0 2 4 6 VD (VS) (V) 8 10 Figure 9. RON as a Function of VD (VS) for Different Temperatures Rev. B | Page 7 of 16 ADG441/ADG442/ADG444 120 VDD = 12V VSS = 0V TA = 25°C VIN = 8V 0.005 100 ID (ON) tON IS (OFF) t (ns) LEAKAGE CURRENT (nA) 0.010 Data Sheet 0 ID (OFF) –0.005 80 60 2 4 6 VS, VD (V) 8 10 12 40 ±10 Figure 10. Leakage Currents as a Function of VS (VD) 160 30 ±20 VIN = 8V 140 20 120 tON 10 VDD = +15V VSS = –15V t (ns) 0 100 VDD = 12V VSS = 0V –10 80 60 –20 tOFF 40 –30 –12 –9 –6 –3 0 VS (V) 3 6 9 12 15 05233-012 CHARGE INJECTION (pC) ±18 Figure 12. Switching Time vs. Bipolar Supply TA = 25°C –40 –15 ±14 ±16 SUPPLY VOLTAGE (V) Figure 11. Charge Injection vs. Source Voltage 20 8 10 12 14 16 SUPPLY VOLTAGE (V) 18 Figure 13. Switching Time vs. Single Supply Rev. B | Page 8 of 16 20 05233-014 40 ±12 05233-013 0 05233-011 tOFF –0.010 Data Sheet ADG441/ADG442/ADG444 TEST CIRCUITS IDS ID (OFF) VS D ID (ON) S A VD 05233-015 S D VS RON = V1/IDS Figure 14. On Resistance 0.1F +5V VD VDD VL VIN S Figure 16. On Leakage 3V 0.1F 50% 50% 50% 50% ADG441/ADG444 D RL 1k VS VOUT CL 35pF 3V VIN ADG442 IN GND 90% VSS 90% VOUT tON tOFF 05233-018 0.1F –15V Figure 17. Switching Times +15V +5V VDD VL 3V S D VOUT CL 1nF VS IN VIN VOUT VOUT GND VSS QINJ = CL × VOUT 05233-019 RS –15V Figure 18. Charge Injection Rev. B | Page 9 of 16 A VS Figure 15. Off Leakage +15V D 05233-017 S A 05233-016 IS (OFF) V1 ADG441/ADG442/ADG444 +15V +5V VDD VSS S 0.1F 0.1F D VS VS IN VOUT VSS 0.1F –15V VDD VSS 0.1F 50 D VIN1 VIN2 NC RL 50 GND VSS 0.1F 05233-021 VIN +5V S VOUT RL 50 GND +15V –15V CHANNEL-TO-CHANNEL CROSSTALK = 20 × LOG | VS/VOUT | Figure 19. Off Isolation Figure 20. Channel-to-Channel Crosstalk Rev. B | Page 10 of 16 05233-022 0.1F Data Sheet Data Sheet ADG441/ADG442/ADG444 TERMINOLOGY RON Ohmic resistance between D and S. RON Match Difference between the RON of any two channels. IS (OFF) Source leakage current with the switch OFF. ID (OFF) Drain leakage current with the switch OFF. ID, IS (ON) Channel leakage current with the switch ON. VD (VS) Analog voltage on Terminals D, S. CS (OFF) OFF switch source capacitance. CD (OFF) OFF switch drain capacitance. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tOPEN Break-before-make delay when switches are configured as a multiplexer. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an OFF switch. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. CD, CS (ON) ON switch capacitance. Rev. B | Page 11 of 16 ADG441/ADG442/ADG444 Data Sheet TRENCH ISOLATION NMOS PMOS P-WELL N-WELL LOCO In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode becomes forward-biased. A silicon-controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current which, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch. TRENCH BURIED OXIDE LAYER SUBSTRATE (BACK GATE) Figure 21. Trench Isolation Rev. B | Page 12 of 16 05233-004 In the ADG441A, ADG442A, and ADG444A, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. Data Sheet ADG441/ADG442/ADG444 OUTLINE DIMENSIONS 0.775 0.755 0.735 9 16 PIN 1 INDICATOR 0.280 0.250 0.240 1 8 TOP VIEW 0.210 MAX SIDE VIEW 0.325 0.310 0.300 0.195 0.130 0.115 0.015 MIN 0.150 0.130 0.115 0.022 0.018 0.015 0.070 0.045 0.060 0.039 0.055 0.030 0.015 GAUGE PLANE END VIEW SEATING PLANE 0.021 0.016 0.011 0.012 0.010 0.008 0.430 MAX 03-07-2014-D 0.100 BSC COMPLIANT TO JEDEC STANDARDS MS-001-BB Figure 22. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) Figure 23. 16-Lead Standard Small Outline Package [SOIC_N] (R-16) Dimensions shown in millimeters and (inches) Rev. B | Page 13 of 16 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. ADG441/ADG442/ADG444 Data Sheet ORDERING GUIDE Model1, 2 ADG441BNZ ADG441BR ADG441BR-REEL ADG441BRZ ADG441BRZ-REEL ADG441ABCHIPS ADG441ABR-REEL ADG441ABRZ-REEL ADG442BNZ ADG442BRZ ADG442BRZ-REEL ADG444BNZ ADG444BR ADG444BR-REEL ADG444BRZ ADG444BRZ-REEL 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] DIE 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. A = Trench isolated. Rev. B | Page 14 of 16 Package Option N-16 R-16 R-16 R-16 R-16 R-16 R-16 N-16 R-16 R-16 N-16 R-16 R-16 R-16 R-16 Data Sheet ADG441/ADG442/ADG444 NOTES Rev. B | Page 15 of 16 ADG441/ADG442/ADG444 Data Sheet NOTES ©1994–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00396-0-5/14(B) Rev. B | Page 16 of 16