AN-874: Operating the ADG12xx Series of Parts with 5 V Supplies and the Impact on Performance (Rev. 0) PDF

AN-874
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Operating the ADG12xx Series of Parts with ±5 V Supplies
and the Impact on Performance
by Theresa Corrigan
INTRODUCTION
The ADG12xx family of parts can also be operated with ±5 V
supplies. This application note uses the key specifications of the
ADG12xx and explains how these parts perform with the lower
supply voltage. It also shows that advantage can still be taken of
the high performance capacitance and charge injection offered
by these parts even if only ±5 V supply voltages are available in
the application.
Industrial design engineers require analog switches and multiplexers to support faster sampling, increased performance,
lower power dissipation, and a smaller footprint. To meet these
requirements, a range of low capacitance, low leakage, and low
charge injection analog switches and multiplexers are required.
Analog Devices, Inc. iCMOS® process technology has enabled
the introduction of a wide range of high performance switch
and multiplexer solutions. The ADG12xx family of parts offers
the industry’s lowest capacitance, charge injection, and leakage
for high end data acquisition in very small packages. These
parts are fully specified with bipolar ±15 V supplies and +12 V
single-supply operation.
The full list of ADG12xx parts are listed in Table 1. Complete
specifications for each part with ±15 V/+12 V supplies can be
found in the datasheets available from Analog Devices and
should be consulted in conjunction with this application note.
Table 1. Key Specifications for the ADG12xx Series
Part
No.
ADG1201
ADG1202
ADG1221
ADG1222
ADG1223
ADG1211
ADG1212
ADG1213
ADG1219
ADG1236
ADG1233
ADG1234
ADG1204
ADG1208
Function
1 × SPST
1 × SPST
2 × SPST
2 × SPST
2 × SPST
4 × SPST
4 × SPST
4 × SPST
1 × SPDT
2 × SPDT
3 × SPDT
4 × SPDT
4:1 mux
8:1 mux
On Capacitance
(pF)
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.6
3.5
3.5
3.5
3.5
5.5
6
QINJ (pC)
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−1
+0.5
+0.5
−0.7
+0.4
RON (Ω)
120
120
120
120
120
120
120
120
120
120
120
120
120
120
On Leakage
(pA)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
ADG1206
ADG1209
16:1 mux
Differential 4:1 mux
11
3.5
+0.5
+0.4
120
120
80
20
ADG1207
Differential 8:1 mux
7
+0.5
120
80
Rev. 0 | Page 1 of 8
Package
6-Lead SOT-23
6-Lead SOT-23
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
16-Lead TSSOP; 16-Lead, 3 mm × 3 mm LFCSP
16-Lead TSSOP; 16-Lead, 3 mm × 3 mm LFCSP
16-Lead TSSOP; 16-Lead, 3 mm × 3 mm LFCSP
8-Lead SOT-23
16-Lead TSSOP; 12-Lead, 3 mm × 3 mm LFCSP
16-Lead TSSOP; 16-Lead, 4 mm × 4 mm LFCSP
20-Lead TSSOP; 20-Lead, 4 mm × 4 mm LFCSP
14-Lead TSSOP; 12-Lead, 3 mm × 3 mm LFCSP
16-Lead TSSOP; 16-Lead, SOIC; and 16-Lead,
4 mm × 4 mm LFCSP
28-Lead TSSOP; 32-Lead, 5 mm × 5 mm LFCSP
16-Lead TSSOP; 16-Lead, SOIC; and 16-Lead,
4 mm × 4 mm LFCSP
28-Lead TSSOP; 32-Lead, 5 mm × 5 mm LFCSP
AN-874
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Trigger Levels .................................................................................5
±5 V Performance............................................................................. 3
On Resistance ................................................................................5
Capacitance ................................................................................... 3
Leakage ...........................................................................................6
AC Parameters .............................................................................. 3
Timing ............................................................................................6
Charge Injection ........................................................................... 4
Conclusion .....................................................................................6
Rev. 0 | Page 2 of 8
AN-874
±5 V PERFORMANCE
20
The ADG12xx family of switches and multiplexers are designed
on Analog Devices, 33 V, iCMOS process technology for ±16.5 V
maximum operating voltage. Therefore, the performance
parameters are optimized at these higher supply voltages.
18
SOURCE/DRAIN ON
CAPACITANCE (pF)
16
The main performance parameters affected with lower supply
voltages on switches and multiplexers are the on resistance and
timing. If low on resistance is a key performance requirement at
±5 V, then the Analog Devices families of ADG6xx and ADG14xx
should be considered. The remainder of this application note
outlines the level of performance expected at ±5 V on the
ADG12xx series.
14
DRAIN OFF
12
VDD = +5V
VSS = –5V
TA = 25°C
10
8
6
4
0
–5
CAPACITANCE
The iCMOS process technology offers a significant reduction in
parasitic capacitance per unit area. The design of the ADG12xx
family is optimized for capacitance performance; thus, the die
area has been kept to a minimum. This ensures very low parasitic
capacitance because capacitance is largely dependent on the
switch area. Efforts are also made during the layout of the
device to minimize parasitic capacitance.
Capacitance is an important parameter to consider in any
design and, therefore, the following parameters are specified in
the data sheet:
–4
–3
–2
–1
0
06418-001
SOURCE OFF
2
1
2
3
4
5
VBIAS (V)
Figure 1. ADG1206 Capacitance at ±5 V Dual Supply
AC PARAMETERS
The very low parasitic capacitance of these parts ensures that
these parts have excellent bandwidth, off isolation, and crosstalk
performance. Capacitance and, consequently, the ac performance
over frequency is not affected by lower supply voltages. Figure 2
through Figure 4 show the frequency performance of the
ADG1204 part with ±5 V supplies. All measurements are taken
with a 50 Ω, 5 pF output load.
Off Isolation
CS (Off)
The source off capacitance is measured between the source
input and GND when the switch is off or disabled.
CD (Off)
The drain off capacitance is measured between the drain output
and GND when the switch is disabled.
Off isolation is a measure of unwanted signal coupling through
an off switch. Figure 2 shows that the off isolation at 1 MHz is
−85 dB typically with a ±5 V supply on the ADG1204.
0
–10
–20
OFF ISOLATION (dB)
CD, CS (On)
The on switch capacitance is measured between the input or
output and GND. On capacitance is a measure of the source
capacitance, drain capacitance, and the switch capacitance for
an on switch.
CIN
VDD = +5V
VSS = –5V
TA = +25°C
–30
–40
–50
–60
–70
–80
Digital input capacitance is the capacitance measured between
digital input and GND.
The drain on and drain off capacitance is a function of the
number of switch channels connected to it. Therefore, the drain
capacitance for an 8:1 multiplexer is typically half that of a 16:1
multiplexer.
06418-002
Given that capacitance is mainly dependent on the process and
die area, the operating voltage does not have a significant
impact on performance levels. The very low capacitance
featured at ±15 V is maintained when operating the part with
±5 V supplies. Figure 1 shows the capacitance performance of
the ADG1206, 16:1 multiplexer with ±5 V supplies.
–90
–100
–110
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 2. ADG1204 Off Isolation vs. Frequency
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance. Figure 3 shows that the adjacent channel crosstalk
at 1 MHz is −80 dB typically with ±5 V supply on the ADG1204.
Rev. 0 | Page 3 of 8
AN-874
1.5
0
–20
1.0
CHARGE INJECTION (pC)
CROSSTALK (dB)
–30
–40
S1 TO S2
–50
–60
–70
S2 TO S4
–80
–90
0.5
0
–0.5
–1.0
06418-003
–100
–110
–120
10k
VDD = +5V
VSS = –5V
TA = 25°C
100k
1M
10M
FREQUENCY (Hz)
100M
–1.5
–5
1G
06418-005
–10
VDD = +5V
VSS = –5V
TA = +25°C
–4
–3
–2
–1
0
1
2
3
4
5
VS (V)
Figure 3. ADG1204 Crosstalk vs. Frequency
Figure 5. Charge Injection vs. Source Voltage
Bandwidth
Bandwidth is the frequency at which the output is attenuated by
−3 dB. With ±5 V supplies, the ADG1204 −3 dB point is 600 MHz.
The insertion loss deteriorates with lower supply voltage due to
the increase in on resistance performance. Figure 4 shows the
frequency response when the switch is on for the ADG1204.
–10.0
VDD = +5V
VSS = –5V
TA = 25°C
–15.0
–17.5
0.20
–20.0
VDD = +5V
VSS = –5V
MUX (SOURCE TO DRAIN)
TA = 25°C
0.19
0.18
06418-004
–25.0
10k
CHARGE INJECTION (pC)
–22.5
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 4. ADG1204 On Response vs. Frequency
CHARGE INJECTION
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching. It
is caused by stray capacitance associated with the NMOS and
PMOS transistors that make up the analog switch. In switch
applications, charge injection introduces gain error and dc
offset errors thereby impacting the overall system accuracy.
The ADG12xx parts have excellent charge injection performance due to the lower parasitic capacitance on the iCMOS
process and better matching of the NMOS and PMOS transistors.
The ADG1211, ADG1212, ADG1213, ADG1236, ADG1233,
ADG1234, and the ADG1204 charge injection performance is
typically ±1 pC over the full signal with ±5 V power supplies.
See Figure 5 for a typical performance curve.
Rev. 0 | Page 4 of 8
0.17
0.16
0.15
0.14
0.13
0.12
06418-006
ON RESPONSE (dB)
–12.5
The design techniques used for the ADG1208, ADG1209,
ADG1206, and ADG1207 multiplexers mean that the charge
injection performance is virtually flat over the full signal range.
This is achieved by placing a compensation switch on the drain
of the multiplexers. Figure 6 shows the performance of the
ADG1208, ADG1209, ADG1206, and ADG1207 when used as
a multiplexer (source-to-drain) at ±5 V supplies. The charge
injection is typically 0.15 pC and there is minimal variation
over input signal. The demultiplexer (drain-to-source) charge
injection performance is typically that as shown in Figure 5.
This makes these multiplexers ideal in any application that
demands minimized charge injection, for example, in sample-andhold systems.
0.11
0.10
–5
–4
–3
–2
–1
0
1
2
3
4
VS (V)
Figure 6. Source-to-Drain Charge Injection vs. Source Voltage
5
AN-874
450
1.8
400
1.6
350
VDD = +12V
VSS = 0V
300
250
200
VDD = +15V
VSS = –15V
1.0
10
11
12
13
14
15
06418-009
9
100
16
VSUPPLY , |VDD| = |VSS|
15.0
8
12.5
7
10.0
6
7.5
5
5.0
4
–15.0
3
0
06418-007
0.8
150
2.5
DECREASING
1.2
VDD = +5.5V
VSS = –5.5V
–2.5
INCREASING
1.4
TA = 25°C
–5.0
ON RESISTANCE (Ω)
VTRIG
DUAL SUPPLY
–7.5
2.0
–10.0
The input buffer on the ADG12xx parts is powered from GND
and VDD. The ADG12xx parts have 3 V logic-compatible inputs
with VIH = 2 V minimum and VIL = 0.8 V maximum. These levels
are fully guaranteed in the data sheets at ±15 V and +12 V. There is
very little variation in the trigger point with varying supply for
both dual-supply (see Figure 7) and single-supply operation
(see Figure 8).
Supply voltage has a significant impact on the on resistance
performance of a switch. To obtain the lowest possible on
resistance performance from switches and multiplexers, they
should be operated with the maximum allowable operating
voltage. This is ±16.5 V on the ADG12xx parts. Operating the
part with a higher supply voltage also ensures less variation of
input resistance with varying input signal. This dependence of
operating voltage on the on resistance performance is clearly
shown in Figure 9.
–12.5
TRIGGER LEVELS
SOURCE OR DRAIN VOLTAGE (V)
Figure 7. Trigger Level as a Function of Dual-Supply Voltage
Figure 9. On Resistance as a Function of VD (VS) for Different Supply Voltages
2.0
SINGLE SUPPLY
The ADG12xx on resistance performance with ±5 V supplies is
shown in Figure 10. This plot shows the on resistance performance at 5 V supplies and the performance with a 10% tolerance
on these supplies. The same basic switch cells are used in the
design of all the ADG12xx parts, making these on resistance
plots typical of all configurations.
1.8
1.6
VTRIG
INCREASING
1.4
DECREASING
600
1.2
TA = 25°C
500
VDD = +4.5V
VSS = –4.5V
4
5
6
7
8
9
10
11
12
13
14
15
16
VSUPPLY = VDD, VSS = 0V
Figure 8. Trigger Level as a Function of Single-Supply Voltage
ON RESISTANCE
400
VDD = +5.5V
VSS = –5.5V
300
200
100
The on resistance (RON) of a switch is a measure of the resistance
between the input and the output. A signal passing through a
switch suffers an IR drop, where R is a measure of the RON and
I is the current.
The ADG12xx parts are optimized for low capacitance
performance; therefore, the die area is kept to a minimum.
However, when designing low RON switches, the die area is
maximized to ensure low on resistance. Therefore, there is
an obvious direct trade-off between capacitance and on
resistance performance for switches and multiplexers.
VDD = +5V
VSS = –5V
06418-010
3
ON RESISTANCE (Ω)
0.8
06418-008
1.0
0
–6
–4
–2
0
2
SOURCE OR DRAIN VOLTAGE (V)
4
6
Figure 10. On Resistance as a Function of VD (VS)
As demonstrated in Figure 9 and Figure 10, the on resistance
performance of switches and multiplexers is a function of
supply and input signal. The on resistance performance also
varies with temperature. How the on resistance varies with
temperature at ±5 V supplies for the ADG1211, ADG1212, and
Rev. 0 | Page 5 of 8
AN-874
ADG1213 is shown in Figure 11. It is evident that the on
resistance is higher with higher temperature.
700
VDD = +5V
VSS = –5V
TIMING
The following timing parameters are the most commonly
specified in the part data sheets for on switches and multiplexers.
+125°C
600
tON (EN)
+85°C
Delay time between the 50% and 90% points of the digital input
and switch on condition.
RON (Ω)
500
400
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
300
–40°C
200
+25°C
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
06418-011
100
0
–5
–4
–3
–2
–1
0
1
2
3
5
4
SOURCE OR DRAIN VOLTAGE (V)
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures
LEAKAGE
The iCMOS process technology and the design of the ADG12xx
switches and multiplexers offer very low leakage performance.
The leakage is typically around 20 pA.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
TBBM
Break-before-make timing—off time measured between the
80% point of both switches when switching from one address
state to another.
Timing performance is a function of temperature and supply
voltage. Timing is slower with higher temperature and is slower
with lower supply voltages. The Figure 13 shows the timing performance over temperature and supply voltage for the ADG1211,
ADG1212, and ADG1213 quad SPST switches. It is evident that
the typical tON time at ±5 V, 25°C is 225 ns and the typical tOFF
time is 110 ns.
ID, IS (On)
Channel leakage current when the switch is on.
350
300
Figure 12 shows the leakage performance at a ±5 V supply for
the ADG1206 16:1 multiplexer. The on leakage and drain off
leakage are a function of the number of channels connected to
the drain. This result, then, is a multiple of the number of
channels.
400
TIME (ns)
VDD = +5V
VSS = –5V
VBIAS = +4.5V/–4.5V
300
200
150
5V DS tOFF
100
0
–40
100
06418-013
50
200
–20
20
40
60
80
100
120
Figure 13. tON/tOFF Time vs. Temperature at 5 V Dual Supply
–100
CONCLUSION
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) + +
ID, IS (ON) – –
–200
–300
–400
0
TEMPERATURE (°C)
0
0
20
40
06418-012
LEAKAGE (pA)
5V DS tON
250
60
80
100
120
TEMPERATURE (°C)
Figure 12. Leakage Currents as a Function of Temperature, Dual Supply
The ADG12xx family of parts offer the industry’s lowest
capacitance, charge injection, and leakage for high end data
acquisition in very small packages for ±15 V/+12 V systems.
With lower supply voltages, the excellent capacitance, charge
injection and leakage performance is maintained. The disadvantage of using the ADG12xx parts with ±5V supplies is a
significant decrease to the on resistance and timing performance.
Rev. 0 | Page 6 of 8
AN-874
NOTES
Rev. 0 | Page 7 of 8
AN-874
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN06418-0-1/08(0)
Rev. 0 | Page 8 of 8
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