REVISIONS LTR DESCRIPTION DATE APPROVED A Correct the operating temperature range in section 1.3 and the pin out in section 1.2.2. - phn 12-09-20 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 12-04-09 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE CODE IDENT. NO. A REV AMSC N/A DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil TITLE MICROCIRCUIT, DIGITAL, LOW CAPACITANCE, LOW CHARGE INJECTION, ±15 V/+12 V iCMOS QUAD SPST SWITCHES, MONOLITHIC SILICON DWG NO. V62/12617 16236 A PAGE 1 OF 13 5962-V104-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low capacitance, low charge injection, ±15 V/+12 V iCMOS quad SPST switches microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12617 - Drawing number 01 X B Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 ADG1212-EP Circuit function Low capacitance, low charge injection, ±15 V/+12 V iCMOS quad SPST switches 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 16 JEDEC MO-153-AB X Package style Lead thin Shrink Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 2 1.3 Absolute maximum ratings. 1/ VDD to VSS ................................................................................................ VDD to GND ............................................................................................. VSS to GND .............................................................................................. Analog inputs .......................................................................................... Digital inputs ............................................................................................ Peak current, S or D ................................................................................ Continuous current per channel, S or D .................................................. Operating temperature range ................................................................. Storage temperature range ..................................................................... Junction temperature .............................................................................. 16 lead TSSOP, θJA Thermal impedance (4 layer board) ....................... Lead temperature, soldering ................................................................... 35 V -0.3 V to +35 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V 2/ or 30 mA which ever occurs first GND - 0.3 V to VDD + 0.3 V 2/ or 30 mA which ever occurs first 100 mA (pulsed at 1 ms, 10% duty cycles max) 25 mA -55°C to +125°C -65°C to 150°C 150°C 112°C/W As per JEDEC J-STD 020 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 J-STD-020 Registered and Standard Outlines for Semiconductor Devices Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 1/ 2/ – – Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 3 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Truth table. The truth table shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in figure 5. 3.5.6 Off leakage. The off leakage shall be as shown in figure 6. 3.5.7 On leakage. The on leakage shall be as shown in figure 7. 3.5.8 Off Isolation. The Off isolation shall be as shown in figure 8. 3.5.9 Channel-to-channel crosstalk. The channel-to-channel crosstalk shall be as shown in figure 9. 3.5.10 On Resistance. The on resistance shall be as shown in figure 10. 3.5.11 Bandwidth. The bandwidth shall be as shown in figure 11. 3.5.12 THD + Noise. The THD + Noise shall be as shown in figure 12. 3.5.13 Switching times. The switching times shall be as shown in figure 13. 3.5.14 Charge injection. The charge injection shall be as shown in figure 14. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Analog switch Analog signal range On Resistance Conditions 2/ 25°C Min Max Limits -40°C to +85°C -40°C to +125°C Min Max Min Max Unit VDD to VSS RON ∆RON On Resistance match between channel On Resistance flatness RFLAT(ON) VS = ±10 V, IS = -1 mA See Figure 10 VDD = +13.5 V, VSS = -13.5 V 120 TYP VS = ±10 V, IS = -1 mA 2.5 TYP 6 20 TYP 57 190 VS = -5V/0 V/+V; IS = -1 mA 230 260 10 11 72 79 ±0.6 ±1 ±0.6 ±1 ±0.6 ±1 V Ω Leakage currents (VDD = +16.5 V, VSS = -16.5 V) Source off leakage IS(Off) Drain off leakage ID(Off) Channel on leakage ID, IS (On) Digital inputs Input high voltage VINH Input low voltage VINL Input current IINL or IINH Digital input capacitance CIN Dynamic characteristics 3/ tON tOFF Charge injection Off isolation Channel to channel crosstalk Total harmonic distortion + Noise -3 dB bandwidth CS(Off) CD(Off) CD, CS (On) Power requirements VS = ±10 V, VD = ∓10 V See Figure 6 VS = ±10 V, VD = ∓10 V See Figure 6 VS = VD = ±10 V See Figure 7 ±0.02 TYP ±0.1 ±0.02 TYP ±0.1 ±0.02 TYP ±0.1 nA 2.0 0.005 TYP 2.5 TYP RL = 300 Ω, CL = 35 pF, VS = 10 V; See Figure 13 V 0.8 ±0.1 65 TYP RL = 300 Ω, CL = 35 pF, VS = 10 V; See Figure 13 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 14 RL = 50 Ω, CL = 5 pF, f = 1 MHz, See figure 8 RL = 50 Ω, CL = 5 pF, f = 1 MHz, See figure 9 RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz, See figure 12 RL = 50 Ω, CL = 5 pF, See Figure 11 VS = 0 V, f = 1 MHz µA pF ns 80 80 TYP 95 110 100 -0.3 TYP 115 135 pC 80 TYP dB 90 TYP 0.15 TYP % 1000 TYP MHz 1.1 1.2 3 pF (VDD = +16.5 V, VSS = -16.5 V) IDD Digital inputs = 0 V or VDD IDD Digital inputs = 5 V 0.001 TYP 1.0 220 TYP 420 ISS Digital inputs = 0 V or VDD 0.001 TYP 1.0 ISS Digital inputs = 5 V 0.001 TYP 1.0 µA See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Analog switch Analog signal range On Resistance Conditions 4/ Drain off leakage Channel on leakage IS(Off) ID(Off) ID, IS (On) Digital inputs Input high voltage VINH Input low voltage VINL Input current IINL or IINH Digital input capacitance CIN Dynamic characteristics 3/ tON tOFF Charge injection Off isolation Channel to channel crosstalk -3 dB bandwidth CS(Off) CD(Off) CD, CS (On) Power requirements 1/ 2/ 3/ 4/ Limits -40°C to +85°C -40°C to +125°C Min Max Min Max Unit 0 V to VDD RON VS =0 V to10 V, IS = -1 mA See Figure 10 VDD = 10.8 V, VSS = 0 V On Resistance match ∆RON VS = 0 V to10 V, IS = -1 mA between channel On Resistance flatness RFLAT(ON) VS = -3V/6 V, 9 V/+V; IS = -1 mA Leakage currents (VDD = 13.2 V, VSS = 0 V) Source off leakage 25°C Min Max VS = ±10 V, VD = ∓10 V See Figure 6 VS = ±10 V, VD = ∓10 V See Figure 6 VS = VD = ±10 V See Figure 7 V Ω 300 TYP 475 567 625 4.5 TYP 12 60 TYP 26 27 ±0.6 ±1 ±0.6 ±1 ±0.6 ±1 ±0.02 TYP ±0.1 ±0.02 TYP ±0.1 ±0.02 TYP ±0.1 nA 2.0 0.001 TYP 3 TYP RL = 300 Ω, CL = 35 pF, VS = 8 V; See Figure 13 80 TYP RL = 300 Ω, CL = 35 pF, VS = 8 V; See Figure 13 VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 14 RL = 50 Ω, CL = 5 pF, f = 1 MHz, See figure 8 RL = 50 Ω, CL = 5 pF, f = 1 MHz, See figure 9 RL = 50 Ω, CL = 5 pF, See Figure 11 VS = 0 V, f = 1 MHz V 0.8 ±0.1 µA pF ns 105 90 TYP 125 140 115 0 TYP 140 165 pC 80 TYP dB 90 TYP 900 TYP MHz 1.4 1.5 3.9 pF (VDD = +16.5 V, VSS = -16.5 V) IDD Digital inputs = 0 V or VDD ISS Digital inputs = 5 V 0.001 TYP 1.0 220 TYP 420 µA Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. VDD = 15 V ±10%, VSS = - 15 V ±10%, GND = 0 V, unless otherwise noted. Guaranteed by design, not subject to production test. VDD = 12 V ±10%, VSS = 0 V, GND = 0 V, unless otherwise noted DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 6 Case X e b 16 9 0°-8° E E1 PIN 1 IDENTIFIER 1 L 8 DETAIL A D SEE DETAIL A A1 A SEATING PLANE Symbol A A1 b c D Dimensions Millimeters Symbol Min Max 0.05 0.19 0.09 4.90 1.20 0.15 0.30 0.20 5.10 E E1 e L c Millimeters Min Max 4.30 4.50 6.40 BSC 0.65 BSC 0.45 0.75 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-15-AB3. FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 7 Case outline X Terminal Terminal symbol number IN1 9 D1 10 S1 11 Terminal number 1 2 3 Terminal symbol IN3 D3 S3 4 5 VSS GND 12 13 VDD 6 7 8 S4 D4 IN4 14 15 16 S2 D2 IN2 NC NOTES: 1. NC = No Connect. Do not connect to this pin. FIGURE 2. Terminal connections. Terminal Number Mnemonic 1 IN1 2 D1 3 S1 4 VSS 5 GND 6 S4 7 D4 8 IN4 9 IN3 10 D3 11 S3 12 NC 13 VDD 14 S2 15 D2 16 IN2 Case outline X Description Logic control input. Drain terminal. This pin can be an input or output. Source terminal. This pin can be an input or output. Most negative power supply potential. Ground (0 V) reference. Source terminal. This pin can be an input or output. Drain terminal. This pin can be an input or output. Logic control input. Logic control input. Drain terminal. This pin can be an input or output. Source terminal. This pin can be an input or output. No connection. Most positive power supply potential. Source terminal. This pin can be an input or output. Drain terminal. This pin can be an input or output. Logic control input. FIGURE 3. Terminal function. Input INx Switch condition 1 0 On Off FIGURE 4. Truth table DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 8 S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4 IN4 D4 NOTES: 1. Switches shown are for logic 1 input. FIGURE 5. Functional block diagram. IDS V1 IS(OFF) A S D ID(OFF) VS S A VS VD ION FIGURE 6. Off Leakage. DLA LAND AND MARITIME COLUMBUS, OHIO D =V1/IDS FIGURE 7. On Leakage SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 9 V DD 0.1 V SS F 0.1 V DD F NETWORK ANALYZER V SS S 50 50 IN VS D V IN RL V OUT 50 GND Off Isolation = 20 log VOUT VS FIGURE 8. Off isolation. V DD 0.1 NETWORK ANALYZER V OUT RL V SS F 0.1 V DD F V SS S1 50 D S2 R 50 GND VS Channel-to-channel crosstalk = 20 log VOUT VS FIGURE 9. Channel-to-channel crosstalk. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 10 S NC ID(ON) D A VD NC=NO CONNECT FIGURE 10. On resistance. V DD 0.1 V SS F 0.1 V DD F NETWORK ANALYZER V SS S 50 IN VS D V IN RL V OUT 50 GND Insertion loss = 20 log VOUT WITH Switch VOUT WITOUT SWITCH FIGURE 11. Bandwidth V SS V DD 0.1 F 0.1 F AUDIO PRECISION V SS V DD RS S IN VS V P-P D V IN GND V OUT RL 10 k FIGURE 12. THD + Noise DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 11 V DD 0.1 V SS F 0.1 V DD V SS S VS F D V IN 50% V OUT 90% V OUT RL IN 300 CL 35 pF t ON GND t OFF FIGURE 13. Switching times. RS V DD V SS V DD V SS S V IN D VS CL IN ON OFF V OUT 1 nF V OUT QINJ =C L x VOUT VOUT GND FIGURE 14. Charge injection. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12617-01XB 24355 ADG1212SRU-EP-RL7 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices 1 Technology Way P.O. Box 9106 Norwood, MA 02062-9106 SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/12617 PAGE 13