a FEATURES 1.8 V to 5.5 V Single Supply Low On Resistance (2.5 Typ) Low On-Resistance Flatness (0.5 ) –3 dB Bandwidth > 200 MHz Rail-to-Rail Operation 20-Lead 4 mm 4 mm Chip Scale Package Fast Switching Times t ON = 16 ns t OFF = 10 ns Typical Power Consumption (< 0.01 W) TTL/CMOS Compatible For Functionally Equivalent Devices in 16-Lead TSSOP and SOIC Packages, See ADG711/ADG712/ADG713 2.5 Quad SPST Switches in Chip Scale Package ADG781/ADG782/ADG783 FUNCTIONAL BLOCK DIAGRAMS S1 IN1 IN1 D1 D1 S2 S2 IN2 IN2 S3 IN3 D3 D3 S4 S4 IN4 D4 D2 ADG783 S3 IN3 IN4 S2 D2 ADG782 S3 IN3 D1 IN2 D2 ADG781 S1 S1 IN1 D3 S4 IN4 D4 D4 SWITCHES SHOWN FOR A LOGIC “1” INPUT APPLICATIONS Battery Powered Systems Communication Systems Sample Hold Systems Audio Signal Routing Video Switching Mechanical Reed Relay Replacement GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG781, ADG782, and ADG783 are monolithic CMOS devices containing four independently selectable switches. These switches are designed on an advanced submicron process that provides low power dissipation and high switching speed, low on resistance, low leakage currents and high bandwidth. 1. 20-Lead 4 mm ⫻ 4 mm Chip Scale Package (CSP). They are designed to operate from a single 1.8 V to 5.5 V supply, making them ideal for use in battery powered instruments and with the new generation of DACs and ADCs from Analog Devices. Fast switching times and high bandwidth make the part suitable for video signal switching. 3. Very Low RON (4.5 Ω max at 5 V, 8 Ω max at 3 V). At supply voltage of 1.8 V, RON is typically 35 Ω over the temperature range. The ADG781, ADG782, and ADG783 contain four independent single-pole/single throw (SPST) switches. The ADG781 and ADG782 differ only in that the digital control logic is inverted. The ADG781 switches are turned on with a logic low on the appropriate control input, while a logic high is required to turn on the switches of the ADG782. The ADG783 contains two switches whose digital control logic is similar to the ADG781, while the logic is inverted on the other two switches. 2. 1.8 V to 5.5 V Single Supply Operation. The ADG781, ADG782, and ADG783 offer high performance and are fully specified and guaranteed with 3 V and 5 V supply rails. 4. Low On-Resistance Flatness. 5. –3 dB Bandwidth >200 MHz. 6. Low Power Dissipation. CMOS construction ensures low power dissipation. 7. Fast tON/tOFF. 8. Break-Before-Make Switching. This prevents channel shorting when the switches are configured as a multiplexer (ADG783 only). Each switch conducts equally well in both directions when ON. The ADG783 exhibits break-before-make switching action. The ADG781/ADG782/ADG783 are available in 20-lead chip scale packages. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/461-3113 © Analog Devices, Inc., 2013 ADG781/ADG782/ADG783–SPECIFICATIONS Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT(ON)) B Version –40C to +25C +85C 0 V to VDD 2.5 4 4.5 0.05 0.4 0.5 1.0 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 11 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments VS = 0 V to VDD, IS = –10 mA; Test Circuit 1 VS = 0 V to VDD, IS = –10 mA VS = 0 V to VDD, IS = –10 mA VDD = 5.5 V; VS = 4.5 V/1 V, VD = 1 V/4.5 V; Test Circuit 2 VS = 4.5 V/1 V, VD = 1 V/4.5 V; Test Circuit 2 VS = VD = 1 V, or 4.5 V; Test Circuit 3 ± 0.2 nA typ nA max nA typ nA max nA typ nA max 2.4 0.8 V min V max ± 0.1 μA typ μA max VIN = VINL or VINH RL = 300 Ω, CL = 35 pF, VS = 3 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS = 3 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; Test Circuit 5 VS = 2 V; RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 10 MHz; Test Circuit 8 RL = 50 Ω, CL = 5 pF; Test Circuit 9 f = 1 MHz f = 1 MHz f = 1 MHz ± 0.2 ± 0.2 tOFF 6 Break-Before-Make Time Delay, tD (ADG783 Only) Charge Injection 6 3 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –58 –78 dB typ dB typ Channel-to-Channel Crosstalk –90 dB typ Bandwidth –3 dB CS (OFF) CD (OFF) CD, CS (ON) 200 10 10 22 MHz typ pF typ pF typ pF typ 0.001 μA typ μA max 16 10 POWER REQUIREMENTS IDD (VDD = 5 V 10%, GND = 0 V. All specifications –40C to +85C unless otherwise noted.) 1 1.0 VDD = 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1 Temperature ranges are as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. C ADG781/ADG782/ADG783 SPECIFICATIONS1 (VDD = 3 V 10%, GND = 0 V. All specifications –40C to +85C unless otherwise noted.) Parameter B Version –40C to +25C +85C ANALOG SWITCH Analog Signal Range On Resistance (RON) 5 On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) 0 V to VDD 5.5 10 VS = 0 V to VDD, IS = –10 mA ± 0.2 nA typ nA max nA typ nA max nA typ nA max VDD = 3.3 V; VS = 3 V/1 V, VD = 1 V/3 V; Test Circuit 2 VS = 3 V/1 V, VD = 1 V/3 V; Test Circuit 2 VS = VD = 1 V, or 3 V; Test Circuit 3 2.0 0.8 V min V max ± 0.1 μA typ μA max VIN = VINL or VINH RL = 300 Ω, CL = 35 pF, VS = 2 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS = 2 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; Test Circuit 5 VS = 1.5 V; RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 10 MHz; Test Circuit 8 RL = 50 Ω, CL = 5 pF; Test Circuit 9 f = 1 MHz f = 1 MHz f = 1 MHz 0.5 2.5 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 13 ± 0.2 ± 0.2 tOFF 7 Break-Before-Make Time Delay, tD (ADG783 Only) Charge Injection 7 3 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –58 –78 dB typ dB typ Channel-to-Channel Crosstalk –90 dB typ Bandwidth –3 dB CS (OFF) CD (OFF) CD, CS (ON) 200 10 10 22 MHz typ pF typ pF typ pF typ 0.001 μA typ μA max 20 12 POWER REQUIREMENTS IDD 1 1.0 NOTES 1 Temperature ranges are as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. C Test Conditions/Comments V Ω typ Ω max Ω typ Ω max Ω typ 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 Unit –3– VS = 0 V to VDD, IS = –10 mA; Test Circuit 1 VS = 0 V to VDD, IS = –10 mA VDD = 3.3 V Digital Inputs = 0 V or 3.3 V ADG781/ADG782/ADG783 ABSOLUTE MAXIMUM RATINGS 1 Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C IR Reflow (<20 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235°C (TA = 25°C unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Analog, Digital Inputs2 . . . . . . . . . . –0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Chip Scale Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 32°C/W NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. Table I. Truth Table (ADG781/ADG782) PIN CONFIGURATION OFF ON ON OFF 18 NC 16 NC 13 VDD 12 S3 11 D3 NC 10 0 1 6 D4 5 14 S2 TOP VIEW (Not to Scale) 7 S4 4 Switch 2, 3 NC Switch 1, 4 GND 3 IN4 Logic ADG781/ ADG782/ ADG783 S1 2 Table II. Truth Table (ADG783) 17 IN2 15 D2 D1 1 8 ON OFF 9 1 0 NC 0 1 IN3 Switch Condition 20 NC ADG782 In 19 IN1 (LFCSP) ADG781 In NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, GND. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG781/ADG782/ADG783 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. C ADG781/ADG782/ADG783 TERMINOLOGY VDD Most positive power supply potential. GND S D IN RON ΔRON Ground (0 V) reference. Source terminal. May be an input or output. Drain terminal. May be an input or output. Logic control input. Ohmic resistance between D and S. On-resistance match between any two channels (i.e., RON max and RON min). Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. Source leakage current with the switch “OFF.” Drain leakage current with the switch “OFF.” Channel leakage current with the switch “ON.” Analog voltage on terminals D, S. “OFF” switch source capacitance. “OFF” switch drain capacitance. RFLAT(ON) IS (OFF) ID (OFF) ID, IS (ON) VD (VS) CS (OFF) CD (OFF) CD, CS (ON) tON tOFF tD Crosstalk Off Isolation Charge Injection On Response On Loss “ON” switch capacitance. Delay between applying the digital control input and the output switching on. Delay between applying the digital control input and the output switching off. “OFF” time or “ON” time measured between the 90% points of both switches, when switching from one address state to another (ADG783 only). A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an “OFF” switch. A measure of the glitch impulse transferred from the digital input to the analog output during switching. The frequency response of the “ON” switch. The loss due to the on resistance of the switch. Typical Performance Characteristics 6 6 TA = 25C 5.5 5.5 VDD = 2.7V 5 4.5 4.5 4 3.5 VDD = 4.5V RON – RON – 4 VDD = 3V 3 2.5 2 +85C 3.5 +25C 3 2.5 2 VDD = 5V 1.5 1.5 1 1 0.5 0.5 0 –40C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V 5 0 TPC 1. On Resistance as a Function of VD (VS) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V 5 TPC 3. On Resistance as a Function of VD (VS) for Different Temperatures VDD = 5 V 6 10m VDD = 5V VDD = 3V 5.5 5 1m +85C 4.5 +25C 100 ISUPPLY – Amps 4 RON – VDD = 5V 5 3.5 3 2.5 –40C 2 4 SW 10 1 SW 1 100n 1.5 1 10n 0.5 1n 100 0 0 0.5 1 1.5 2 2.5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V 3 TPC 2. On Resistance as a Function of VD (VS) for Different Temperatures VDD = 3 V REV. C 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 4. Supply Current vs. Input Switching Frequency –5– ADG781/ADG782/ADG783 –30 0 –40 VDD = 5V, 3V –50 ON RESPONSE – dB OFF ISOLATION – dB VDD = 5V –60 –70 –80 –90 –100 –2 –4 –110 –120 –130 10k 100k 1M 10M FREQUENCY – Hz –6 10k 100M TPC 5. Off Isolation vs. Frequency 100k 100M 1M 10M FREQUENCY – Hz TPC 7. On Response vs. Frequency 25 –30 TA = 25C –40 20 VDD = 5V, 3V 15 –60 –70 QINJ – pC CROSSTALK – dB –50 –80 –90 –100 10 VDD = 5V VDD = 3V 5 0 –110 –5 –120 –10 –130 10k 100k 1M 10M FREQUENCY – Hz 0 100M 0.5 1 1.5 2 2.5 3 3.5 SOURCE VOLTAGE – V 4 4.5 5 TPC 8. Charge Injection vs. Source Voltage TPC 6. Crosstalk vs. Frequency APPLICATIONS C1 Figure 1 illustrates a photodetector circuit with programmable gain. An AD820 is used as the output operational amplifier. With the resistor values shown in the circuit, and using different combinations of the switches, gain in the range of 2 to 16 can be achieved. R1 33k 5V AD820 D1 2.5V VOUT R2 510k 5V S1 D1 R4 240k R5 240k S2 D2 R6 120k R7 120k S3 D3 R8 120k S4 D4 R9 120k (LSB) IN1 IN2 IN3 (MSB) IN4 GND R3 510k 2.5V R10 120k GAIN RANGE 2 TO 16 Figure 1. Photodetector Circuit with Programmable Gain –6– REV. C ADG781/ADG782/ADG783 Test Circuits V IS (OFF) S D D S NC A VS IDS VS ID (OFF) S A D ID (ON) A VD VD NC = NO CONNECT RON = V/IDS Test Circuit 1. On Resistance Test Circuit 2. Off Leakage Test Circuit 3. On Leakage VDD 0.1F VDD D S 50% 50% VIN ADG782 50% 50% VOUT RL 300 IN VS VIN ADG781 VS CL 35pF VOUT 90% 90% GND t ON t OFF Test Circuit 4. Switching Times VDD VIN 0.1F 50% 0V VDD S1 VS1 D1 D2 S2 VS2 VIN VOUT2 CL2 35pF RL2 300 IN1, IN2 RL1 300 CL1 35pF VOUT1 VOUT1 90% 90% 0V 90% VOUT2 ADG783 50% 90% 0V GND tD tD Test Circuit 5. Break-Before-Make Time Delay, tD SW ON VDD SW OFF VIN VDD RS VS D S VOUT CL 1nF IN GND VOUT VOUT Q INJ = CL VOUT Test Circuit 6. Charge Injection VDD VDD 0.1F 0.1F NETWORK ANALYZER NETWORK ANALYZER VDD S 50 IN GND S2 VS RL 50 VOUT NC D2 RL 50 50 OFF ISOLATION = 20 LOG VS IN GND CHANNEL-TO-CHANNEL V CROSSTALK = 20 LOG OUT VS VOUT VS Test Circuit 7. Off Isolation REV. C S1 RL 50 50 D VIN VDD D1 VOUT Test Circuit 8. Channel-to-Channel Crosstalk –7– ADG781/ADG782/ADG783 VDD 0.1F NETWORK ANALYZER VDD S 50 IN VS D VIN RL 50 GND INSERTION LOSS = 20 LOG VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH Test Circuit 9. Bandwidth –8– REV. C ADG781/ADG782/ADG783 OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. 08-16-2010-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 2. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-6) Dimensions shown in millimeters ORDERING GUIDE Model1 ADG781BCPZ ADG781BCPZ-REEL7 ADG782BCPZ ADG782BCPZ-REEL7 ADG783BCPZ ADG783BCPZ-REEL ADG783BCPZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. REVISION HISTORY 2/13—Rev. B to Rev. C Changed Pin 4 from S3 to S4 ........................................................... 4 Changes to Test Circuit 1 ................................................................. 7 Changes to Ordering Guide ............................................................. 9 8/12—Rev. A to Rev. B Updated Outline Dimensions .......................................................... 9 Changes to Ordering Guide ............................................................. 9 3/02—Rev. 0 to Rev. A Edits to Typical Performance Characteristics ........................... 5-6 Changes to OUTLINE DIMENSIONS drawing ........................... 8 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02372-0-2/13(C) REV. C –9– Package Option CP-20-6 CP-20-6 CP-20-6 CP-20-6 CP-20-6 CP-20-6 CP-20-6