ADG859: 1.3 CMOS, 1.8 V to 5.5 V Single SPDT Switch/2:1 MUX in SOT-66 Package Data Sheet (Rev. A) PDF

1.3 Ω CMOS, 1.8 V to 5.5 V Single SPDT
Switch/2:1 MUX in SOT-66 Package
ADG859
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.8 V to 5.5 V single supply
Tiny 1.65 mm × 1.65 mm package
Low on resistance: 1.3 Ω at 5 V supply
High current-carrying capability:
300 mA continuous current
500 mA peak current at 5 V
Rail-to-rail operation
Typical power consumption: <0.01 μW
TTL-/CMOS-compatible inputs
ADG859
S2
D
S1
SWITCHES SHOWN
FOR A LOGIC 1 INPUT
05258-001
IN
Figure 1.
APPLICATIONS
Cellular phones
PDAs
MP3 players
Battery-powered systems
Audio and video signal routing
Modems
PCMCIA cards
Hard drives
Relay replacement
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG859 is a monolithic, CMOS SPDT (single pole, double
throw) switch that operates with a supply range of 1.8 V to
5.5 V. It is designed to offer low on resistance of 2.3 Ω maximum over the entire temperature range of −40°C to +125°C.
The ADG859 also has the capability of carrying large amounts
of current, typically 300 mA at 5 V operation. These features
make the ADG859 an ideal solution for applications that are
space-constrained, such as handsets, PDAs, and MP3 players.
1.
Low on resistance: 2.3 Ω maximum over the full
temperature range of −40°C to +125°C.
2.
High current-carrying capability.
3.
Tiny 6-lead, 1.65 mm × 1.65 mm SOT-66 package.
Each switch conducts equally well in both directions when on.
The device exhibits break-before-make switching action,
thereby preventing momentary shorting when switching
channels.
The ADG859 is available in a tiny 6-lead SOT-66 package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADG859
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Applications....................................................................................... 1
Pin Configuration and Function Descriptions..............................6
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................7
General Description ......................................................................... 1
Test Circuits..................................................................................... 10
Product Highlights ........................................................................... 1
Terminology .................................................................................... 12
Revision History ............................................................................... 2
Outline Dimensions ....................................................................... 13
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 13
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
12/06—Rev. 0 to Rev. A
Changes to the Ordering Guide.................................................... 13
6/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG859
SPECIFICATIONS
VDD = 5 V ± 10%, GND = 0 V, unless otherwise noted.1
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+125°C
0 to VDD
1.3
2.1
0.01
0.093
0.32
0.45
2.2
2.3
0.163
0.163
0.6
0.65
±0.02
±0.02
2
0.8
0.005
4
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
±13
−78
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
−78
dB typ
−3 dB Bandwidth
Insertion Loss
Total Harmonic Distortion (THD + N)
125
−0.11
0.062
MHz typ
dB typ
%
18
45
pF typ
pF typ
11
12
6.5
7
1
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
0.001
1
2
V min
V max
μA typ
μA max
pF typ
8
10
4.5
6
4
tOFF
1
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA typ
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
Unit
Temperature range is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 16
μA typ
μA max
Test Conditions/Comments
VDD = 4.5 V, VS = 0 V to VDD, IS = −100 mA;
Figure 16
VDD = 4.5 V, VS = 4.5V, IS = −100 mA;
Figure 16
VDD = 4.5 V, VS = 0 V to VDD, IS = −100 mA;
Figure 16
VDD = 5.5 V
VS = 4.5 V/1 V, VD = 1 V/4.5 V; Figure 17
VS = VD = 1 V or 4.5 V; Figure 18
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = 3 V; Figure 19
RL = 50 Ω, CL = 35 pF
VS = 3 V; Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; Figure 20
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 22
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 23
RL = 50 Ω, CL = 5 pF; Figure 24
RL = 50 Ω, CL = 5 pF; Figure 24
RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 3 V p-p; Figure 14
f = 1 MHz
f = 1 MHz
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
ADG859
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.1
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IIN
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
25°C
−40°C to
+85°C
−40°C to
+125°C
0 to VDD
3
4.3
0.03
0.11
4.5
4.7
0.15
0.15
±0.02
±0.05
nA typ
nA typ
2.0
0.8
0.7
0.005
±0.1
±0.1
16
17
10
11
4
V min
V max
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
±7
−78
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
−78
dB typ
−3 dB Bandwidth
Insertion Loss
Total Harmonic Distortion (THD + N)
125
−0.11
0.1
MHz typ
dB typ
%
18
46
pF typ
pF typ
1
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
0.001
1
2
V
Ω typ
Ω max
Ω typ
Ω max
11
15
6
9.5
5
tOFF
1
Unit
Temperature range is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 16
μA typ
μA max
Test Conditions/Comments
VDD = 2.7 V, VS = 0 V to VDD, IS = −100 mA;
Figure 16
VDD = 2.7 V, VS = 1.2 V, IS = −100 mA;
Figure 16
VDD = 3.6 V
VS = 3 V/1 V, VD = 1 V/3 V; Figure 17
VS = VD = 1 V or 3 V; Figure 18
VDD = 3 V to 3.6 V
VDD = 2.7 V
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; Figure 19
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; Figure 20
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 22
S1 to S2; RL = 50 Ω, CL = 5 pF,
f = 100 kHz; Figure 23
RL = 50 Ω, CL = 5 pF; Figure 24
RL = 50 Ω, CL = 5 pF; Figure 24
RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 2 V p-p; Figure 14
f = 1 MHz
f = 1 MHz
VDD = 3.6 V
Digital inputs = 0 V or 3.6 V
ADG859
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Rating
−0.3 V to +7.0 V
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
500 mA
460 mA
Table 4. Truth Table
300 mA
275 mA
Logic (IN)
0
1
Table 3.
Parameter
VDD to GND
Analog Inputs 1
Digital Inputs1
Peak Current, S or D
5 V Operation
3 V Operation
Continuous Current, S or D
5 V Operation
3 V Operation
Operating Temperature Range
Automotive
Storage Temperature Range
Junction Temperature
SOT-66 Package (4-Layer Board)
θJA Thermal Impedance
Lead-Free Reflow
Peak Temperature
Time at Peak Temperature
1
Switch 2 (S2)
Off
On
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
191°C/W
260 (+0/−5)°C
10 sec to 40 sec
Overvoltages at S or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. A | Page 5 of 16
Switch 1 (S1)
On
Off
ADG859
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN 1
6
S2
ADG859
5 D
TOP VIEW
(Not to Scale)
GND 3
4
S1
05258-002
VDD 2
Figure 2. 6-Lead SOT-66 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
IN
VDD
GND
S1
D
S2
Description
Logic Control Input.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Rev. A | Page 6 of 16
ADG859
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.8
VDD = 4.5V
1.6
3.0
TA = 25°C
IDS = 100mA
+125°C
2.5
1.2
1.0
0.8
VDD = 5.5V
0.6
0.4
2.0
+25°C
1.5
–40°C
1.0
VDD = 3V
IDS = 100mA
05258-012
0.5
0.2
0
0
1
2
3
4
0
5
0
0.5
1.0
VS/VD (V)
1.5
2.0
Figure 6. On Resistance vs. Source Voltage for
Different Temperatures, VDD = 3 V
3.0
5
TA = 25°C
IDS = 100mA
VDD = 2.7V
VDD = 5V
2.5
4
VDD = 3V
1.5
LEAKAGE (nA)
VDD = 3.3V
VDD = 3.6V
1.0
0.5
ID, IS (ON)
3
2
1
IS (OFF)
0
0.5
1.0
1.5
2.0
2.5
3.0
–1
–40
3.5
05258-016
05258-024
0
–20
0
VS/VD (V)
Figure 4. On Resistance vs. VS (VD), VDD = 2.7 V to 3.6 V
40
60
80
100
120
Figure 7. Leakage vs. Temperature, VDD = 5 V
4.5
1.8
1.6
4.0
+125°C
+85°C
1.4
VDD = 3V
3.5
ID, IS (ON)
3.0
LEAKAGE (nA)
1.2
1.0
0.8
+25°C
–40°C
0.6
2.5
2.0
1.5
1.0
0.4
0.5
VDD = 5V
IDS = 100mA
0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
05258-014
ON RESISTANCE (Ω)
20
TEMPERATURE (°C)
5.0
0
–0.5
–40
IS (OFF)
–20
0
20
40
60
80
100
TEMPERATURE (°C)
SOURCE VOLTAGE (V)
Figure 5. On Resistance vs. Source Voltage for
Different Temperatures, VDD = 5 V
Figure 8. Leakage vs. Temperature, VDD = 3 V
Rev. A | Page 7 of 16
120
05258-015
RON (Ω)
2.0
0
3.0
SOURCE VOLTAGE (V)
Figure 3. On Resistance vs. VS (VD), VDD = 5 V ± 10%
0
2.5
05258-013
ON RESISTANCE (Ω)
1.4
RON (Ω)
+85°C
VDD = 5V
ADG859
30
0
TA = 25°C
TA = 25°C
VDD = 3V/5V
–20
20
ATTENUATION (dB)
VDD = 5V
15
VDD = 3V
10
5
–60
–80
–100
05258-017
0
–40
0.5
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–120
100
5.0
05258-020
CHARGE INJECTION (pC)
25
1k
10k
VD (V)
14
100M
10M
100M
TA = 25°C
VDD = 3V/5V
–20
ATTENUATION (dB)
VDD = 3.3V
10
tON
8
VDD = 5V
6
VDD = 3.3V
tOFF
4
–40
–60
–80
VDD = 5V
–100
0
–40
05258-018
2
–20
0
20
40
60
–120
100
80
05258-021
TIME (ns)
10M
0
12
1k
10k
TEMPERATURE (°C)
100k
1M
FREQUENCY (Hz)
Figure 13. Crosstalk vs. Frequency
Figure 10. tON/tOFF Times vs. Temperature
0.20
0
TA = 25°C
0.18
–2
0.16
TA = 25°C
VDD = 3V/5V
0.14
THD + N (%)
–4
–6
–8
0.12
VDD = 3V, VS = 2V p-p
0.10
0.08
0.06
VDD = 5V, VS = 3V p-p
1k
10k
100k
1M
10M
100M
1G
05258-022
0.04
–10
05258-019
ON RESPONSE (dB)
1M
Figure 12. Off Isolation vs. Frequency
Figure 9. Charge Injection vs. Source Voltage
–12
100
100k
FREQUENCY (Hz)
0.02
0
0
5k
10k
15k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. Total Harmonic Distortion + Noise
Figure 11. Bandwidth
Rev. A | Page 8 of 16
20k
ADG859
0
–20
TA = 25°C
VDD = 3V/5V
NO SUPPLY DECOUPLING
–60
–80
–100
–120
100
05258-023
PSRR (dB)
–40
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 15. PSRR
Rev. A | Page 9 of 16
ADG859
TEST CIRCUITS
V
S
D
05258-003
IDS
VS
Figure 16. On Resistance
IS (OFF)
S
A
ID (OFF)
D
A
VD
05258-004
VS
Figure 17. Off Leakage
ID (ON)
D
A
VD
NC = NO CONNECT
05258-005
S
NC
Figure 18. On Leakage
VDD
0.1µF
VIN
50%
50%
VIN
50%
50%
VDD
VOUT
D
RL
50Ω
IN
VIN
CL
35pF
90%
VOUT
GND
tON
90%
tOFF
05258-006
S2
S1
VS
Figure 19. Switching Times, tON, tOFF
0.1µF
VDD
VIN
VDD
S2
S1
VS
VOUT
D
RL
50Ω
IN
80%
VOUT
CL
35pF
tBBM
VIN
tBBM
05258-007
GND
Figure 20. Break-Before-Make Time Delay, tBBM
0.1µF
VDD
VIN (NORMALLY
CLOSED SWITCH)
VDD
D
S2
CL
1nF
IN
VIN
NC
S1
GND
VOUT
OFF
VIN (NORMALLY
OPEN SWITCH)
VOUT
ΔVOUT
QINJ = CL × ΔVOUT
05258-008
VS
ON
NC = NO CONNECT
Figure 21. Charge Injection
Rev. A | Page 10 of 16
ADG859
VDD
0.1µF
VDD
S1
IN
NETWORK
ANALYZER
NC
S2
50Ω
50Ω
VS
D
VIN
RL
50Ω
GND
VOUT
05258-009
OFF ISOLATION = 20 log
VOUT
VS
NC = NO CONNECT
Figure 22. Off Isolation
VDD
0.1µF
NETWORK
ANALYZER
VDD
S1
VOUT
RL
50Ω
D
S2
50Ω
R
50Ω
IN
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
05258-010
GND
VOUT
VS
Figure 23. Channel-to-Channel Crosstalk
VDD
0.1µF
VDD
S1
50Ω
S2
VS
D
VIN
RL
50Ω
GND
INSERTION LOSS = 20 log
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
NC = NO CONNECT
Figure 24. Bandwidth
Rev. A | Page 11 of 16
05258-011
IN
NETWORK
ANALYZER
NC
ADG859
TERMINOLOGY
VDD
Most positive power supply potential.
CD (Off)
Off switch drain capacitance. Measured with reference to
ground.
IDD
Positive supply current.
CD, CS (On)
On switch capacitance. Measured with reference to ground.
GND
Ground (0 V) reference.
CIN
Digital input capacitance.
S
Source terminal. Can be an input or an output.
tON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
D
Drain terminal. Can be an input or an output.
tOFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
IN
Logic control input.
VD (VS)
Analog voltage on the D and S terminals.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.
RON
Ohmic resistance between the D and S terminals.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
ΔRON
On resistance mismatch between any two channels.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during on/off switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
IS (Off)
Source leakage current with the switch off.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
ID (Off)
Drain leakage current with the switch off.
−3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
ID, IS (On)
Channel leakage current with the switch on.
On Response
The frequency response of the on switch.
VINL
Maximum input voltage for Logic 0.
Insertion Loss
The loss due to the on resistance of the switch.
VINH
Minimum input voltage for Logic 1.
THD + N
The ratio of harmonic amplitudes plus noise of a signal to the
fundamental.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to
ground.
Rev. A | Page 12 of 16
ADG859
OUTLINE DIMENSIONS
1.70
1.66
1.50
6
1.30
1.20
1.10
5
4
TOP VIEW
1
2
0.20 MIN
0.26
0.19
0.11
1.70
1.65
1.50
3
BOTTOM
VIEW
0.10 NOM
0.05 MIN
PIN 1
12° MAX
0.60
0.57
0.53
0.18
0.17
0.13
0.34 MAX
0.27 NOM
0.50
BSC
0.30
0.23
0.10
0.25 MAX
0.17 MIN
SEATING
PLANE
Figure 25. 6-Lead Small Outline Transistor Package [SOT-66]
(RY-6-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG859YRYZ-REEL2
ADG859YRYZ-REEL7 2
ADG859BRYZ-REEL2
ADG859BRYZ-REEL72
EVAL-ADG859EB
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
Package Description
6-Lead Small Outline Transistor Package [SOT-66]
6-Lead Small Outline Transistor Package [SOT-66]
6-Lead Small Outline Transistor Package [SOT-66]
6-Lead Small Outline Transistor Package [SOT-66]
Evaluation Board
Branding on this package is limited to two characters due to space constraints.
Z = Pb-free part.
Rev. A | Page 13 of 16
Package Option
RY-6-1
RY-6-1
RY-6-1
RY-6-1
Branding 1
04
04
02
02
ADG859
NOTES
Rev. A | Page 14 of 16
ADG859
NOTES
Rev. A | Page 15 of 16
ADG859
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05258-0-12/06(A)
Rev. A | Page 16 of 16
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