0.5 Ω CMOS, Dual 2:1 MUX/SPDT Audio Switch ADG884 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V to 5.5 V operation Ultralow on resistance 0.28 Ω typical at 5 V supply 0.41 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion 0.1 Ω typical 0.15 Ω maximum RON flatness High current carrying capability 400 mA continuous 600 mA peak current at 5 V supply Rail-to-rail switching operation Typical power consumption (<0.1 μW) ADG884 S1A D1 S1B IN1 IN2 S2A D2 NOTES: 1. SWITCHES SHOWN FOR A LOGIC 1 INPUT. 05028-001 S2B Figure 1. APPLICATIONS Cellular phones PDAs MP3 players Power routing Battery-powered systems PCMCIA cards Modems Audio and video signal routing Communications systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG884 is a low voltage CMOS device containing two independently selectable single-pole, double-throw (SPDT) switches. This device offers ultralow on resistance of 0.41 Ω over the full temperature range, making the part an ideal solution for applications that require minimal distortion through the switch. The ADG884 also has the capability of carrying large amounts of current, typically 600 mA at 5 V operation. 1. 2. 3. 4. 5. Single 1.8 V to 5.5 V operation. High current handling capability (400 mA continuous current). 1.8 V logic compatible. Low THD + N (0.01% typical). Tiny 2 mm × 1.5 mm WLCSP, 3 mm × 3 mm 10-lead LFCSP_WD, and 10-lead MSOP packages. The ADG884 is available in a 10-ball, 2 mm × 1.5 mm WLCSP package, a 10-lead LFCSP_WD package, and a 10-lead MSOP package. These tiny packages make the ADG884 the ideal solution for space-constrained applications. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The ADG884 exhibits break-before-make switching action. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. ADG884 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications....................................................................................... 1 Pin Configurations and Function Descriptions ............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Test Circuits..................................................................................... 11 Product Highlights ........................................................................... 1 Terminology .................................................................................... 13 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 14 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 15 Absolute Maximum Ratings............................................................ 6 REVISION HISTORY 4/12—Rev. C to Rev. D Added Exposed Pad Notation to Figure 2 and Table 5................ 7 Changes to Figure 3 and Table 6..................................................... 7 6/08—Rev. B to Rev. C Changes to Temperature Range........................................Universal Changes to Product Highlights....................................................... 1 Changes to Table 4............................................................................ 6 Updated Outline Dimensions ....................................................... 14 Changes to the Ordering Guide.................................................... 15 7/06—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 5 Changes to Table 4............................................................................ 6 Changes to the Ordering Guide.................................................... 15 6/05—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 10/04—Revision 0: Initial Version Rev. D | Page 2 of 16 Data Sheet ADG884 SPECIFICATIONS VDD = 5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 0.28 0.37 0.01 0.035 0.1 0.13 −40°C to +85°C Unit Test Conditions/Comments 0 to VDD V Ω typ Ω max Ω typ VDD = 4.5 V, VS = 0 V to VDD, IS = 100 mA See Figure 18 VDD = 4.5 V, VS = 2 V, IS = 100 mA 0.41 0.05 0.15 ±0.2 ±0.2 nA typ nA typ 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON 2 V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tBBM 42 50 15 20 16 Charge Injection Off Isolation Channel-to-Channel Crosstalk 125 −60 −120 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ −60 dB typ 0.017 −0.03 18 103 295 % typ dB typ MHz typ pF typ pF typ 0.003 μA typ μA max tOFF 53 21 10 Total Harmonic Distortion, THD + N Insertion Loss −3 dB Bandwidth CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 1 1 Ω max Ω typ Ω max Guaranteed by design, not production tested. Rev. D | Page 3 of 16 VDD = 4.5 V, VS = 0 V to VDD IS = 100 mA VDD = 5.5 V VS = 0.6 V/4.5 V, VD = 4.5 V/0.6 V; see Figure 19 VS = VD = 0.6 V or 4.5 V; see Figure 20 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 3 V/0 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS = 3 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 22 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p RL = 50 Ω, CL = 5 pF; see Figure 26 RL = 50 Ω, CL = 5 pF; see Figure 26 VDD = 5.5 V Digital inputs = 0 V or 5.5 V ADG884 Data Sheet VDD = 3.4 V to 4.2 V; GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 0.33 0.4 0.013 0.042 0.13 0.155 −40°C to +85°C Unit Test Conditions/Comments 0 to VDD V Ω typ Ω max Ω typ VDD = 3.4 V, VS = 0 V to VDD, IS = 100 mA See Figure 18 VDD = 3.4 V, VS = 2 V, IS = 100 mA 0.47 0.065 0.175 ±0.2 ±0.2 nA typ nA typ 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON 2 V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tBBM 42 50 15 21 17 Charge Injection Off Isolation Channel-to-Channel Crosstalk 100 −60 −120 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ −60 dB typ 0.01 −0.03 18 110 300 % typ dB typ MHz typ pF typ pF typ 0.003 μA typ μA max tOFF 54 24 10 Total Harmonic Distortion, THD + N Insertion Loss −3 dB Bandwidth CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 1 1 Ω max Ω typ Ω max Guaranteed by design, not production tested. Rev. D | Page 4 of 16 VDD = 3.4 V, VS = 0 V to VDD IS = 100 mA VDD = 4.2 V VS = 0.6 V/3.9 V, VD = 3.9 V/0.6 V; see Figure 19 VS = VD = 0.6 V or 3.9 V; see Figure 20 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 1.5 V/0 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS = 1.5 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 22 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p RL = 50 Ω, CL = 5 pF; see Figure 26 RL = 50 Ω, CL = 5 pF; see Figure 26 VDD = 4.2 V Digital inputs = 0 V or 4.2 V Data Sheet ADG884 VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25°C On-Resistance Match Between Channels, ∆RON 0.4 0.51 0.02 On-Resistance Flatness, RFLAT (On) 0.07 0.18 −40°C to +85°C Unit Test Conditions/Comments 0 to VDD V Ω typ Ω max Ω typ VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA; see Figure 18 VDD = 2.7 V, VS = 0.6 V 0.61 0.1 0.25 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±0.2 ±0.2 nA typ nA typ 1.3 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON 2 V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tBBM 42 56 14 19 24 Charge Injection Off Isolation Channel-to-Channel Crosstalk 85 −60 −120 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ −60 dB typ 0.03 −0.03 18 110 300 % typ dB typ MHz typ pF typ pF typ 0.003 μA typ μA max tOFF 62 21 10 Total Harmonic Distortion, THD + N Insertion Loss –3 dB Bandwidth CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 1 1 Ω max Ω typ Ω max Guaranteed by design, not production tested. Rev. D | Page 5 of 16 IS = 100 mA VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA VDD = 3.6 V VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 19 VS = VD = 0.6 V or 3.3 V; see Figure 20 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 1.5 V/0 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS = 1.5 V; see Figure 21 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 22 VS = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 23 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24 S1A to S2A/S1B to S2B, RL = 50 V, CL = 5 pF, f = 100 kHz; see Figure 27 S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p RL = 50 Ω, CL = 5 pF; see Figure 26 RL = 50 Ω, CL = 5 pF; see Figure 26 VDD = 3.6 V Digital inputs = 0 V or 3.6 V ADG884 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Analog Inputs, 1 Digital Inputs Peak Current, S or D Continuous Current, S or D Operating Temperature Range Storage Temperature Range Junction Temperature 10-Lead MSOP, Thermal Impedance θJA θJC 10-Ball WLCSP (4-Layer Board), Thermal Impedance θJA 10-Lead LFCSP_WD (4-Layer Board), Thermal Impedance θJA θJC Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +6 V −0.3 V to VDD + 0.3 V or 30 mA (whichever occurs first) 600 mA (pulsed at 1 ms, 10% duty cycle maximum) 400 mA −40°C to +85°C −65°C to +150°C 150°C 206°C/W 44°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION 120°C/W 76°C/W 13.5°C/W 260(+ 0 or −5)°C 10 sec to 40 sec Overvoltages at IN, S, or D pins are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. D | Page 6 of 16 Data Sheet ADG884 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADG884 9 D2 TOP VIEW (Not to Scale) 8 IN2 7 S2B 6 GND D1 3 IN1 4 S1B 5 NOTES 1. THE LFCSP_WD PACKAGE HAS AN EXPOSED PAD THAT SHOULD BE TIED TO GROUND. A 2 3 GND S2B 1 2 IN1 B C D 3 IN2 4 ADG884 TOP VIEW D1 (Not to Scale) D2 5 9 10 S1A VDD S2A 8 7 6 (SOLDER BALLS ON OPPOSITE SIDE) Figure 2. LFCSP_WD and MSOP Pin Configuration 05028-028 10 S2A 05028-002 VDD 1 S1A 2 1 S1B Figure 3. WLCSP Pin Configuration Table 5. LFCSP_WD and MSOP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VDD S1A D1 IN1 S1B GND S2B IN2 D2 S2A EPAD Description Most Positive Power Supply Potential. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Source Terminal. Can be an input or output. Ground (0 V) Reference. Source Terminal. Can be an input or output. Login Control Input. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. The LFCSP_WD package has an exposed pad that should be tied to ground. Table 6. WLCSP Package Pin Function Description WLCSP Package Ball Number Location 1 A1 2 A2 3 A3 4 B3 5 C3 6 D3 7 D2 8 D1 9 C1 10 B1 Mnemonic S1B GND S2B IN2 D2 S2A VDD S1A D1 IN1 Description Source Terminal. Can be an input or output. Ground (0 V) Reference. Source Terminal. Can be an input or output. Login Control Input. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Positive Power Supply Potential. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Table 7. ADG884 Truth Table Logic (IN1/IN2) 0 1 Switch 1A/Switch 2A Off On Rev. D | Page 7 of 16 Switch 1B/Switch 2B On Off ADG884 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.30 0.45 TA = 25°C IDS = 100mA VDD = 3.3V IDS = 100mA 0.40 0.25 0.35 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 4.5V 4.2V 0.20 5.5V 0.15 5V 0.10 +85°C 0.30 +25°C 0.25 –40°C 0.20 0.15 0.10 0 1 2 3 SIGNAL RANGE (V) 4 0 5 Figure 4. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V 1.0 1.5 2.0 SIGNAL RANGE (V) 2.5 3.0 3 2.7V 0.30 3V 0.25 3.3V 0.20 VDD = 5V 4 LEAKAGE CURRENT (nA) 0.15 0.10 2 ID, IS (ON) 1 0 IS (OFF) –1 –2 05028-005 –3 0.05 0 0.5 1.0 1.5 2.0 SIGNAL RANGE (V) 2.5 05028-008 ON RESISTANCE (Ω) 0.35 –4 –5 3.0 Figure 5. On Resistance vs. VD (VS), VDD = 2.7 V to 3.3 V 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 Figure 8. Leakage Current vs. Temperature, VDD = 5 V 0.35 5 VDD = 5V IDS = 100mA 0.30 VDD = 4.2V 4 LEAKAGE CURRENT (nA) ON RESISTANCE (Ω) 0.5 5 TA = 25°C IDS = 100mA 0.40 0.25 +85°C 0.20 +25°C 0.15 –40°C 0.10 3 2 1 ID, IS (ON) 0 05028-006 0.05 0 0 Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V 0.45 0 05028-007 0.05 0 1 2 3 SIGNAL RANGE (V) 4 05028-009 0 05028-004 0.05 IS (OFF) –1 5 Figure 6. On Resistance vs. VD (VS) for Different Temperature, VDD = 5 V Rev. D | Page 8 of 16 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 Figure 9. Leakage Current vs. Temperature, VDD = 4.2 V 80 Data Sheet ADG884 4.0 0 VDD = 3.3V 3.5 –1 TA = 25°C VDD = 5V/4.2V/3V –2 2.5 ATTENUATION (dB) LEAKAGE CURRENT (nA) 3.0 2.0 1.5 ID, IS (ON) 1.0 0.5 –3 –4 –5 –6 0 IS (OFF) 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 –8 0.03 80 Figure 10. Leakage Current vs. Temperature, VDD = 3.3 V 05028-022 –1.0 –7 05028-026 –0.5 0.10 1.00 10.00 FREQUENCY (MHz) 100.00 Figure 13. Bandwidth, VDD = 5 V/4.2 V/3 V 600 0 TA = 25°C 500 –10 VDD = 5V TA = 25°C VDD = 5V/4.2V/3V ATTENUATION (dB) –20 QINJ (pC) 400 VDD = 4.2V 300 200 –30 –40 –50 –60 0.5 1.0 1.5 2.0 2.5 3.0 VS (V) 3.5 4.0 4.5 –80 10 5.0 50 ATTENUATION (dB) 30 20 VDD = 5V tOFF 100M 0 TA = 25°C VDD = 5V/3V 20 40 TEMPERATURE (°C) –30 –40 –50 –60 VDD = 3V 10 –20 10M –20 VDD = 3V –70 05028-011 TIME (ns) –10 VDD = 5V 0 –40 10k 100k 1M FREQUENCY (MHz) 0 TA = 25°C tON 1k Figure 14. Off Isolation vs. Frequency Figure 11. Charge Injection vs. Source Voltage 40 100 60 –80 100 80 05028-024 0 –70 05028-010 0 VDD = 3V 05028-023 100 1k 10k 100k 1M FREQUENCY (MHz) Figure 15. Crosstalk vs. Frequency Figure 12. tON/tOFF Times vs. Temperature Rev. D | Page 9 of 16 10M 100M ADG884 Data Sheet 0.10 0 –20 TA = 25°C VDD = 5V/4.2V/3V 0.09 0.08 0.07 –80 –100 0.06 0.05 0.04 VDD = 3V, 1.5V p-p 0.03 –120 VDD = 5V, 3.5V p-p 0.02 –140 –160 10 100 1k 10k 100k 1M FREQUENCY (MHz) 10M 100M Figure 16. AC PSRR 0.01 0 VDD = 4.2V, 2V p-p 0 10 20 30 40 50 60 70 FREQUENCY (kHz) Figure 17. THD + N Rev. D | Page 10 of 16 05028-027 THD + N (%) –60 05028-025 ATTENUATION (dB) –40 80 90 100 Data Sheet ADG884 TEST CIRCUITS IDS V1 S RON = V1/IDS 05028-012 VS D Figure 18. On Resistance IS (OFF) A S D ID (OFF) A VD 05028-013 VS Figure 19. Off Leakage D ID (ON) A VD 05028-014 S NC Figure 20. On Leakage VDD 0.1µF VDD VS VOUT D RL 50Ω IN 50% VIN 50% CL 35pF 90% VOUT 90% GND tON tOFF 05028-015 S1B S1A Figure 21. Switching Times, tON, tOFF VDD 0.1µF 50% VDD S1B S1A VS VIN VOUT D RL IN CL 35pF 80% 80% tBBM tBBM 05028-016 50Ω VOUT 50% 0V GND Figure 22. Break-Before-Make Time Delay, tBBM Rev. D | Page 11 of 16 ADG884 Data Sheet VDD SW OFF SW ON D VS VIN S1B NC S1A VOUT 1nF IN VOUT ∆VOUT GND 05028-017 QINJ = CL × ∆VOUT Figure 23. Charge Injection VDD 0.1µF 0.1µF NETWORK ANALYZER VDD S1A 50Ω 50Ω NETWORK ANALYZER VDD S1B VS 50Ω S1A VS D RL 50Ω GND OFF ISOLATION = 20 LOG VOUT RL 50Ω GND VOUT INSERTION LOSS = 20 LOG VS Figure 24. Off Isolation VOUT 05028-019 D 05028-018 S1B NC VDD VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 26. Bandwidth VDD 0.1µF VDD VOUT 50Ω D S1B 50Ω VS CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG RL 50Ω VS NC S2B 50Ω GND VOUT D2 S2A VS D1 S1A S1B CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG NC VOUT VS Figure 27. Channel-to-Channel Crosstalk (S1A to S2A) Figure 25. Channel-to-Channel Crosstalk (S1A to S1B) Rev. D | Page 12 of 16 50Ω 05028-021 RL 50Ω 05028-020 VOUT NETWORK ANALYZER S1A Data Sheet ADG884 TERMINOLOGY IDD Positive supply current. CD, CS (On) On switch capacitance. Measured with reference to ground. VD (VS) Analog voltage on Terminal D and Terminal S. CIN RON tON Delay time between the 50% and 90% points of the digital input and switch on condition. Digital input capacitance. Ohmic resistance between Terminal D and Terminal S. RFLAT (On) The difference between the maximum and minimum values of on resistance as measured on the switch. ΔRON On resistance match between any two channels. IS (Off) Source leakage current with the switch off. ID (Off) Drain leakage current with the switch off. ID, IS (On) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (Off) Off switch source capacitance. Measured with reference to ground. CD (Off) Off switch drain capacitance. Measured with reference to ground. tOFF Delay time between the 50% and 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection Measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Off Isolation Measure of unwanted signal coupling through an off switch. Crosstalk Measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance. −3 dB Bandwidth Frequency at which the output is attenuated by 3 dB. On Response Frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) Ratio of the harmonics amplitude plus noise of a signal to the fundamental. Rev. D | Page 13 of 16 ADG884 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 3.00 BSC SQ 0.50 BSC 10 6 PIN 1 INDEX AREA 1.74 1.64 1.49 EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 5 TOP VIEW 2.48 2.38 2.23 0.80 MAX 0.55 NOM 0.80 0.75 0.70 1 PIN 1 INDICATOR (R 0.20) 0.05 MAX 0.02 NOM SEATING PLANE 031208-B 0.20 REF Figure 28. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 1.10 MAX 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 29. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. D | Page 14 of 16 0.80 0.60 0.40 Data Sheet ADG884 0.63 0.57 0.51 SEATING PLANE 1.56 1.50 1.44 3 2 A 0.36 0.32 0.28 BALL 1 IDENTIFIER 1 2.06 2.00 1.94 B 0.50 BSC BALL PITCH C D (BALL SIDE DOWN) 0.11 0.09 0.07 BOTTOM VIEW (BALL SIDE UP) 081607-A 0.26 0.22 0.18 TOP VIEW Figure 30. 10-Ball Wafer Level Chip Scale Package [WLCSP] (CB-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG884BRMZ ADG884BRMZ-REEL ADG884BRMZ-REEL7 ADG884BCPZ-REEL ADG884BCPZ-REEL7 ADG884BCBZ-REEL ADG884BCBZ-REEL7 EVAL-ADG884EBZ 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Ball Wafer Level Chip Scale Package [WLCSP] 10-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. Branding on this package is limited to three characters due to space constraints. Rev. D | Page 15 of 16 Package Option RM-10 RM-10 RM-10 CP-10-9 CP-10-9 CB-10 CB-10 Branding 2 S9C S9C S9C S9C S9C S9C S9C ADG884 Data Sheet NOTES ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05028-0-4/12(D) Rev. D | Page 16 of 16