Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 April 2010 Reference Design RD1072 Introduction For systems using microprocessors or computers there are usually numerous power supplies. If a power supply fails the power manager circuits may, as a minimum, force a shutdown. For maintenance and troubleshooting it is very desirable to know which power supply failed and the type of failure condition (over-voltage or under-voltage). This reference design presents a solution that records the supply fault condition in non-volatile memory so the fault(s) can read back at a later time. This solution is fast, reliable, and cost effective because it is based on a Power Manager II, MachXO™ or LatticeXP2™ and non-volatile SPI Flash memory. Theory of Operation This fault logger reference design uses a Lattice Power Manager II device to monitor the voltage levels in the system. The Power Manager II device is designed to monitor and control different power supplies within a system and has an on-board analog-to-digital converter. The user can set high and low voltage alarm points within the device and these can then be used to initiate different control actions of the user’s choosing. For this design a voltage alarm will cause a fault status output to be driven high and the status of all the voltage monitor channels to be output on four data status lines. This design uses the ispPAC®-POWR1220AT8 Power Manager II device but could also be adapted to the ispPAC-POWR1014A device. The fault status output and the four data status lines are connected to a MachXO or LatticeXP2 device which then captures the fault data, formats it, and writes the formatted data to a SPI Flash memory for later retrieval. The sequence of events can be summarized as follows: 1. The ispPAC-POWR1220AT8 detects a fault on one or more of the VMON inputs and dumps the status of all the VMON inputs to the MachXO or LatticeXP2 device. 2. The dump of VMON status is implemented using supervisory logic equations and happens automatically using outputs and clock pins of the Power Manager II. 3. The MachXO or LatticeXP2 implements a receiver state machine to capture the VMON status. 4. The MachXO or LatticeXP2 adds a time stamp to the VMON status information, sends the commands and writes the data to a SPI Flash memory device. A block diagram of the Fault Logging Reference Design is shown in Figure 1. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 rd1072_01.0 Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Lattice Semiconductor Figure 1. Fault Logging Design Block Diagram Fault Detection and Dump ispPAC-POWR1220AT8 Fault Capture and Logger MachXO or LatticeXP2-5E OUT16 - PM_FLT0 Timer OUT17 - PM_FLT1 SS VMON 1-12 A&B VMON Status Dump State Machine OUT18 - PM_FLT2 OUT19 - PM_FLT3 OUT20 - PM_FLT4 VMON Status Capture State Machine SCLK SPI Write Status State Machine MOSI MISO SS SPI Memory 250kHz - PCLK M U X 8MHz - MCLK SS Sequencer & Supervisory Logic SCLK MOSI MISO SCLK MOSI MISO Arbitration Logic and Handshaking Reset SPI Full Busy Mem Clear Ready Microprocessor Interface Design Details Figure 3 shows the details of the VMON status dump from the Power Manager II to the MachXO or LatticeXP2 device and the transfer of data from the MachXO or LatticeXP2 device to the SPI Flash memory. The VMON status dump is generated within the Power Manager II device using an internal 250 KHz clock (fixed) which also drives the PCLK signal. The PCLK signal is used to drive the VMON Status Capture state machine inside the MachXO or LatticeXP2 device. As shown in Figure 1, the fault logging process is divided between two devices; the Power Manager II detects and dumps the faults to the CPLD that captures the faults. The CPLD then writes them to a standard non-volatile SPI memory. The CPLD also provides arbitration logic, a timer, and a MUX interface to the SPI memory for microprocessor support. The details of the CPLD design are presented in RD1092 Fault Logging Twelve Power Supplies using the MachXO. This document discusses the details of the Power Manager ispPAC-POWR1220AT8 design file RD1072_Fault_Logging.PAC, which is targeted for demonstration on the Power Manager Hercules Evaluation Board. The heart of this design is contained in the supervisory logic equations in the LogiBuilder window of PACDesigner® (see Listing 2). One set of equations is used to implement a three-bit binary up-counter and the second set of equations is used to dump all the VMON status values to the CPLD. When the counter is active the four-bit bus of output pins is updated with the VMON status values on the rising edge of the PLD clock (250 kHz). The rising edge of the fifth output (OUT20_PM_FLT4) is used to trigger the CPLD to capture the VMON status. 2 Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Lattice Semiconductor Equations 0 to 6 implement a three-bit binary up-counter. This counter is reset to a value of 3 and then counts up using the sequence; 4, 5, 6, 7, 0, and 1 at the rate of the PLD clock. The counter is enabled when NODE7 (named DUMP_FAULTSn) is set low in the main sequence (see Listing 1). When the counter reaches a value of 2 it sets DUMP_FAULTSn high which resets the counter and prevents multiple status dumps. A key element to this design is the flag or internal signal DUMP_FAULTSn. It is through this signal that the main sequence tells the equations to dump the VMON status. This node is named using the Pin Definition dialog (see Figure 2) from LogiBuilder’s PINS window. In this design the main sequence monitors VMON9 (the slide potentiometer on the Power Manager Hercules Evaluation Board) and sets DUMP_FAULTSn low if the voltage is in error. Figure 2. Naming NODE7 in the PINS Window Equations 7 to 11 decode the three-bit binary counter and combine the VMON status to provide the fault reporting to the fault logging device. Equations 7 to 10 are combinatorial and provide a four-bit data bus to the CPLD with the VMON status. Each OR branch of the equation decodes the counter value and combines a unique VMON status so that all 24 VMON status are transferred to the CPLD in six PLD clocks (24 µs). The CPLD uses the negative edge of the PLD_CLK to latch the four VMON status presented on the four-bit bus (see Figure 3). Equation 11 simply maps the most significant bit of the counter (Cntr2) to the output OUT20_PM_FLT4. This output transitions from low to high to trigger the CPLD to capture the status dump. The status dump and binary counter are shown in Figure 3 with the PLD_Clock. The main sequence (see Listing 1) is a very simple monitoring loop. Steps 0 to 1 start-up and initialize the Power Good LED in the off state and reset the DUMP_FAULTSn flag. Steps 2 to 6 monitor the status of VMON9 to control the Power Good LED and the DUMP_FAULTSn flag. When VMON9 is between the trip points the Power Good LED is on. When VMON9 is outside the windowed trip points, the Power Good LED is off and the DUMP_FAULTSn flag is activated. In the Analog Input Settings dialog (from the main schematic window) VMON9 is configured in Window mode with the lower trip point of 2.0V and the upper trip point of 3.0V. On the Power Manager Hercules Evaluation Board VMON9 is connected to the slide potentiometer to simulate either an under or over voltage situation. This design is easily modified to include any number of other VMON or input conditions to trigger the fault dump by adding to the Boolean logic in Step 4. Other sequences and controls could also be added before Step 2 based on the design requirements. 3 Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Lattice Semiconductor Normally, the Logical Signal Name for VMON9_A would be renamed to indicate the signal source and the window mode of operation such as VM9_SLIDE_POT_OK. However, this was not done in this design for two reasons. First is so that all the documentation uses the same signal name to clarify the concept. Secondly, to highlight the design flow used. Normal design flow suggests naming the inputs and outputs before starting on the sequence or supervisory logic equations. However, this particular design can be entered faster and with less chance for error by copying the equations from the Boolean_EQ.txt file and pasting them into the equations dialog box. After the equations are entered the Logical Signal Names can be edited and the Sequence and Equations will automatically be updated. For convenience, RD1092, Fault Logging Twelve Power Supplies using the MachXO, uses the 8 MHz MCLK signal from the Power Manager II to drive the SPI memory write operations. (The MCLK signal from the Power Manager II is a fixed rate clock.) A user design could use a faster clock signal if desired. The entire operation takes less than 100 microseconds to store the fault record to the SPI Flash memory as shown in Figure 3. Figure 3. Waveform Diagrams of Fault Logging Design Fault Logging Status Dump Waveforms 24 us 250kHz - PCLK PM_FLT0 VMON1A VMON1B VMON2A VMON2B VMON3A VMON3B VMON4A VMON4B VMON5A VMON5B VMON6A VMON6B VMON7A VMON7B VMON8A VMON8B VMON9A VMON9B VMON10A VMON10B VMON11A VMON11B VMON12A VMON12B PM_FLT1 PM_FLT2 PM_FLT3 Internal D^Ctr2 & PM_FLT4 Internal D^Ctr0 Internal D^Ctr1 Count Value 4 5 6 7 0 1 2 Fault Logging SPI Page Program Waveforms 15 us 25 us SS MOSI (104 Bits) WREN PP Ins. 24-Bit Adx 8 Bytes 8 MHz - SCLK Internal PP Delay 4 Data Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Lattice Semiconductor Listing 1. LogiBuilder Sequence // Reset, turn off Power Good LED and reset Fault Dump flag. Step 0 Wait for AGOOD OUT15_PWR_GOOD = 1, DUMP_FAULTSn = 1 // Optional additional startup delay. Step 1 Wait for 15.36ms using timer 1 // Wait for VMON9 to be more than 2V and less than 3V // VMON9 is the slide potentiometer on the Hercules Demo Board. Step 2 Wait for VMON9_A // Turn on the Power Good LED Step 3 OUT15_PWR_GOOD = 0, // Wait for VMON9 to be less than 2V or more than 3V // a fault condition. Step 4 Wait for NOT VMON9_A // Turn off Power Good LED and start the Fault Dump. Step 5 OUT15_PWR_GOOD = 1, DUMP_FAULTSn = 0, // Return to monitoring VMON9. Step 6 Go to step 2 // A shutdown sequence is not used in this design. Step 7 Begin Shutdown Sequence Step 8 Halt (end-of-program) Listing 2. Supervisory Logic Equations // // EQ EQ EQ Equations 3 – 8 provide a three-bit binary up-counter that is enabled by DUMP_FAULTSn. 0 Cntr0.D = NOT Cntr0 1 Cntr1.D = ( Cntr0 AND NOT Cntr1 ) OR ( NOT Cntr0 AND Cntr1 ) 2 Cntr2.D = ( NOT Cntr2 AND Cntr0 AND Cntr1 ) OR ( Cntr2 AND NOT ( Cntr0 AND Cntr1 ) ) // // // EQ EQ EQ The binary counter is reset to a count of 3 when the DUMP_FAULTSn flag is true and counts 4,5,6,7,0,1,2 when the flag is low. 3 Cntr0.ap = DUMP_FAULTSn 4 Cntr1.ap = DUMP_FAULTSn 5 Cntr2.ar = DUMP_FAULTSn // // // EQ Equation 6 automatically sets DUMP_FAULTSn high to reset the binary counter; after the VMON status bits have been dumped (at the count of 2). 6 DUMP_FAULTSn.ap = NOT Cntr0 AND Cntr1 AND NOT Cntr2 // Equations 7 – 10 are combinatorial logic that decode the counter // value to select the VMON status to output. The four bits of VMON // status are updated on the rising edge of PLD_CLK. 5 Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Lattice Semiconductor // VMON1 – VMON3 status EQ 7 OUT16_PM_FLT0 = ( VMON1_A OR ( VMON1_B OR ( VMON2_A OR ( VMON2_B OR ( VMON3_A OR ( VMON3_B bits are decoded to fault bit zero. // VMON4 – VMON6 status EQ 8 OUT17_PM_FLT1 = ( VMON4_A OR ( VMON4_B OR ( VMON5_A OR ( VMON5_B OR ( VMON6_A OR ( VMON6_B bits are decoded to fault bit one. // VMON7 – VMON9 status EQ 9 OUT18_PM_FLT2 = ( VMON7_A OR ( VMON7_B OR ( VMON8_A OR ( VMON8_B OR ( VMON9_A OR ( VMON9_B bits are decoded to fault bit two. AND NOT Cntr0 AND NOT Cntr1 AND Cntr0 AND NOT Cntr1 AND NOT Cntr0 AND Cntr1 AND Cntr0 AND Cntr1 AND NOT Cntr0 AND NOT Cntr1 AND Cntr0 AND NOT Cntr1 AND NOT Cntr0 AND NOT Cntr1 AND Cntr0 AND NOT Cntr1 AND NOT Cntr0 AND Cntr1 AND Cntr0 AND Cntr1 AND NOT Cntr0 AND NOT Cntr1 AND Cntr0 AND NOT Cntr1 AND NOT Cntr0 AND NOT Cntr1 AND Cntr0 AND NOT Cntr1 AND NOT Cntr0 AND Cntr1 AND Cntr0 AND Cntr1 AND NOT Cntr0 AND NOT Cntr1 AND Cntr0 AND NOT Cntr1 // VMON10 – VMON12 status bits are decoded EQ 10 OUT19_PM_FLT3 = ( VMON10_A AND NOT Cntr0 AND OR ( VMON10_B AND Cntr0 AND OR ( VMON11_A AND NOT Cntr0 AND OR ( VMON12_B AND Cntr0 AND OR ( VMON12_A AND NOT Cntr0 AND OR ( VMON12_B AND Cntr0 AND // // // // // // EQ AND Cntr2 ) AND Cntr2 ) AND Cntr2 ) AND NOT Cntr2 ) AND NOT Cntr2 ) AND NOT Cntr2 ) AND Cntr2 ) AND Cntr2 ) AND Cntr2 ) AND NOT Cntr2 ) AND NOT Cntr2 ) AND NOT Cntr2 ) AND Cntr2 ) AND Cntr2 ) AND Cntr2 ) AND NOT Cntr2 ) AND NOT Cntr2 ) AND NOT Cntr2 ) to fault bit three. NOT Cntr1 AND Cntr2 ) NOT Cntr1 AND Cntr2 ) Cntr1 AND Cntr2 ) Cntr1 AND NOT Cntr2 ) NOT Cntr1 AND NOT Cntr2 ) NOT Cntr1 AND NOT Cntr2 ) Equation 11 is also combinatorial but only outputs the value of the most significant bit of the counter. The rising edge of this output is used to trigger the CPLD to capture the VMON status and thus the faults. Based on the simple logic; Cntr2 is optimized by the fitter to OUT20_PM_FLT4. So the Cntr2 signal is missing from the simulation and fitter report. 11 OUT20_PM_FLT4 = Cntr2 Simulation and Verification The simulation of this design is done using a reduced value for Timer1 for faster and smaller simulation files. The timer value is changed from 15.3 ms to 104 µs. Figure 4 shows the simulation result for an under-voltage fault and Figure 5 shows the simulation result for an over-voltage fault. 6 Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Lattice Semiconductor Figure 4. VMON9 Under-Voltage Simulation Fault Dump Figure 5. VMON9 Over-Voltage Fault Dump Simulation 7 Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Lattice Semiconductor Implementation Performance and Resource Utilization Device Macrocells Product Terms ispPAC-POWR1220AT81 17 80 VMONs 2 1 In Out HVOUT Timers 0 5 0 1 1. Resource utilization characteristics are generated using PAC-Designer 5.2 software. When using this design in a different device, utilization characteristics may vary. 2. All 12 VMONs status are captured in this design but, none are dedicated to this design. All are free to be used at the designer’s needs and discretion. VMON9 is used as an example in this design and to be compatible with the Power Manager Hercules Evaluation Board. References • ispPAC-POWR1220AT8 Data Sheet • MachXO Family Data Sheet • LatticeXP2 Family Data Sheet Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version April 2010 01.0 Change Summary Initial release. 8 A B C IN1 +5V_HS Mon_Ext_12V_Current Mon_Ext_12V_In +3.3V_HS J5 HEADER 3 4 3 1 2 5 HEADER 3 J6 SW3 IN1 IN1 PM_TDO PM_TDI PM_TMS PM_TCK Over_Current_12V PM_IN3 PM_IN4 Mon_12V_In Mon_12V_HS Mon_12V_Current VMON9 VMON8 VMON7 Mon_5V_Current Mon_Input 5V Mon_3V_Current +1.2V_SEQ_SENSE +1.2V_SEQ_GS VMON2 VMON2_GS Mon_Input 3V XO_PWR0 XO_PWR1 C7 0.1uF 4 34 31 28 37 30 32 97 1 2 4 6 7 47 46 50 48 52 51 54 53 56 55 58 57 62 61 64 63 66 65 68 67 70 69 72 71 89 90 C11 0.1uF TDO TDI TMS TCK ATDI TDISEL IN1 IN2 IN3 IN4 IN5 IN6 VMON1 VMON1GS VMON2 VMON2GS VMON3 VMON3GS VMON4 VMON4GS VMON5 VMON5GS VMON6 VMON6GS VMON7 VMON7GS VMON8 VMON8GS VMON9 VMON9GS VMON10 VMON10GS VMON11 VMON11GS VMON12 VMON12GS VPS0 VPS1 U2 ispPAC-POWR1220AT8 C14 0.1uF C23 0.1uF 3 XO_PWR2 XO_PWR3 GNDD XO_PWR[0:3] GNDD 22 D PWR_3.3V 36 4 5 VCCINP GNDD 5 33 VCCJ 43 94 GNDD 1 2 3 39 VCCPROG 88 38 GNDD 1 2 3 60 VCCA 98 13 VCCD GNDD VCCD GNDA VCCD GNDA 45 9 87 C24 0.1uF 3 RESETb SCL SDA PLDCLK MCLK OUT5_SMBA OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 HVOUT1 HVOUT2 HVOUT3 HVOUT4 TRIM1 TRIM2 TRIM3 TRIM4 TRIM5 TRIM6 TRIM7 TRIM8 3 PM_SCL PM_SDA 92 93 PWR_3.3V PM_PLDCLK PM_MCLK 95 96 C17 0.1uF 91 PM_SMBA Enable_1_2V Enable_2_5V Enable_3_3V Ext_LowCurrent_EN LowCurrent_EN Shut_12V_Down PRI_12V_OR EXT_12V_OR cPCI_12V_EN PWR_GOOD PM_FLT0 PM_FLT1 PM_FLT2 PM_FLT3 PM_FLT4 Charge_Pump HVOUT2 HotSwap_3V HotSwap_5V Trim_1.2V Trim2 8 9 10 11 12 14 15 16 17 18 19 20 21 23 24 25 86 85 42 40 84 83 82 80 79 75 74 73 PWR_3.3V 2 2 2 Green R19 1k Date: Size B 2 R85 1k 3 VMON9 31 March 2010 Project Hercules Demo Board 1 Sheet A A Schematic Rev Board Rev 2 of 12 TDO_LED 2.2k 4 RN5D 2.2k RN5C Lattice Semiconductor Applications Email: [email protected] Phone (503) 268-8001 -or- (800) LATTICE 1 3 Title Power Manager 1220AT8 Fault Logging Interface Sheet 6 PWR_3.3V 2.2k 2.2k D9 RN5B RN5A PWR_GOOD 1 10 PWR_3.3V 1 A B C D Lattice Semiconductor Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Appendix A. Schematic Figure 6. Power Manager ispPAC-POWR1220AT8 10 A B C D 8MHz PM_MCLK Fault Logging Interface Sheet 2 PWR_3.3V 5 4 3 1 2 75 73 PM_FLT1 PM_FLT0 SW4 XO_SW PWR_3.3V PT4D PT4A PT4B PT3F PT3D PT3A PT3B PT2E PT2F PT2C PT2D PT2A PT2B BANK 0 4 4 C4 0.1uF VCCIO0 VCCIO0 PT9E PT9F PT9C PT9D PT9A PT9B PT8C PT8A PT8B PT7E PT7C PT7A PT6A PCLKT0_1/PT6B PT5C PCLKT0_0/PT5B (2 OF 3) LCMX2280-T144/TN144 VCCIO1 VCCIO1 PB11C PB11D PB11A PB11B PB10C PB10D PB10A PB10B PR9D PR9A PR8C PR8A PR7D PR7A PR7B PR6C PR6D PR5D PR5B PR4D PR4A PR4B PR3C PR3D PR3A PR3B PR2C PR2D PR2A PR2B BANK 1 U3B XO_SW 98 82 77 74 80 78 PM_FLT3 PM_FLT2 81 AD21 AD22 AD23 79 76 84 AD20 92 91 AD13 AD14 85 94 AD12 86 95 AD11 AD19 96 AD10 AD18 100 97 AD8 AD9 87 102 101 AD6 AD7 AD17 105 103 AD4 AD5 90 89 107 104 AD1 AD3 AD15 AD16 108 106 AD0 AD2 PM_PLDCLK PM_FLT4 5 C12 0.1uF PWR_3.3V C19 0.1uF SPI[0:3] XO_LED[0:3] C27 0.1uF USB_UART_TX USB_UART_CTS 111 109 C18 0.1uF USB_UART_RX USB_UART_RTS 113 110 XO_PWR[0:3] cPCI_RST cPCI_INTA 135 117 cPCI_IDSEL 114 112 cPCI_STOP cPCI_DEVSEL cPCI_IRDY cPCI_TRDY cPCI_FRAME cPCI_PAR cPCI_CLK cPCI_CBE3 cPCI_CBE2 cPCI_CBE0 cPCI_CBE1 115 119 116 120 121 122 125 124 126 127 130 132 131 cCPI_BD_SEL cCPI_HEALTHY 133 3 C28 0.1uF cPCI_SCL cPCI_SDA cPCI_RDY USB_SDA USB_SCL PM_SMBA XO_SW XO_SPARE C29 0.1uF 10 26 34 36 32 35 31 33 29 30 25 28 24 22 23 19 20 17 18 15 13 14 12 9 7 8 4 6 2 5 1 3 C20 0.1uF PWR_3.3V PWR_3.3V SPI2 SPI3 SPI0 SPI1 XO_LED2 XO_LED3 XO_LED0 XO_LED1 XO_PWR2 XO_PWR3 XO_PWR0 XO_PWR1 VID_6 VID_7 AD30 AD31 PM_SCL VID_4 VID_5 AD28 AD29 PM_SDA VID_2 VID_3 VID_0 VID_1 AD26 AD27 AD24 AD25 134 139 137 141 138 143 140 144 142 AD[0:31] 3 2 PB4C PB4D PB4A PB4B PB3C PB3D PB3A PB3B PB2C BANK 2 Date: Size B LCD_1 LCD_21 LCD_2 LCD_20 LCD_3 LCD_19 44 45 46 48 49 50 38 63 72 68 71 67 69 65 66 62 61 60 57 58 56 1 31 March 2010 1 Sheet Lattice Semiconductor Applications Email: [email protected] Phone (503) 268-8001 -or- (800) LATTICE PWR_3.3V LCD_11 LCD_13 LCD_12 LCD_9 LCD_10 LCD_8 LCD_14 LCD_15 LCD_7 LCD_16 LCD_17 LCD_6 LCD_5 LCD_4 LCD_18 LCD_0 LCD_22 54 55 LCD_23 40 41 43 Project Hercules Demo Board Title MachXO I/O VCCIO2 VCCIO2 PB9F PB9C PB9D PB9A PB9B PB8C PB8D PB8A PB7E PB7C PB6A PCLKT2_0/PB6B PB5D PB5A PCLKT2_1/PB5B (1 OF 3) VID_[0:7] LCMXO640-T144/TN144 VCCIO3 VCCIO3 PL11C PL11D PL11A PL11B PL10C PL10D PL10A PL10B PL9C PL9D PL8C/TSALL PL8A PL8B PL7A PL7B PL6C PL6D PL5D PL5A PL5B/GSRN PL4D PL4A PL3C PL3D PL3A PL3B PL2C PL2D PL2A PL2B BANK 3 U3A 2 A A Schematic Rev Board Rev of 12 6 LCD_[0:23] A B C D Lattice Semiconductor Voltage Monitoring for Fault Logging with ispPAC-POWR1220AT8 Figure 7. MachXO I/O