Clock Generation Selector Guide

Clock Generation Selector Guide
Universal Clock Generators simplify traditional board design by synthesizing frequencies from a reference input clock or a common low cost crystal providing low jitter output clocks. When used
together with Microsemi® Clock Distribution Fanout Buffers provide customers an improved board performance and complete timing solutions.
Clock Synthesis Devices
# Independent
Output
Frequency
Families
# Inputs
Crystal Input
Freq. Range
Xtal Osc. or
CMOS Input
Freq. Range
Diff Input
Freq. Range
# LowJitter
APLLs
Typical
Jitter
fs RMS
NCO
Mode
NCO
ppb
# Diff
Outputs
ZL30236
2
1 xtal
20M-24.576M
–
–
2
700
–
–
8
ZL30237
2
1 xtal
20M-24.576M
–
–
2
700
Y
0.24
ZL30230
4
1 xtal
20M-24.576M
–
–
2
700
–
–
MAX24405
2
1xtal/SE, 3D/SE
25M-52M
9.72M-160M
9.72M-750M
2
1801
–
–
MAX24505
2
1xtal/SE, 3D/SE
25M-52M
9.72M-160M
9.72M-750M
2
180
1
–
MAX24410
2
1xtal/SE, 3D/SE
25M-52M
9.72M-160M
9.72M-750M
2
180
1
MAX24510
2
1xtal/SE, 3D/SE
25M-52M
9.72M-160M
9.72M-750M
2
1801
ZL30250
1
1xtal/SE, 3D/SE
25M-60M
9.72M-300M
9.72M-1250M
1
ZL30251
1
1xtal/SE, 3D/SE
25M-60M
9.72M-300M
9.72M-1250M
ZL30244
2
2xtal/SE, 6D/SE
25M-60M
9.72M-300M
ZL30245
2
2xtal/SE, 6D/SE
25M-60M
9.72M-300M
Abbreviation Key:
D = Differential
SE = Single-Ended (CMOS)
1 = Integer-Mode APLL only Operation
Part #
#CMOS Output Freq.
Outputs
Range
NV
Memory
Host
Bus
Supply
Voltage
Pkg Size,
mm
4
1K-750M
OTP
SPI/I2C
3.3+1.8
11x11
8
4
1K-750M
OTP
SPI/I2C
3.3+1.8
11x11
4-12
4-12
1K-750M
OTP
SPI/I2C
3.3+1.8
11x11
0-5
0-10
<1Hz-750M
Ext EE
SPI
3.3+1.8
10x10
–
0-5
0-10
<1Hz-750M
Int EE
SPI
3.3+1.8
10x10
–
–
0-10
0-20
<1Hz-750M
Ext EE
SPI
3.3+1.8
10x10
–
–
0-10
0-20
<1Hz-750M
Int EE
SPI
3.3+1.8
10x10
1601
Y
0.01
0-3
0-6
<1Hz-1035M2
Ext EE3
SPI/I2C
3.3+1.8
5x5
1
160
1
Y
0.01
0-3
0-6
<1Hz-1035M
2
3
Int EE
SPI/I2C
3.3+1.8
5x5
9.72M-1250M
2
160
1
Y
0.01
0-6
0-12
<1Hz-1035M
2
3
Ext EE
SPI/I2C
3.3+1.8
5x10
9.72M-1250M
2
1601
Y
0.01
0-6
0-12
<1Hz-1035M2
Int EE3
SPI/I2C
3.3+1.8
5x10
NCO = Numerically Controlled Oscillator
2 = Spread Spectrum Capable
Ext EE = External EEPROM
Int EE = Internal EEPROM
3 = Upto Four Configurations Pin-Selectable
OTP = One-Time Programmable
Clock Generation Selector Guide
Rate Conversion / Jitter Attenuation Devices
Part #
# Independent
Output
Frequency
Families
# Inputs
2
1xtal/SE, 3D/SE
25M-52M
2KHz-160M
2KHz-750M
2
1801
Glitchless /
Digital Hold /
4Hz-400Hz
Y
<0.001
0-5
0-10
<1Hz-750M
Ext EE
SPI
3.3+1.8
10x10
2
1xtal/SE, 3D/SE
25M-52M
2KHz-160M
2KHz-750M
2
1801
Glitchless /
Digital Hold /
4Hz-400Hz
Y
<0.001
0-10
0-20
<1Hz-750M
Ext EE
SPI
3.3+1.8
10x10
1
1 xtal, 1D
20M or
24.578M
1Hz-177.5M
1Hz-750M
1
<1000
-
N
–
0
2
<1Hz-177.5M
–
SPI/I2C
3.3+1.8
9x9
1
1xtal/SE, 3D/SE
25M-60M
1kHz-300M
1kHz-1250M
1
1601
Glitchless /
Digital Hold /
14Hz-500Hz
Y
0.01
0-3
0-6
<1Hz-1035M2
Ext EE3
SPI/I2C
3.3+1.8
5x5
1
1xtal/SE, 3D/SE
25M-60M
1kHz-300M
1kHz-1250M
1
1601
Glitchless /
Digital Hold /
14Hz-500Hz
Y
0.01
0-3
0-6
<1Hz-1035M2
Int EE3
SPI/I2C
3.3+1.8
5x5
1
1xtal, 2SE
49.152MHz
8kHz or
25MHz
-
1
<1ps
Glitchless /
Digital Hold /
25Hz
N
–
2
0
125MHz or
156.25MHz
–
None
3.3+1.8
5x5
2
2xtal/SE, 6D/SE
25M-60M
1kHz-300M
1kHz-1250M
2
1601
Glitchless /
Digital-Hold /
14Hz-500Hz
Y
0.01
0-6
0-12
<1Hz-1035M2
Int EE3
SPI/I2C
3.3+1.8
5x10
MAX24605
MAX24610
ZL30159
ZL30252
ZL30253
ZL30254
ZL30255
Abbreviation Key:
DPLL Features:
Xtal Osc. or
# Low- Typical
Crystal Input
Diff Input
Ref. Switching/ NCO
CMOS Input
Jitter
Jitter
Freq. Range
Freq. Range
Holdover/
Mode
Freq. Range
APLLs fs RMS
Bandwidth
D = Differential SE = Single-Ended (CMOS)
1 = Integer-Mode APLL only Operation
NCO = Numerically Controlled Oscillator
2 = Spread Spectrum Capable
NCO
ppb
# Diff #CMOS Output Freq.
NV
Outputs Outputs
Range
Memory
Ext EE = External EEPROM Int EE = Internal EEPROM
3 = Upto Four Configurations Pin-Selectable
Host
Bus
Supply Pkg Size,
Voltage
mm
OTP = One-Time Programmable
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sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
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