7809ALP - ADC, 16 bit, 100 kSPS, Serial

7809ALP
16-Bit Latchup Protected
Analog to Digital Converter
R/C
CS
POWER DOWN
Successive Approximation Register and Control Logic
Clock
CDAC
20 kΩ
R1IN
BUSY
10 kΩ
R2IN
5 kΩ
Comparator
R3IN
20 kΩ
Serial Data
Out
Data
Clock
Serial
Data
CAP
Buffer
4 kΩ
Internal
+2.5V Ref.
REF
Memory
Logic Diagram
FEATURES:
DESCRIPTION:
• RAD-PAK® radiation-hardened against natural space
radiation
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Latch-up Protection Technology (LPTTM)
• SEL converted into a reset
- Rate based on cross section and mission
• Package: 24 pin RAD-PAK flat package
• 100 kHz min sampling rate
• ±10 V and 0 V to 5 V input range
• DNL: 15-bits “No Missing Codes”
• 83 dB min SINAD with 20 kHz input
• Single +5 V supply operation
• Utilizes internal or external reference
• Serial output
• Power dissipation: 132 mW max
Maxwell Technologies’ 7809ALP high-speed 16-bit analog to
digital converter features a greater than 100 kilorad (Si) total
dose tolerance depending upon space mission. Using Maxwell’s radiation-hardened RAD-PAK® packaging technology is
latchup protected by Maxwell Technologies’ Latchup Protection Technology (LPTTM). It is a 24 pin, 16-bit sampling analogto-digital converter using state-of-the-art CMOS structures.
The 7809ALP contains a 16-bit capacitor based SAR A/D with
S/H, reference, clock, interface for microprocessor use, and
serial output drivers. The 7809ALP is specified at a 100kHz
sampling rate, and guaranteed over the full temperature
range. Laser-trimmed scaling resistors provide various input
ranges include ±10 V and 0 to 5 V, while the innovative design
allows operation from a single +5 V supply, with power dissipation of under 132 mW.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK® provides greater than 50
krad (Si) radiation dose tolerance. This product is available
with screening up to Maxwell Technologies’ self-defined Class
K.
09.03.15 Rev 2
(858) 503-3300- Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice
1
©2015 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 1. 7809ALP PIN DESCRIPTION
PIN
SYMBOL
LPT PROTECTION
DESCRIPTION
1
R1IN
Not Protected
2
AGND1
N/A
3
R2IN
Not Protected
Analog Input.
4
R3IN
Not Protected
Analog Input.
5
CAP
Not Protected
Reference Buffer Capacitor. 2.2 µF tantalum to ground.
6
REF
Not Protected
Reference Input/Output. 2.2 µF tantalum capacitor to ground.
7
AGND2
N/A
8
SB/BTC
Not Protected
Select Straight Binary or Binary Two’s Complement data output format. If
HIGH, data will be output in a Straight Binary format. If LOW, data will be output
in a Binary Two’s Complement format.
9
EXT/INT
Not Protected
Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If LOW, a convert command
will initiate the transmission of the data from the previous conversion, along
with 16 clock pulses output on DATACLK.
10
DGND
N/A
11
LPBIT
Not Protected
Built In test function of the latchup protection. Drive LOW during normal operation.
12
LPSTATUS
Not Protected
Latchup Protection Status Output. LPSTATUS when HIGH indicates latchup
protection is active and output data is invalid.
13
VDIG
Protected
Digital Supply Input. Nominally 5V.
14
VANA
Protected
Analog Supply Input. Nominally 5V.
15
SYNC
Not Protected
Sync Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a
falling edge on CS with R/C HIGH will output a pulse on SYNC synchronized to
the external DATACLK.
16
DATACLK
Protected
Either an input or an output depending on the EXT/INT level. Output data will
be synchronized to this clock. If EXT/INT is LOW, DATACLK will transmit 16
pulses after each conversion, and then remain LOW between conversions.
17
DATA
Not Protected
Serial Data Output. Data will be synchronized to DATACLK, with the format
determined by the level of SB/BTC. In the external clock mode, after 16-bits of
data, the 7809LOPO will output the level input of TAG as long as CS is LOW
and R/C is HIGH. If EXT/INT is LOW, data will be valid on both the rising and
falling edges of DATACLK, and between conversions DATA will stay at the level
of the TAG input when the conversion was started.
18
TAG
Protected
Analog Input.
Analog Ground. Used internally as ground reference point.
Analog Ground.
Tag input for use in external clock mode. If EXT/INT is HIGH, the digital data
input on TAG will be output on DATA with a delay of 16 DATACLK pulses as
long as CS is LOW and R/C is HIGH.
09.03.15 Rev 2
All data sheets are subject to change without notice
2
©2015 Maxwell Technologies
All rights reserved.
Memory
Digital Ground.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 1. 7809ALP PIN DESCRIPTION
PIN
SYMBOL
LPT PROTECTION
DESCRIPTION
19
R/C
Protected
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. When EXT/INT is LOW, this
also initiates the transmission of the data results from the previous conversion.
If EXT/INT is HIGH, a rising edge on R/C with CS LOW, or a falling edge on CS
with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
20
CS
Protected
Chip Select. Internally OR’ed with R/C.
21
BUSY
22
PWRD
Protected
Power Down Input. If HIGH, conversions are inhibited and power consumption
is significantly reduced. Results from the previous conversions are maintained
in the output shift register.
23
LPVANA
Protected
Latchup Protected Analog Supply.
24
LPVDIG
Protected
Latchup Protected Digital Supply.
Busy Output. Falls when a conversion is started, and remains LOW until the
conversion is completed and the data is latched into the output shift register.
CS or R/C must be HIGH when BUSY rises, or another conversion will start
without time for signal acquisition.
Memory
TABLE 2. 7809ALP ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNIT
Analog Inputs
R1IN
R2IN
R3IN
CAP
REF 1
-25
-25
-25
VANA + 0.3
25
25
25
AGND2 - 0.3
V
V
V
V
-0.3
0.3
V
--
7
V
7
V
Ground Voltage Differences: DGND, AGND2
VANA
VDIG
VDIG to VANA
--
0.3
V
Digital Inputs
-0.3
VDIG + 0.3
V
--
7.8
Grams
Weight
Thermal Resistance
TJC
--
7.3
°C/W
Operating Temperature2
TOPE
-35
+85
°C
Storage Temperature
TSTG
-65
150
°C
1. Indefinite short to AGND2, momentarily short to VANA.
2. Minimum Temperature is -40°C when using with an external reference.
09.03.15 Rev 2
All data sheets are subject to change without notice
3
©2015 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 3. 7809ALP DC ACCURACY SPECIFICATIONS
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
PARAMETER
SUBGROUPS
MIN
TYP
MAX
UNIT
1, 2, 3
--
--
±7
LSB 1
1
2, 3
---
---
-2, 3
-1, 6
LSB
LSB
No Missing Codes 2
15
--
--
Bits
Transition Noise 3
--
1.3
--
LSB
--
±0.8
%
±0.8
%
Integral Linearity Error
Differential Linearity Error
-35 to 85°C (Internal Reference); -40 to 85°C (External Reference
1, 2, 3
--
Full Scale Error 4,5 (using ext. 2.5000 Vref)
1, 2, 3
--
--
--
±7
--
ppm/°C
Full Scale Error Drift (using ext. 2.5000 Vref)
1, 2, 3
--
±2
--
ppm/°C
Bipolar Zero Error 4
1, 2, 3
--
--
±12
mV
--
±2
--
ppm/°C
---
---
±3
±16
mV
mV
Unipolar Zero Error Drift
--
±2
--
ppm/°C
Recovery to Rated Accuracy after Power Down (1 uF Capacitor
to CAP)
--
1
--
ms
---
---
±8
±32
LSB
LSB
Full Scale Error Drift
Bipolar Zero Error Drift
Unipolar Zero Error 4
-35 to 85°C (Internal Reference); -40 to 85°C (External Reference
Power Supply Sensitivity (VDIG = VANA = VD) 4.75 V < VD < 5.2 V
-35 to 85°C (Internal Reference); -40 to 85°C (External Reference
1
2, 3
1
2, 3
Memory
Full Scale Error 4,5
1. LSB stands for Least Significant Bit. One LSB is equal to 305 µV.
2. Not tested.
3. Typical rms noise at worst case transitions and temperatures.
4. Measured with various fixed resistors.
5. For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and
last scale code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset
error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It
also includes the effect of offset error.
TABLE 4. DELTA LIMITS1
PARAMETER
VARIATION
ICC
+/- 10%
09.03.15 Rev 2
All data sheets are subject to change without notice
4
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All rights reserved.
7809ALP
16-Bit Latchup Protected Analog to Digital Converter
TABLE 5. 7809ALP ANALOG INPUT AND THROUGHPUT SPEED
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
PARAMETER
SUBGROUPS
Voltage Ranges
1, 2, 3
Impedance
1, 2, 3
Capacitance1
Conversion Time
Complete Cycle (Acquire and Convert)
Throughput Rate
1. Guarenteed by design.
2
MIN
TYP
MAX
UNIT
10 V, 0 V to 5 V, etc.
See Table 12.
--
35
--
pF
9, 10, 11
--
7.6
8
µs
9, 10, 11
--
--
10
µs
9, 10, 11
--
--
100
kHz
2. Tested by application of signal.
Memory
TABLE 6. 7809ALP AC ACCURACY SPECIFICATIONS
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
PARAMETER
SUBGROUPS
MIN
TYP
MAX
UNIT
Spurious-Free Dynamic Range, fIN = 20 kHz 1
4, 5, 6
90
100
--
dB 2
Total Harmonic Distortion, fIN = 20 kHz 1
4, 5, 6
--
-100
-90
dB
Signal-to-Noise (Noise + Distortion)
fIN = 20 kHz
-60 dB Input
4, 5, 6
83
--
88
30
---
Signal-to-Noise 1, fIN = 20 kHz
83
88
--
dB
Full-Power Bandwidth
--
250
--
kHz
1
1,3
dB
1. Guaranteed by design.
2. All specifications in dB are referred to a full-scale ±10 V input.
3. Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 60 dB.
TABLE 7. 7809ALP SAMPLING DYNAMICS
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
PARAMETER
SUBGROUPS
Aperture Delay
Aperture Jitter
MIN
TYP
MAX
UNIT
--
40
--
ns
9, 10, 11
Sufficient to meet AC specification
Transient Response FS Step
--
2
--
us
Overvoltage Recovery
--
150
--
ns
1
1. Recovers to specified performance after 2 X FS input overvoltage.
09.03.15 Rev 2
All data sheets are subject to change without notice
5
©2015 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 8. 7809ALP REFERENCE
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Internal Reference Voltage1
No Load
2.48
2.5
2.52
V
Internal Reference Source Current (Must be
ext. buffer)
--
1
--
µA
External Reference Voltage Range for Specified Linearity 2
2.3
2.5
2.7
V
--
--
175
µA
External Reference Current Drain
Ext. 2.5000V Ref
1. Tested from -35C to +85C
2. Tested by application of signal.
PARAMETER
SUBGROUPS
Data Format
Data Coding
Pipeline Delay
CONDITIONS
MIN
TYP
MAX
UNIT
Serial 16-bits
Binary Two’s Complement or Straight Binary
Conversion results only available after completed conversion
Selectable for internal or external data clock
Data Clock
Internal (Output Only When
9, 10, 11
EXT/INT Low
-Transmitting Data)
EXT/INT High
0.1
External (Can Run Continually)
1, 2, 3
2.3
--
-10
MHz
ISINK = 1.6 mA
ISOURCE = 500 µA
-4
---
0.4
--
V
Leakage Current 1
High-Z State,
VOUT = 0V to VDIG
--
--
±16
µA
Output Capacitance 1
High-Z State
--
15
--
pF
VOL
VOH
Memory
TABLE 9. 7809ALP DIGITAL OUTPUTS
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
1. Not tested.
TABLE 10. 7809ALP DIGITAL INPUTS
PARAMETER
VIL
SUBGROUPS
MIN
TYP
MAX
UNIT
1, 2, 3
-0.3
--
0.8
V
2.0
--
V+0.3
V
--
--
+/- 10
uA
VIH
IIL - IHL
09.03.15 Rev 2
All data sheets are subject to change without notice
6
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All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 11. 7809ALP POWER SUPPLIES
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
PARAMETER
SUBGROUPS
CONDITIONS
MIN
TYP
MAX
UNIT
Must be < VANA
4.75
5
5.25
V
4.75
5
5.25
V
IDIG
--
0.3
--
mA
IANA
--
16
--
mA
26.4
mA
VDIG
1, 2, 3
VANA
1, 2, 3
Icc
1, 2, 3
Power Dissipation
PWRD LOW
PWRD HIGH1
1, 2, 3
IDIG +IANA @
100KHz
mW
VANA = VDIG = 5V
fs = 100 kHz
---
---
132
100
1) Not Tested
TABLE 12. 7809ALP CONTROL LINE FUNCTIONS FOR READ AND CONVERT
CS
R/C
BUSY
EXT/INT
DATACL
K
PWRD
Initiate Conversion and Output
Data using Internal Clock
1>0
0
1
0
Output
0
x
Initiates conversion “n”.
Data from conversion “n1” clocked out on DATA
synchronized to 16 clock
pulses output on DATACLK
0
1>0
1
0
Output
0
x
Initiates conversion “n”.
Data from conversion “n1” clocked out on DATA
synchronized to 16 clock
pulses output on DATACLK
09.03.15 Rev 2
Memory
SPECIFIC FUNCTION
SB/BTC OPERATION
All data sheets are subject to change without notice
7
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16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 12. 7809ALP CONTROL LINE FUNCTIONS FOR READ AND CONVERT
SPECIFIC FUNCTION
CS
R/C
BUSY
EXT/INT
DATACL
K
PWRD
Initiate Conversion and Output
Data using External Clock
1>0
0
1
1
Input
0
x
Initiates conversion “n”
0
1>0
1
1
Input
0
x
Initiates conversion “n”
1>0
1
1
1
Input
x
x
Outputs a pulse on SYNC
followed by data from conversion “n” clocked out
synchronized to external
DATACLK.
1>0
1
0
1
Input
0
x
Outputs a pules on SYNC
followed by data from conversion “n-1” clocked out
synchronized to external
DATACLK 1. Conversion
“n” in process.
0
0>1
0
1
Input
0
x
Outputs a pulse on SYNC
followed by data from conversion “n-1” clocked out
synchronized to external
DATACLK 1. Conversion
“n” in process.
Incorrect Conversions
0
0
0>1
x
x
0
x
CS or R/C must be HIGH
or a new conversion will
be initiated without time
for acquisition
Power Down
x
x
x
x
x
0
x
Analog circuitry powered.
Conversion will be initiated without time for
acquisition
x
x
x
x
x
1
x
Analog circuitry disabled.
Data from previous conversion maintained in output registers
x
x
x
x
x
x
0
Serial data is output in
Binary Two’s Complement format.
x
x
x
x
x
x
1
Serial data is output in
Straight Binary format.
SB/BTC OPERATION
Selecting Output
Format
1. See Figure 4 for constraints on previous data valid during conversion.
TABLE 13. 7809ALP INPUT RANGE CONNECTION
ANALOG INPUT RANGE
±10V
CONNECT R1IN VIA 200Ω CONNECT R2IN VIA 100Ω
TO
TO
VIN
AGND
09.03.15 Rev 2
CONNECT R3IN TO
IMPEDANCE
CAP
22.9 kΩ
All data sheets are subject to change without notice
8
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All rights reserved.
Memory
1) Not Tested
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 13. 7809ALP INPUT RANGE CONNECTION
CONNECT R1IN VIA 200Ω CONNECT R2IN VIA 100Ω
CONNECT R3IN TO
IMPEDANCE
VIN
CAP
13.3 kΩ
VIN
VIN
CAP
10.7 kΩ
0V to 10V1
AGND
VIN
AGND
13.3kΩ
0V to 5V1
AGND
AGND
VIN
10.0 kΩ
0V to 4V
VIN
AGND
VIN
10.7 kΩ
ANALOG INPUT RANGE
TO
TO
±5V1
AGND
±3.3V1
TABLE 14. 7809ALP CONVERSION AND DATA TIMING
(SPECIFIED PERFORMANCE: -40 TO +85°C USING EXTERNAL REFERENCE; -35 TO +85°C USING INTERNAL REFERENCE)
SYMBOL
DESCRIPTION
SUBGROUPS
MIN
TYP
MAX
UNIT
Convert Pulse Width
9, 10, 11
40
--
6000
ns
t2
BUSY Delay
9, 10, 11
--
--
80
ns
t3
BUSY LOW
9, 10, 11
--
--
8
µs
t4
BUSY Delay after End of Conversion
9, 10, 11
--
220
--
ns
t5
Aperture Delay
9, 10, 11
--
40
--
ns
t6
Conversion Time
9, 10, 11
--
7.6
8
µs
t7
Acquisition Time
9, 10, 11
--
--
2
µs
t6 + t7
Throughput Time
9, 10, 11
--
9
10
µs
t8
R/C Low to DATACLK Delay
9, 10, 11
--
450
--
ns
t9
DATACLK Period
9, 10, 11
--
440
--
ns
t10
Data Valid to DATACLK HIGH Delay
9, 10, 11
20
75
--
ns
t11
Data Valid after DATACLK LOW
Delay
9, 10, 11
100
125
--
ns
t12
External DATACLK
9, 10, 11
100
--
--
ns
t13
External DATACLK HIGH
9, 10, 11
20
--
--
ns
t14
External DATACLK LOW
9, 10, 11
30
--
--
ns
t15
DATACLK HIGH Setup Time
9, 10, 11
20
--
t12 + 5
ns
t16
R/C to CS Setup Time
9, 10, 11
10
--
--
ns
t17
SYNC Delay After DATACLK High
9, 10, 11
15
--
45
ns
t18
Data Valid Delay
9, 10, 11
25
--
70
ns
t19
CS to Rising Edge Delay
9, 10, 11
25
--
--
ns
t20
Data Available after CS LOW
9, 10, 11
6
--
--
µs
09.03.15 Rev 2
All data sheets are subject to change without notice
Memory
t1
9
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All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
TABLE 15. 7809ALP OUTPUT CODES AND IDEAL INPUT VOLTAGES
DIGITAL OUTPUT
DESCRIPTION
BINARY TWO’S
COMPLEMENT (SB/BTC
LOW)
ANALOG INPUT
BINARY CODE
Full Scale
Range
±10
±5
±3.33V
0V to
10V
Least Significant Bit (LSB)
305 µV
153 µV
102 µV
153 µV
+ Full Scale
(FS - 1 LSB)
9.99969 4.99984 3.33323 9.99984 4.99992 3.99993
5V
7V
1V
7V
4V
8V
Midscale
-Full Scale
0V
0V
5V
-5V
3.33333
3V
0V
HEX
CODE
0V to 5V 0V to 4V
76 µV
2.5V
61 µV
2V
0111 1111
1111 1111
7FFF
1111 1111
1111 1111
FFFF
0000 0000
0000 0000
0000
1000 0000
0000 0000
8000
1111 1111
1111 1111
FFFF
0111 1111
1111 1111
7FFF
1000 0000
0000 0000
8000
0000 0000
0000 0000
0000
-305 µV -153 µV -102 µV 4.99984 2.49992 1.99993
7V
4V
9V
-10V
BINARY CODE
0V
0V
TABLE 16. LPTTM OPERATING CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNIT
Supply Threshold
ITHR
75
ma
Protection Time
TPT
10
us
Supply Recovery Time
TSR
50
us
Functional Recoverty Time
TFR
75
us
8-Bit Accuracy Recovery Time
T8R
80
us
TFAR
5
ms
Full Scale Recovery Time
FIGURE 1. CONVERSION TIMING
09.03.15 Rev 2
All data sheets are subject to change without notice
10
©2015 Maxwell Technologies
All rights reserved.
Memory
One LSB
Below Midscale
0V
HEX
CODE
STRAIGHT BINARY
(SB/BTC HIGH)
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
FIGURE 2. SERIAL DATA TIMING USING INTERNAL CLOCK (CS, EXT/INT AND TAG TIED LOW)
09.03.15 Rev 2
All data sheets are subject to change without notice
11
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Memory
FIGURE 3. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ AFTER
CONVERSION
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
FIGURE 4. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ DURING
CONVERSION
Memory
09.03.15 Rev 2
All data sheets are subject to change without notice
12
©2015 Maxwell Technologies
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16-Bit Latchup Protected Analog to Digital Converter
7809ALP
FIGURE 5. OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES
Memory
09.03.15 Rev 2
All data sheets are subject to change without notice
13
©2015 Maxwell Technologies
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16-Bit Latchup Protected Analog to Digital Converter
7809LP
Figure 7. LPTTM Timing Diagram
09.19.2011 Rev 10
All data sheets are subject to change without notice
#
©2011 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
FIGURE 6. OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES
Memory
09.03.15 Rev 2
All data sheets are subject to change without notice
15
©2015 Maxwell Technologies
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16-Bit Latchup Protected Analog to Digital Converter
7809ALP
Memory
24-PIN RAD-PAK® FLAT PACKAGE
DIMENSION
SYMBOL
MIN
NOM
MAX
A
0.255
0.278
0.302
b
0.015
0.017
0.022
c
0.006
0.008
0.010
D
--
0.596
0.606
E
0.390
0.400
0.410
E1
--
--
0.440
E2
0.268
0.270
0.272
E3
0.055
0.065
--
e
0.050 BSC
L
0.420
0.430
0.450
Q
0.040
0.045
0.050
S1
0.006
0.014
--
N
24
Note: All dimensions in inches
Top and Bottom of package internally connected to ground.
09.03.15 Rev 2
All data sheets are subject to change without notice
16
©2015 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
Important Notice:
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
Memory
09.03.15 Rev 2
All data sheets are subject to change without notice
17
©2015 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
7809ALP
Product Ordering Options
Model Number
7809ALP
RP
F
X
Option Details
Feature
Multi Chip Module (MCM)1
K = Maxwell Self-Defined Class K
H = Maxwell Self-Defined Class H
I = Industrial (testing @ -40°C,
+25°C, +85°C)
E = Engineering (testing @ +25°C
Package
F = Flat Pack
Radiation Feature
RP = RAD-PAK® package
Base Product
Nomenclature
16-Bit Latchup Protected Analog
to Digital Converter
Memory
Screening Flow
1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows.
09.03.15 Rev 2
All data sheets are subject to change without notice
18
©2015 Maxwell Technologies
All rights reserved.
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