9240LP 9240 14 Bit A/D LPTBIT 9240LP BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 DVDD LPTVREF AVDD LPTDVDD VINA DVDD LPTDRVDD DRVDD LPTVINA VINA VINB LPTVINB DRVDD LPTVREF VREF VINB VREF CROW BAR Memory 9240LP Block Diagram DVSS AVSS DVDD AVDD NC DRVDD CLK LPTSTATUS LPTBIT NC BIT 14 NC BIAS CAPB CAPT NC CML LPTref VinA VinB LPTAVDD LPTDVDD LPTAVDD CURRENT SENSE AVDD Data Outputs LPTSTATUS Control Signals REFCOM Vref SENSE NC AVSS AVDD NC NC OTC BIT 1 BIT 2 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FEATURES: DESCRIPTION: • RAD-PAK® radiation-hardened against natural space radiation • Low power dissipation: 285 mW • Single 5 V supply • Integral nonlinearity error: 2.5 LSB • Differential nonlinearity error: 0.6 LSB • Input referred noise: 0.36 LSB • Complete: On-chip sample-and-hold amplifier and voltage reference • Signal-to-noise and distortion ration: 77.5 dB • Spurious-free dynamic range: 90 dB • Out-of-range indicator • Straight binary output data • Total dose hardened to 100 krads (Si), dependent on orbit and mission duration • Single Event Latchup (SEL) protected Maxwell Technologies 9240LP is a 14-bit analog to digital converter that operates at a 10 MSPS rate. Manufactured with a high speed CMOS process, this A/D, with latch-up protection, contains an onchip, high performance, low noise, sample-andhold amplifier and a programmable voltage reference. The 9240LP offers single supply operation and dissipates only 480 mW with a 5 volt supply. This device provides no missing codes and excellent temperature drift performance over the full operating temperature range. The 9240LP utilizes Maxwell’s LPT™ Latchup Protection Circuit. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK® provides protection to 100 krad (Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defined Class K flow. 11.09.12 Rev 8 (858) 503-3300- Fax: (858) 503-3301- www.maxwell.com All data sheets are subject to change without notice 1 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC TABLE 1. 9240LP PIN DESCRIPTION PIN NUMBER NAME DESCRIPTION 1 DVSS Digital Ground 2, 29 AVSS Analog Ground 3 DVDD 5V Digital Supply 4, 28 AVDD 5V Analog Supply 5 NC 6 DRVDD 7 CLK 8 LPTSTATUS A 0 to 5V square-wave is output during the decision time and protect time. Normally low. 9 LPTBIT The LPT circuit will crowbar the power supplies to the 9240 for as long as a logic high is applied. Used to verify operation of the LPT. Normally a logical low or ground is applied to this input. 10 NC 11 BIT 14 12-23 BIT 13-BIT 2 24 BIT 1 Most Significant Data Bits (MSB) 25 OTR Out of Range 26, 27, 30 NC No Connect 31 SENSE 32 VREF 33 REFCOM 34, 38 NC 35 BIAS 1 Power/Speed Programming 36 CAPB Noise Reduction Pin 37 CAPT Noise Reduction Pin 39 CML Common-Mod Level (Midsupply) 40 LPTVREF 41 VINA Analog Input Pin (+) 42 VINB Analog Input Pin (-) 43 LPTDVDD Protected 5V Digital Supply 44 LPTAVDD Protected 5V Analog Supply No Connect Digital Output Driver Supply Clock Input Pin Memory No Connect Least Significant Data Bit (LSB) Data Output Bits Reference Select Reference I/O Reference Common No Connect Protected Reference I/O 1. See Speed/Power programmability section. 11.09.12 Rev 8 All data sheets are subject to change without notice 2 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC TABLE 2. 9240LP ABSOLUTE MAXIMUM RATINGS 1 WITH RESPECT TO MIN AVDD AVSS DVDD PARAMETER SYMBOL UNIT -0.3 6.5 V DVSS -0.3 6.5 V AVSS DVSS -0.3 0.3 V AVDD DVDD -6.5 6.5 V DRVDD DRVSS -0.3 6.5 V DRVSS AVSS -0.3 0.3 V REFCOM AVSS -0.3 0.3 V CLK AVSS 0 AVDD -0.5 V DRVSS -0.3 DRVDD + 0.3 V VINA, VINB AVSS -0.3 AVDD + 0.3 V VREF AVSS -0.3 AVDD + 0.3 V SENSE AVSS -0.3 AVDD + 0.3 V CAPB, CAPT AVSS -0.3 AVDD + 0.3 V BIAS AVSS -0.3 AVDD + -.3 V Junction Temperature TJ -- 150 °C Operating Temperature TA -55 125 °C Package Weight -- 10.5 -- Grams 9.6 -- °C/W Thermal Resistance TJC -- Storage Temperature TSTG -65 150 °C TL -- 300 °C Lead Temperature (10 sec) Memory MAX Digital Outputs TYP 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. TABLE 3. DTELTA ABLEPARAMETERS 1. PARAMETERS VARIATION IDVDD +/- 10 % IADVD +/- 10% 1. Parameters are measured and recorded as Deltas per MIL-STD-883 for Class K devices. Specified in Table 4. 11.09.12 Rev 8 All data sheets are subject to change without notice 3 ©2012 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP TABLE 3. TABLE 4. 9240LP DC SPECIFICATIONS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2KΩ, VREF = 2.5V, VINA=VINB = ±2.5V DIFFERENTIAL INPUT CENTERED ON VREF(1.25V TO 3.75V ABSOLUTE) TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER RESOLUTION MAX CONVERSION RATE MAX REFERRED VREF= 1 V VREF = 2.5V SUBGROUPS MIN TYP1 MAX UNIT 1 14 -- -- Bits min 9, 10, 11 10 -- -- MHz min --- 0.9 0.36 --- LSB rms -3 -1 ----0.3 -1.5 -0.75 ±2.5 ±0.6 ±2.5 ±0.7 ----- 3 1.0 -14 0.3 1.5 0.75 LSB LSB LSB LSB Bits Guaranteed % FSR % FSR % FSR ---- 3.0 20.0 5.0 ---- ppm/°C ppm/°C ppm/°C -- -- 0.1 % FSR 2 -0 -- ---16 -5 AVDD + .25 -- V p-p V p-p V pF ------- 1 -2.5 -10 -- -±14 -±35 -10.0 V mV V mV mV mV -- 5 -- kΩ NOISE1 1, 2, 3 1, 2, 3 1 1 1 TEMPERATURE DRIFT Zero Error Gain Error4 Gain Error5 1, 2, 3 POWER SUPPLY REJECTION 1, 2, 3 Memory ACCURACY2 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL3 DNL3 No Missing Codes Zero Error (@ 25 °C) Gain Error (@ 25 °C)1,4 Gain Error (@ 25 °C)5 INPUT1 ANALOG Input Span (with VREF = 1.0 V) (with VREF = 2.5 V) Input (VINA OR VINB) Range Input Capacitance 1, 2, 3 INTERNAL VOLTAGE REFERENCE1 Output Voltage (1V mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2.5 V Mode) Output Voltage Tolerance (2.5 V Mode) Load Regulation VREF Load Regulation LPTVREF6,7 REFERENCE INPUT RESISTANCE 1, 2, 3 11.09.12 Rev 8 All data sheets are subject to change without notice 4 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC TABLE 3. TABLE 4. 9240LP DC SPECIFICATIONS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2KΩ, VREF = 2.5V, VINA=VINB = ±2.5V DIFFERENTIAL INPUT CENTERED ON VREF(1.25V TO 3.75V ABSOLUTE) TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS LPT ASIC RDS ON - VREF 1, 2, 3 MIN POWER SUPPLIES Supply Voltages - AVDD - DVDD - DRVDD Supply Current - IAVDD - IDVDD MAX UNIT 8 8 105 105 15 Ω Ω Ω Ω 10 70 75 ±15 28 ±5 1, 2, 3 1, 2, 3 µs µs mA mA mA ---- 5 5 5 5 5 5 --- 43 3 55 16 Memory - AVDD - DVDD - VIN A - VIN B LATCHUP PROTECTION - Decision Time - Protect Time - AVDD Trip Current - AVDD Trip Current Tolerance - DVDD Trip Current - DVDD Trip Current Tolerance TYP1 V (±5% AVDD Operating) V (±5% DVDD Operating) V (±5% DRVDD Operating) mA mA POWER CONSUMPTION8 1. Guaranteed by design 295 355 mW 2. Tested using external VREF with servo control 3. VREF = 1V 4. Including internal reference 5. Excluding internal reference 6. Load regulkation with 1 mA load current 7. LPTVREF should not be capacitively loaded above 0.1uF 8. Calculated from IDD 11.09.12 Rev 8 All data sheets are subject to change without notice 5 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC TABLE 5. 9240LP AC SPECIFICATIONS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, fSAMPLE = 10MSPS, BIAS = 2KΩ, VREF = 2.5V, VINA = -0.5dBFS, AC COUPLED/DIFFERENTIAL INPUT, TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) MIN TYP1 MAX UNIT SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz ---- 76.0 76.0 75.5 ---- dB dB dB EFFECTIVE NUMBER OF BITS (ENOB)2 fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz 12 --- -12.3 11.9 ---- Bits Bits Bits 74.5 --- 77 77 77 ---- dB dB dB ---- -76.0 -83.0 -75.0 ---- dB dB dB ---- 90.0 90.0 80.0 ---- dB dB dB ------- 70 70 1 4 45 167 ------- MHz MHz ns ps rms ns ns TYP MAX UNIT 5 -1.0 ±10 ±10 -- V V µA µA pF SUBGROUPS PARAMETER SIGNAL-TO-NOISE RATION (SNR) fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz 4, 5, 6 SPURIOUS FREE DYNAMIC RANGE fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz Memory TOTAL HARMONIC DISTORTION (THD) fINPUT = 500 kHz fINPUT = 1.0 MHz fINPUT = 5.0 MHz 4, 5, 6 DYNAMIC PERFORMANCE1 Full Power Bandwidth Small Signal Bandwidth Aperture Delay Aperture Jitter Acquisition to Full-Scale Step (0.0025%) Overvoltage Recovery Time 1. Guaranteed by design 2. ENOB calculated from SNR TABLE 6. 9240LP DIGITAL SPECIFICATIONS (AVDD = 5V, DVDD = 5V, TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER CLOCK INPUT1 High Level Input Voltage2 Low Level Input Voltage High Level Input Current (VIN = DVDD) Low Level Input Current (VIN = 0V) Input Capacitance SUBGROUPS SYMBOL MIN VIH VIL IIH IIL CIN 3.5 ----- 1, 2, 3 11.09.12 Rev 8 All data sheets are subject to change without notice 6 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC TABLE 6. 9240LP DIGITAL SPECIFICATIONS (AVDD = 5V, DVDD = 5V, TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS SYMBOL MIN TYP MAX UNIT LOGIC OUTPUTS (with DRVDD = 5V) 1, 2, 3 High Level Output Voltage (IOH = 50 µA) VOH 4.5 High Level Output Voltage (IOH = 0.5 mA) VOH 2.4 Low Level Output Voltage (IOL = 1.6 mA) VOL 0.4 Low Level Output Voltage (IOL = 50 µA) VOL 0.1 Output Capacitance COUT 5 1. Due to the voltage drop across the LPT circuiry the CLOCK signal must be no greater than AVDD - 0.5V V min V min V max V max pF typ 2. Guaranteed by design TABLE 7. 9240LP SWITCHING CHARACTERISTICS1 (TA = -55 TO +125°C WITH AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2 KW, CL = 20 PF) PARAMETER MIN TYP MAX UNITS tC tCH tCL tOD 100 45 45 8 ---- ----13 ----- ns ns ns ns ns ns Clock Cycles Pipeline Delay (Latency) 1. Guaranteed by design -- 19 -- TYPICAL DIFFERENTIAL CHARACTERIZATION CURVES/PLOTS (AVDD = 5V, DVDD = 5V, DRVDD = 5V, fSAMPLE = 10 MSPS, RBIAS = 2 KW, TA = 25 °C, DIFFERENTIAL INPUT) FIGURE 1. TIMING DIAGRAM 11.09.12 Rev 8 All data sheets are subject to change without notice 7 ©2012 Maxwell Technologies All rights reserved. Memory Clock Period CLOCK Pulse width High CLOCK Pulse width Low Output Delay SYMBOL 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 2. SINAD VS. INPUT FREQUENCY (INPUT SPACE = 2V, VCM = 2.5V) FIGURE 3. THD VS. INPUT FREQUENCY (INPUT SPAN = 5V, VCM = 2.5V) Memory 11.09.12 Rev 8 All data sheets are subject to change without notice 8 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 4. TYPICAL FFT, fIN = 1.0 MHZ (INPUT SPACE = 5V, VCM = 2.5V) FIGURE 5. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2V, VCM = 2.5V) Memory FIGURE 6. THD VS. INPUT FREQUENCY (INPUT SPAN = 2V, VCM = 2.5V) 11.09.12 Rev 8 All data sheets are subject to change without notice 9 ©2012 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 7. TYPICAL FFT, fIN = 5.0 MHZ (INPUT SPAN = 2 V, VCM = 2.5 V) FIGURE 8. THD VS. SAMPLE RATE (fIN = 5.0 MHZ, AIN = -0.5 DBFS, VCM = 2.5 V) Memory FIGURE 9. SINGLE TONE SFDR (fIN = 5.0 MHZ, VCM = 2.5 V) 11.09.12 Rev 8 All data sheets are subject to change without notice 10 ©2012 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 10. DUAL TONE SFDR (F1 = 0.95 MHZ, F2 = 1.04 MHZ, VCM = 2.5 V) Memory FIGURE 11. TYPICAL INL (INPUT SPAN = 5 V) FIGURE 12. TYPICAL DNL (INPUT SPAN = 5 V) 11.09.12 Rev 8 All data sheets are subject to change without notice 11 ©2012 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 13. “GROUNDED-INPUT” HISTOGRAM (INPUT SPAN = 5 V) 11.09.12 Rev 8 All data sheets are subject to change without notice 12 ©2012 Maxwell Technologies All rights reserved. Memory FIGURE 14. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2 V, VCM = 2.5V) 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 15. THD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) FIGURE 16. CMR VS. INPUT FREQUENCY (INPUT SPAN = 2 V, VCM = 2.5 V) Memory 11.09.12 Rev 8 All data sheets are subject to change without notice 13 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 17. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) FIGURE 18. THD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) Memory FIGURE 19. TYPICAL VOLTAGE REFERENCE ERROR VS. TEMPERATURE 11.09.12 Rev 8 All data sheets are subject to change without notice 14 ©2012 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP FIGURE 20. SEL CROSS SECTION Memory 44 PIN RAD-PAK® QUAD FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A 0.185 0.205 0.225 b 0.015 0.017 0.019 c 0.008 0.010 0.012 D 0.643 0.650 0.657 D1 0.50 BSC e 0.050 BSC S1 0.005 0.067 -- L 0.260 0.270 0.280 Q 0.020 0.025 0.030 N 44 Note: All dimensions in inches 11.09.12 Rev 8 All data sheets are subject to change without notice 15 ©2012 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 11.09.12 Rev 8 All data sheets are subject to change without notice 16 ©2012 Maxwell Technologies All rights reserved. 9240LP 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC Product Ordering Options Model Number 9240LP RP Q X Feature Screening Flow Radiation Feature Base Product Nomenclature Multi Cjip Module1 K= Maxwell Class K H= Maxwell Class H I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) Memory Package Option Details Q = Quad Flat Pack RP = RAD-PAK® package 14-Bit, 10MSPS A/D Converter with LPT ASIC 1) Products are manufacturered and screened to Maxwell Technologies self-defined CLASS H and CLASS K flows. 11.09.12 Rev 8 All data sheets are subject to change without notice 17 ©2012 Maxwell Technologies All rights reserved.