54LVTH16373 - Interface, D-Latch, 16 Bit, 3.3V

54LVTH16373
3.3V ABT16-Bit Transparent
D-Type Latches
1OE
1
48
1Q1
1LE
1D1
1Q2
1D2
GND
GND
1Q3
1D3
1Q4
1D4
VCC
VCC
1Q5
1D5
1Q6
1D6
GND
GND
1Q7
1D7
1Q8
1D8
2Q1
2Q2
54LVTH16373
2D2
GND
2Q3
2D3
2Q4
2D4
VCC
VCC
2Q5
2D5
2Q6
2D6
GND
GND
2Q7
2D7
1LE/2LE
1/24
48/25
C1
1D1/2D1
47/36
25
1Q1/2Q1
1D
To Seven Other Channels
Logic Diagram
2D8
24
2/13
2LE
FEATURES:
DESCRIPTION:
• 3.3V low voltage advanced BiCMOS technology (LVT) 16bit transparent D-type latches with 3-state outputs
• Total dose hardness:
- > 100 krad (Si), dependent upon space mission
• Single event effect:
- SELTH : No LU > 119 MeV/mg/cm2
• Package: 48 pin RAD-PAK® flat package
• Operating temperature range:
- 55 to 125°C
• Distributed VCC and GND pin configuration minimizes highspeed switching noise
• Supports mixed-mode signal operation
- 5V input and output voltages with 3.3V VCC
• Supports unregulated battery operation down to 2.7V
• Typical VOLP (output ground bounce) < 0.8V at VCC=3.3V,
TA=25°C
• Latch-up performance exceeds 500mA per JEDEC standard
• Supports live insertion
• Bus-hold data inputs eliminate the need for external pullup
resistors
Maxwell Technologies’ 54LVTH16373 16-bit transparent Dtype latches with 3-state output features a greater than 100
krad (Si) total dose tolerance, dependent upon space mission.
The 54LVTH16373 is designed for low voltage (3.3V) VCC
operation, but with the capability to provide a TTL interface to
a 5V system environment. It is suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers. The 54LVTH16373 can be used as two 8-bit latches or
one 16-bit latch. When the latch-enable (LE) input is low, the
Q output are latched at the levels set up at the data (D) inputs.
When LE is high, the Q outputs follow the D inputs. A buffered
output-enable (OE) input can be used to place the eight outputs in either a normal logic state or a high impedance state.
In the high impedance state, the outputs neither load nor drive
the bus lines significantly. The high impedance state and the
increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
2.19.03 Rev 2
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice
1
©2003 Maxwell Technologies
All rights reserved.
Memory
2Q8
1OE/2OE
2D1
GND
2OE
Logic Diagram (PositiveLogic)
54LVTH16373
3.3V ABT 16-Bit Transparent D-Type Latches
TABLE 1. PINOUT DESCRIPTION
PIN
SYMBOL
DESCRIPTION
1, 24
1OE-2OE
Output Enable
2, 3, 5, 6, 8, 9, 11, 12
1Q1-1Q8
Outputs
4, 10, 15, 21, 28, 34, 39, 45
GND
Ground
7, 18, 31, 42
VCC
Power Supply
13, 14, 16, 17, 19, 20, 22, 23
2Q1-2Q8
Outputs
25, 48
2LE-1LE
Latch Enable
26, 27, 29, 30, 32, 33, 35, 36
2D8-2D1
Inputs
37, 38, 40, 41, 43, 44, 46, 47
1D8-1D1
Inputs
TABLE 2. 54LVTH16373 ABSOLUTE MAXIMUM RATINGS
SYMBOL
MIN
MAX
UNIT
Supply voltage range
VCC
-0.5
4.6
V
Input voltage range 1
VI
-0.5
7
V
Voltage range applied to any output in the high state or power-off
state 1
VO
-0.5
7
V
Current into any output in the low state
IO
--
96
mA
Current into any output in the high state 2
IO
--
48
mA
Input clamp current (VI < 0)
IIK
--
-50
mA
Output clamp current (VO < O)
IOK
--
-50
mA
Maximum power dissipation at TA = 55°C 3
PD
--
0.85
mW
Storage temperature range
TS
-65
150
°C
Memory
PARAMETER
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150° C and a board trace length of 750
mils.
2.19.03 Rev 2
All data sheets are subject to change without notice
2
©2003 Maxwell Technologies
All rights reserved.
54LVTH16373
3.3V ABT 16-Bit Transparent D-Type Latches
TABLE 3. DELTA LIMITS
PARAMETER
VARIATION1
ICC(OL)
±10%
ICC(OH)
±10%
±10%
ICC(OD)
1. ± 10% of specified value in Table 5
TABLE 4. 54LVTH16373 RECOMMENDED OPERATING CONDITIONS 1
PARAMETER
MIN
MAX
UNIT
Supply voltage
VCC
2.7
3.6
V
High-level input voltage
VIH
2
--
V
Low-level input voltage
VIL
--
0.8
V
Input voltage
VI
--
5.5
V
High-level output current
IOH
--
-24
mA
Low-level output current
IOL
Input transition rise or fall rate (outputs enabled)
Operating free-air temperature
--
48
mA
∆t/∆v
--
10
ns/V
TA
-55
125
°C
Memory
SYMBOL
1. Unused control inputs must be held high or low to prevent them from floating.
TABLE 5. 54LVTH16373 DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = -55 to 125° C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
TEST CONDITIONS
Input Clamp Voltage
VIK
VCC = 2.7
High-Level Output Voltage
VOH
VCC = 2.7V to 3.6V
Low-Level Output Voltage
VOL
SUBGROUPS
MIN
MAX
UNIT
II = -18mA
1, 2, 3
--
-1.2
V
IOH = -100µ A
1, 2, 3
VCC -0.2
--
V
VCC = 2.7V
IOH = -8mA
2.4
--
VCC = 3V,
IOH = -24mA
2.0
--
VCC = 2.7V
IOL = 100µ A
--
0.2
IOL = 24mA
--
0.5
IOL = 16mA
--
0.4
IOL = 32mA
--
0.5
VCC = 3V
IOL = 48mA
2.19.03 Rev 2
1, 2, 3
V
0.55
All data sheets are subject to change without notice
3
©2003 Maxwell Technologies
All rights reserved.
3.3V ABT 16-Bit Transparent D-Type Latches
54LVTH16373
TABLE 5. 54LVTH16373 DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = -55 to 125° C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
Input Current
SYMBOL
II
TEST CONDITIONS
VCC = 0 or 3.6V
VI = 5.5V
MIN
1, 2, 3
MAX
UNIT
30
µA
VCC = 3.6V
VI = VCC or
GND
Control
Inputs
--
±1
VCC = 3.6V
VI = VCC
Data
Inputs
--
1
--
-5
75
--
-75
--
VI = 0
Hold Current
SUBGROUPS
II(HOLD) VCC = 3V
VI = 0.8V
VI = 2V
Data
Inputs
1, 2, 3
µA
Output Disabled Leakage
Current - High
IOZH
VCC = 3.6V, VO = 3V
1, 2, 3
--
5
µA
Output Disabled Leakage
Current - Low
IOZL
VCC = 3.6V, VO = 0.5V
1, 2, 3
--
-5
µA
IOZPU2
VCC = 0 to 1.5V, VO = 0.5V to 3V, OE = don’t
care
1, 2, 3
--
±100
µA
Power Down Current
IOZPD2
VCC = 1.5V to 0, VO = 0.5V to 3V, OE = don’t
care
1, 2, 3
--
±100
µA
VCC = 3.6V
IO = 0
VI = VCC or GND
1, 2, 3
--
0.19
mA
Outputs
low
--
5
Outputs
disabled
--
0.19
--
0.2
mA
Supply Current
Delta Supply Current
ICC
Outputs
high
∆ICC 1 VCC = 3V to 3.6V, One input at VCC -0.6V,
1, 2, 3
Memory
Power Up Current
Other inputs at VCC or GND
Input Capacitance
CI2
VI = 3V or 0
--
10
pF
Input Output Capacitance
CO2
VO = 3V or 0
--
15
pF
1. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
2. Die manufacturer’s specification, not production tested.
TABLE 6. 54LVTH16373 AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = -55 to 125° C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
Pulse duration, LE high
SYMBOL
tW
SUBGROUPS
9, 10, 11
VCC = 3.3V ± 0.3V
VCC = 2.7V
UNIT
MIN
MAX
MIN
MAX
3.3
--
3.3
--
2.19.03 Rev 2
ns
All data sheets are subject to change without notice
4
©2003 Maxwell Technologies
All rights reserved.
54LVTH16373
3.3V ABT 16-Bit Transparent D-Type Latches
TABLE 6. 54LVTH16373 AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = -55 to 125° C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
VCC = 3.3V ± 0.3V
SUBGROUPS
VCC = 2.7V
UNIT
MIN
MAX
MIN
MAX
Setup time, data before LEØ
tSU
9, 10, 11
2.0
--
2.0
--
ns
Hold time, data after LEØ
tH
9, 10, 11
3.0
--
3.3
--
ns
Propagation Delay Time
D to Q
tPLH
9, 10, 11
1.0
4.5
--
5.2
ns
1.0
4.4
--
4.8
Propagation Delay Time
LE to Q
tPLH
1.4
5.5
--
5.8
1.4
5.2
--
5.6
1.0
5.7
--
6.7
1.0
5.5
--
6.0
1.6
6.0
--
6.2
1.0
5.2
--
5.6
tPHL
9, 10, 11
tPHL
Output Enable Time
OE to Q
tPZH
Output Disable Time
OE to Q
tPHZ
9, 10, 11
tPZL
9, 10, 11
tPLZ
ns
ns
ns
Memory
TABLE 7. FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
FIGURE 1. LOAD CIRCUIT FOR OUTPUTS
Figure Note:
2.19.03 Rev 2
All data sheets are subject to change without notice
5
©2003 Maxwell Technologies
All rights reserved.
3.3V ABT 16-Bit Transparent D-Type Latches
54LVTH16373
1. CL includes probe and jig capacitance.
PARAMETER MEASUREMENT INFORMATION
TEST
S1
TPLH/TPHL
Open
TPLZ/TPZL
6V
TPHZ/TPZH
GND
FIGURE 2. PULSE DURATION
Memory
FIGURE 3. SETUP AND HOLD TIMES
2.19.03 Rev 2
All data sheets are subject to change without notice
6
©2003 Maxwell Technologies
All rights reserved.
3.3V ABT 16-Bit Transparent D-Type Latches
54LVTH16373
FIGURE 4. PROPAGATION DELAY TIMES INVERTING AND NON-INVERTING OUTPUTS
Memory
FIGURE 5. ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
FIGURE NOTES:
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
3. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 5Ω, tr < 2.5 ns, tf < 2.5
ns.
4. The outputs are measured one at a time with one transition per measurement.
2.19.03 Rev 2
All data sheets are subject to change without notice
7
©2003 Maxwell Technologies
All rights reserved.
3.3V ABT 16-Bit Transparent D-Type Latches
54LVTH16373
Memory
48 PIN RAD-PAK® FLAT PACKAGE
SYMBOL
DIMENSION
MIN
NOM
MAX
A
0.144
0.160
0.176
b
0.008
0.010
0.014
c
0.004
0.006
0.007
D
--
0.620
0.640
E
0.370
0.380
0.390
E1
--
--
0.410
E2
0.200
0.210
0.220
E3
0.075
0.085
--
e
0.025 BSC
L
0.275
0.285
0.295
Q
0.013
0.019
0.025
S1
0.005
0.018
--
N
48
Note: All dimensions in inches
2.19.03 Rev 2
All data sheets are subject to change without notice
8
©2003 Maxwell Technologies
All rights reserved.
3.3V ABT 16-Bit Transparent D-Type Latches
54LVTH16373
Important Notice:
These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
Memory
2.19.03 Rev 2
All data sheets are subject to change without notice
9
©2003 Maxwell Technologies
All rights reserved.
3.3V ABT 16-Bit Transparent D-Type Latches
54LVTH16373
Product Ordering Options
Model Number
54LVTH16373
RP
F
X
Option Details
Feature
Monolithic
S = Maxwell Class S
B = Maxwell Class B
I = Industrial (testing @ -55°C,
+25°C, +125°C)
E = Engineering (testing @ +25°C)
Package
F = Flat Pack
Radiation Feature
RP = RAD-PAK® package
Base Product
Nomenclature
3.3V 16-Bit Transparent
D-Type Latches
2.19.03 Rev 2
All data sheets are subject to change without notice
Memory
Screening Flow
10
©2003 Maxwell Technologies
All rights reserved.
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