33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM Memory Logic Diagram FEATURES: DESCRIPTION: • RAD-PAK® Technology radiation-hardened against natural space radiation • 524,288 x 8 bit organization · Total dose hardness: - > 100 krad (Si), depending upon space mission • Excellent Single Event Effect · - SELTH: > 68 MeV/mg/cm2 Maxwell Technologies’ 33LV408 high-density 4 Megabit SRAM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. Using Maxwell’s radiation-hardened RAD-PAK® packaging technology, the 33LV408 realizes a high density, high performance, and low power consumption. Its fully static design eliminates the need for external clocks, while the CMOS circuitry reduces power consumption and provides higher reliability. The 33LV408 is equipped with eight common input/output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. The 33LV408 features the same advanced 512K x 8-bit SRAM, high-speed, and low-power demand as the commercial counterpart. · - SEUTH: = 3 MeV/mg/cm2 - SEU saturated cross section: 6E-9 cm2/bit • Package: - 32-Pin RAD-PAK® flat packFast access time: - 20, 25, 30 ns maximum times available • Single 3.3V + 10% power supply • Fully static operation - No clock or refresh required • Three state outputs • TTL compatible inputs and outputs • Low power: - Standby: 60 mA (TTL); 10 mA (CMOS) - Operation: 150 mA (20 ns); 140 mA (25 ns); 130 mA (30 ns) Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK® provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 08.06.07 REV 3 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com All data sheets are subject to change without notice 1 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 1. PINOUT DESCRIPTION PIN SYMBOL DESCRIPTION 12-5, 27, 26, 23, 25, 4, 28, 3, 31, 2, 30, 1 A0-A18 29 WE Write Enable 22 CS Chip Select 24 OE Output Enable 13-15, 17-21 I/O 0-I/O 7 32 VCC Power 16 VSS Ground Address Inputs Data Inputs/Outputs TABLE 2. 33LV408 ABSOLUTE MAXIMUM RATINGS SYMBOL MIN MAX UNIT VCC -0.5 4.6 V VIN, VOUT -0.5 VCC +0.5 V Power Dissipation PD -- 1.0 W Storage Temperature TS -65 +150 °C Operating Temperature TA -55 +125 °C Voltage on VCC supply relative to VSS Voltage on any pin relative to VSS Memory PARAMETER TABLE 3. DELTA LIMITS PARAMETER VARIATION ICC ±10% of stated vaule in Table 6 ISB ±10% of stated vaule in Table 6 ISB1 ±10% of stated vaule in Table 6 08.06.07 REV 3 All data sheets are subject to change without notice 2 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 4. 33LV408 RECOMMENDED OPERATING CONDITIONS (VCC = 3.3 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Supply Voltage Ground SYMBOL MIN MAX UNIT VCC 3.0 3.6 V VSS 0 0 V Input High Voltage 1 VIH 2.2 VCC+0.3 V Input Low Voltage 2 VIL -0.3 0.8 V ΘJC -- 1.21 °C/W SYMBOL TEST CONDITIONS MAX UNITS CIN VIN = 0 V Thermal Impedance 1. VIH (max) = VCC +2.0V ac (pulse width < 10 ns) for I < 20 mA 2. VIL (min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA TABLE 5. 33LV408 CAPACITANCE PARAMETER Input Capacitance1 CS1 - CS4, OE, WE I/O0-7, I/O8-15, I/O16-23, I/O24-31 Memory (f = 1.0 MHZ, dV = 3.3 V, TA = 25 ° C) pF 7 28 7 Input / Output Capacitance1 COUT VI/O = 0 V 8 pF 1. Guaranteed by design. TABLE 6. 33LV408 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION SUBGROUPS MIN MAX UNIT Input Leakage Current ILI VIN = VSS to VCC 1, 2, 3 -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL, VOUT =VSS to VCC 1, 2, 3 -2 2 µA Output Low Voltage VOL IOL = 8mA 1, 2, 3 -- 0.4 V Output High Voltage VOH IOH = -4mA 1, 2, 3 2.4 -- V Operating Current -20 -25 -30 ICC Min cycle, 100% Duty, CS=VIL, IOUT=0mA, VIN = VIH or VIL 1, 2, 3 ---- 150 140 130 Standby Power Supply Current ISB CS = VIH, Min Cycle 1, 2, 3 -- 60 08.06.07 REV 3 mA mA All data sheets are subject to change without notice 3 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 6. 33LV408 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL CONDITION SUBGROUPS MIN MAX UNIT Standby Power Supply Current - CMOS ISB1 CS > VCC - 0.2V; VIN > VCC - 0.2V or VIN < 0.2V 1, 2, 3 -- 10 mA Input Capacitance 1 CIN VIN = 0V, f = 1MHz, TA = 25 °C 1, 2, 3 -- 7 pF Output Capacitance 1 CI/O VI/O = 0V 1, 2, 3 -- 8 pF 1. Guaranteed by design. TABLE 7. 33LV408 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) MIN TYP MAX UNITS Input Pulse Level 0.0 -- 3.0 V Output Timing Measurement Reference Level -- -- 1.5 V Input Rise/Fall Time -- -- 3.0 ns Input Timing Measurement Reference Level -- -- 1.5 V UNIT Memory PARAMETER TABLE 8. 33LV408 AC CHARACTERISTICS FOR READ CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL SUBGROUPS Read Cycle Time -20 -25 -30 tRC 9, 10, 11 Address Access Time -20 -25 -30 tAA Chip Select Access Time -20 -25 -30 tCO Output Enable to Output Valid -20 -25 -30 tOE Chip Enable to Output in Low-Z -20 -25 -30 tLZ MIN TYP MAX 20 25 30 ---- ---- ---- ---- 20 25 30 ---- ---- 20 25 30 ---- ---- 10 12 14 ---- 3 3 3 ---- ns ns 9, 10, 11 ns 9, 10, 11 9, 10, 11 ns 9, 10, 11 08.06.07 REV 3 ns All data sheets are subject to change without notice 4 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 8. 33LV408 AC CHARACTERISTICS FOR READ CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS Output Enable to Output in Low-Z -20 -25 -30 tOLZ 9, 10, 11 Chip Deselect to Output in High-Z -20 -25 -30 tHZ Output Disable to Output in High-Z -20 -25 -30 tOHZ Output Hold from Address Change -20 -25 -30 tOH Chip Select to Power Up Time -20 -25 -30 tPU Chip Select to Power Down Time -20 -25 -30 tPD MIN TYP MAX ---- 0 0 0 ---- ---- 5 6 8 ---- ---- 5 6 8 ---- 3 5 6 ---- ---- ---- 0 0 0 ---- ---- 10 15 20 ---- UNIT ns ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 Memory SYMBOL ns 9, 10, 11 ns 9, 10, 11 TABLE 9. 33LV408 FUNCTIONAL DESCRIPTION CS WE OE MODE I/O PIN SUPPLY CURRENT H X1 X1 Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L X1 Write DIN ICC L 1. X = don’t care. 08.06.07 REV 3 All data sheets are subject to change without notice 5 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 10. 33LV408 AC CHARACTERISTICS FOR WRITE CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS Write Cycle Time -20 -25 -30 tWC 9, 10, 11 Chip Select to End of Write -20 -25 -30 tCW Address Setup Time -20 -25 -30 tAS Address Valid to End of Write -20 -25 -30 tAW Write Pulse Width (OE High) -20 -25 -30 tWP Write Recovery Time -20 -25 -30 tWR Write to Output in High-Z -20 -25 -30 tWHZ Write Pulse Width (OE Low) -20 -25 -30 tWP1 Data to Write Time Overlap -20 -25 -30 tDW End Write to Output Low-Z -20 -25 -30 tOW MIN TYP MAX 20 25 30 ---- ---- 14 15 17 ---- ---- 0 0 0 ---- ---- 14 15 17 ---- ---- 14 15 17 ---- ---- 0 0 0 ---- ---- ---- 5 5 6 ---- ---- 20 25 30 ---- 9 10 11 ---- ---- ---- 6 7 8 ---- ns ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 ns 9, 10, 11 08.06.07 REV 3 UNIT Memory SYMBOL All data sheets are subject to change without notice 6 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 10. 33LV408 AC CHARACTERISTICS FOR WRITE CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE SPECIFIED) PARAMETER Data Hold from Write Time -20 -25 -30 SYMBOL SUBGROUPS tDH 9, 10, 11 MIN TYP MAX 0 0 0 ---- ---- UNIT ns FIGURE 1: TIMING WAVEFORM OF READ CYCLE(1) Memory FIGURE 2: TIMING WAVEFORM OF READ CYCLE (2) Read Cycle Notes: 1. WE is high for read cycle. 2. All read cycle timing is referenced form the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and from device to device. 5. 6. Transition is measured + 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention condition is necessary during read and write cycle. 08.06.07 REV 3 All data sheets are subject to change without notice 7 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM FIGURE 3: TIMING WAVEFORM OF WRITE CYCLE(1) Memory FIGURE 4: TIMING WAVEFORM OF WRITE CYCLE(2) 08.06.07 REV 3 All data sheets are subject to change without notice 8 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM FIGURE 5: TIMING WAVEFORM OF WRITE CYCLE (3) 1. 2. All write cycle timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low: A write ends at the earliest transition among CS going high and WE going high. t is measured from beginning of write to the end of write. t is measured from the later of CS going low to end of write. t is measured from the address valid to the beginning of write. t is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. D is the read data of the new address. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. WP 3. 4. 5. 6. 7. 8. 9. 10. CW AS WR OUT 08.06.07 REV 3 All data sheets are subject to change without notice 9 ©2007 Maxwell Technologies All rights reserved. Memory WRITE CYCLE NOTE: 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM Memory 32 PIN RAD-PAK® FLAT PACKAGE DIMENSION SYMBOL MIN NOM MAX A 0.122 0.135 0.155 b 0.015 0.017 0.019 c 0.008 0.010 0.012 D -- 0.930 0.940 E 0.635 0.645 0.655 E1 -- -- 0.690 E2 0.550 0.565 -- E3 -- 0.040 -- e 0.050 BSC L 0.390 0.400 0.410 Q 0.088 0.098 .108 S1 -- 0.082 -- N 32 Note: All dimensions in inches 08.06.07 REV 3 All data sheets are subject to change without notice 10 ©2007 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM 33LV408 Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 08.06.07 REV 3 All data sheets are subject to change without notice 11 ©2007 Maxwell Technologies All rights reserved. 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM Product Ordering Options Model Number 33LV408 XX F X -XX Option Details Feature 20 = 20 ns 25 = 25 ns 30 = 30 ns Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) Package F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 4 Megabit CMOS SRAM 08.06.07 REV 3 All data sheets are subject to change without notice Memory Access Time 12 ©2007 Maxwell Technologies All rights reserved.