56F6408 - FLASH NOR, 512 Mb

56F6408
512 Megabit
Flash NOR
DQ15 - DQ0 (A1)
VCC
VSS
VIO
RESET#
WE#
WP#
BYTE#
PINOUT
CE#
OE#
WP#
A24 - A0
Memory
cc
Functional Block Diagram
FEATURES:
DESCRIPTION:
• Single Power Supply Operation
Maxwell Technologies’ 56F6408 high density, 3.3V, 512
Megabit Flash Memory device, features a greater than
100 krads(Si) total dose tolerance, depending on space
mission. The 56F6408 is capable of in-system electrical
programming. It features Data Polling and a Ready/
Busy# signal to indicate the completion of erase and programming operations.
Single 3.3 volt read, erase, and program operations
• RAD-PAK® radiation hardened against natural
space radiation
• Total Dose Hardness
100 krads(Si), depending on space mission
• Single Event Effects
SEL > 60 MeV*cm2/mg at 85 °C
Maxwell Technologies’ patented RAD-PAK® packaging
technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding
while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK®
provides greater than 100 krad(Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies’ self-defined Class S.
• Flexible Sector Architecture
Five Hundred and Twelve 64K word sectors
• Hardware and Software Data Protection
• Package
56 Pin RAD-PAK® flat pack
• 100,000 Erase/Program Cycles per sector
(Typical)
• 20-year Data Retention (Typical)
• Low Power Consumption (Typical)
25mA read, 50mA erase/program, 1uA standby mode
• 8 and 16 Bit Data Bus Select
08.20.15 Rev 2
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56F6408
512 Megabit Flash NOR
Table of Contents
1. Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . 3
3. Absolute Maximum Ratings . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 4
3. DC Electricals . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. AC Electricals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 38
8. Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . 58
10. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11. Product Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Memory
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56F6408
512 Megabit Flash NOR
Table 1.
Table 2. Pin Description
DESCRIPTION
PIN
DESCRIPTION
1
A23
56
A24
2
A22
55
NC
3
A15
54
A16
4
A14
53
BYTE#
5
A13
52
Vss
6
A12
51
DQ15\A-1
7
A11
50
DQ7
8
A10
49
DQ14
9
A9
48
DQ6
10
A8
47
DQ13
11
A19
46
DQ5
12
A20
45
DQ12
13
WE#
44
DQ4
14
RESET#
43
Vcc
15
A21
42
DQ11
16
WP#
41
DQ3
17
RY\BY#
40
DQ10
18
A18
39
DQ2
19
A17
38
DQ9
20
A7
37
DQ1
21
A6
36
DQ8
22
A5
35
DQ0
23
A4
34
OE#
24
A3
33
Vss
25
A2
32
CE#
26
A1
31
A0
27
NC
30
NC
28
NC
29
Vcc
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Memory
PIN
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56F6408
512 Megabit Flash NOR
TABLE 3. 56F6408 Absolute Maximum Ratings 1
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply Voltage (Relative to Vss)
Vcc
-0.5
4.0
V
All other Pins
Output Short Circuit Current2
Storage Temperature
Operating Temperature
Thermal Resistance
Mass
--Tstg
Topr
Tjc
-0.5
--65
-55
Vcc + 0.5
200
150
125
1.3
9.9
V
mA
°C
°C
°C/W
Grams
Memory
1. Minimum DC voltage on input or I/O’s is -0.5V. During voltage transistions, inputs or I/O’s may overshoot Vss to 2.0V for periods of up to 20 ns. Maximum DC voltage on inputs or I/O’s is Vcc + 0.5 V. During voltage transistions,
inputs or I/O’s may overshoot to Vcc = +2.0 V for periods up to 20 ns.
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater
than one second.
Table 4. Delta Limits1
PARAMETER
VARIATION
Icc1
±10% of specified value in Table 5
Icc2
±10% of specified value in Table 5
Icc3
±10% of specified value in Table 5
Icc4
±10% of specified value in Table 5
Icc5
±10% of specified value in Table 5
Icc6
±10% of specified value in Table 5
1. Parameters are measured and recorded per MIL-STD-883 for Class S devices.
TABLE 5. 56F6408 Recommended Operating Conditions 1
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply Voltage
VCC
3.0
3.6
V
Input Low Voltage
VIL
0
0.3 x VCC
V
Input High Voltage
VIH
0.7 x VCC
VCC
V
TOPR
-55
125
°C
Operating Temperature Range
1. All unused control inputs of the device must be held high or low to ensure proper device operation.
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56F6408
512 Megabit Flash NOR
Table 6. 56F6408 DC Electrical Characteristics
(VCC = 3.3 ±0.3 TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
TEST CONDITIONS
SUBGROUPS
MIN
TYP
MAX
UNIT
Input Load Current1
All Inputs unless otherwise noted
ILI1
Vin = Vss to Vcc
Vcc = 3.6 V
1, 2, 3
1
uA
Input Load Current
WP
ILI2
Vin = Vss to Vcc
Vcc = 3.6 V
1, 2, 3
2
uA
Output Leakage
Current
ILO
Vout = Vss to Vcc;
Vcc = 3.6 V
1, 2, 3
-1
1
uA
CE# = VIL; OE# = VIH; VCC =
3.6 V, f = 1 MHz; Byte Mode
1, 2, 3
--
6
20
CE# = VIL; OE# = VIH; VCC =
3.6 V; f = 5 MHz; Byte Mode
--
30
50
CE# = VIL; OE# = VIH; VCC =
3.6 V; f = 10 MHz; Byte Mode
--
60
100
1
10
5
20
Vcc Active Read1
Current
Icc2
CE# = VIL ; OE# = VIH;
Vcc = 3.6 V; f = 10 MHz
1, 2, 3
CE# = VIL ; OE# = VIH;
Vcc = 3.6 V; f = 33 MHz
mA
mA
Vcc Active Erase/Program
Current2,3
Icc3
CE# = VIL ; OE# = VIH;
Vcc = 3.6 V
1, 2, 3
50
110
mA
Vcc Standby Current
Icc4
Vcc = 3.6 V;
Vil = Vss + 0.3 V / -0.1 V
CE#; = Vcc +/- 0.3V
1, 2, 3
1
128
uA
Vcc RESET Current
Icc5
Vcc = 3.6 V;
Vil = Vss + 0.3 V / -0.1 V
CE#; RESET# = Vcc +/- 0.3V
1, 2, 3
1
128
uA
Automatic Sleep Mode3
Icc6
Vcc = 3.6 V;
VIH = Vcc +/- 0.3V;
VIL = Vss + 0.3V/-0.1V
WP# = VIH
1, 2, 3
1
128
uA
Input Low Voltage
VIL
1, 2, 3
-0.1
.3 x
VCC
V
Input High Voltage
VIH
1, 2, 3
0.7x
VCC
VCC
+ .3
V
Output Low Voltage1
VOL
IOL = 100 uA
1, 2, 3
0.15
x
VCC
V
Output High Voltage1
VOH
IOH = 100 uA
1, 2, 3
0.85
x
VCC
Low Vcc Lock-out Voltage
VLKO
1, 2, 3
2.2
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Memory
Vcc Intra-Page Read
Current1
Icc1
V
2.9
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V
5
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56F6408
512 Megabit Flash NOR
1. The Icc current is typically less than 2 mA/MHz, with OE# at VIH.
2. Icc active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
3. Automatic sleep mode enables the lower power mode when addresses remain stable for t ACC + 30ns.
Memory
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56F6408
512 Megabit Flash NOR
Table 7. 56F6408 AC Electrical Characteristics
Read-Only Operation1
(VCC = 3.3 ±0.3, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
DESCRIPTION
SYMBOL
TEST CONDITIONS
SUBGROUPS
Read Cycle Time
tRC
VCC = 3 V
Address to Output
Delay
tACC
Chip Enable to Output
Delay
tCE
Page Access Time
MIN
UNIT
9, 10, 11
115
ns
VCC = 3 V
9, 10, 11
115
ns
VCC = 3 V
9, 10, 11
115
ns
tPACC
9, 10, 11
40
ns
Output Enable to Output Delay1
tOE
9, 10, 11
35
ns
Chip Enable to Output
High Z2
tDF
9, 10, 11
30
ns
Output Hold Time
from Addresses, CE#
or OE#, Whichever
Occurs First
tOH
9, 10, 11
0
ns
Output Enable Hold
Time2
tOEH
9, 10, 11
10
ns
Chip Enable Hold
Time2
tCEH
9, 10, 11
35
ns
Memory
MAX
1) 35PF LOAD
2) NOT 100% TESTED
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56F6408
512 Megabit Flash NOR
1.
Figure 1: Read Operation Timing
Memory
2.
Table 8. Hardware RESET (RESET#)
DESCRIPTION
SYMBLE
SUBGROUPS
RESET# PIN LOW (DURING EMBEDDED
ALGORITHMS) TO READ MODE1
tREADY
RESET# PIN LOW (NOT DURING EMBEDDED
ALGORITHMS) TO READ MODE
tREADY
RESET# Pulse Width
MIN
MAX
UNITS
9, 10, 11
20
ns
9, 10, 11
500
ns
tRP
9, 10, 11
500
ns
RESET High Time Before Read1
tRH
9, 10, 11
50
ns
Mode1
tRPD
9, 10, 11
20
ns
tRB
9, 10, 11
0
ns
RESET# Low to Standby
RDY/BZY# Recovery Time1
1. Not 100% tested. If ramp rate is equal or faster than 1V/100us with a falling edge of the RESET# pin initiated,
the RESET# input needs to be held low for 100 uS for power-up.
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56F6408
512 Megabit Flash NOR
Figure 2: Reset Timing
Memory
Table 9. Erase and Program Operations
DESCRIPTION
SYMBLE
SUBGROUPS
MIN
Write Cycle Time2
tWC
9, 10, 11
110
ns
Address Setup Time
tAS
9, 10, 11
0
ns
Address Setup Time to OE# low during toggle bit polling2
tASO
9, 10, 11
15
ns
Address Hold Time
tAH
9, 10, 11
45
ns
Address Hold Time From CE# or OE# high
during toggle bit polling2
tAHT
9, 10, 11
0
ns
Data Setup Time
tDS
9, 10, 11
45
ns
Data Hold Time
tDH
9, 10, 11
0
ns
CE# High during toggle bit polling2
tCEPH
9, 10, 11
20
ns
Output Enable High during toggle bit
polling2
tOEPH
9, 10, 11
20
ns
Read Recovery Time Before Write (OE#
High to WE# Low)2
tGHWL
9, 10, 11
2
ns
CE# Setup Time
tCE
9, 10, 11
0
ns
CE# Hold Time
tCH
9, 10, 11
0
ns
Write Pulse Width
tWP
9, 10, 11
35
ns
Write Pulse Width High
tWPH
9, 10, 11
30
ns
08.20.15 Rev 2
TYP
MAX1
UNITS
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56F6408
512 Megabit Flash NOR
Table 9. Erase and Program Operations
DESCRIPTION
SYMBLE
SUBGROUPS
Write Buffer Program Operation3
tWHWH1
9, 10, 11
MIN
TYP
MAX1
UNITS
240
900
us
Effective Write Buffer Program Operation
15
us
Program Operation
60
us
Sector Erase
VCC Setup
Operation4
Time2
Erase/Program Valid to RY/BY# Delay
tWHWH2
9, 10, 11
tVCS
9, 10, 11
tBUSY
9, 10, 11
0.5
50
sec
us
Chip Erase Time
256
Chip Program Time
492
1.
2.
3.
4.
3.5
100
ns
1100
sec
sec
Under worst case conditions of 125C, Vcc = 3.0 V, 75,000 cycles.
Not 100% Tested
For 1 -16 words/1 - 32 bytes programmed.
In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before eraser.
Figure 3: Program Operation Timings
Memory
General Description
The 56F6408 is a 3.0V single power flash memory manufactured using 110 nm technology. The 56F6408 is a 512
Mbit, organized as 33,554,432 words or 67,108,864 bytes. The devices have a 16-bit wide data bus that can also
function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system
or in standard EPROM programmers.
Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
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56F6408
512 Megabit Flash NOR
Figure 4: Chip/Sector Erase Operation Timings
Memory
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data.
2. These waveforms are for the word mode.
Figure 5: Data# Polling Timings (During Embedded Algorithms)
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data.
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56F6408
512 Megabit Flash NOR
Figure 6: Toggle Bit Timings (During Embedded Algorithms)
Memory
Notes
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence,
and last data read cycle.
Figure 7: DQ2 vs. DQ6
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
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56F6408
512 Megabit Flash NOR
Figure 10: Power-On Reset Timings
Note
The sum of tRP and tRH must be equal to or greater than tRPH
Memory
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56F6408
512 Megabit Flash NOR
Each device requires only a single 3.0 volt power supply for both read and write functions.
The devices are entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands
are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and
data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data
contents of other sectors. The device is programmed with a checkerboard Pattern when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase operation has
begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode
reduces command sequence overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of
any combination of sectors using a single power supply at VCC.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is
then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset
would thus also reset the device, enabling the host system to read boot-up firmware from the Flash
memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels on
CE# and RESET#, or when addresses have been stable for a specified period of time.
The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently
protected. Once this sector is protected, no further changes within the sector can occur.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP# pin.
The flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through
the internal command register. The command register itself does not occupy any addressable memory
location. The register is a latch used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the device. The following subsections describe
each of these operations in further detail.
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Memory
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given
sector to read or program any other sector and then complete the erase operation. The Program Suspend/
Program Resume feature enables the host system to pause a program operation in a given sector to read
any other sector and then complete the program operation.
56F6408
512 Megabit Flash NOR
Operation
CE#
Read
L
Write (Program/Erase)
L
Standby
Vcc +/‐ 0.3V
Output Disable
L
RESET#
X
OE#
L
H
X
H
X
WE#
H
L
X
H
X
RESET#
H
H
H
H
L
WP#
H
(Note 2)
Vcc +/‐ 0.3V
X
X
Address
Ain
Ain
H
X
X
DQ0‐DQ7
Dout
(Note 3)
High‐Z
High‐Z
High‐Z
DQ8 ‐ DQ15
BYTE# = Voh
BYTE# = Vil
Dout
DQ8‐DQ14 ‐ High‐Z
(Note 3)
DQ15 = A‐1
High‐Z
High‐Z
High‐Z
High‐Z
High‐Z
High‐Z
Legend
L = Logic Low = VIL, H = Logic High = VIH, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes
1. Addresses are AMax:A0 in word mode; AMax:A-1 in byte mode. Sector addresses are AMax:A16 in both modes.
2. If WP# = VIL, the first remains protected. I All sectors are protected when shipped from the factory (using PPB bits).
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm.
Word/Byte Configuration
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and
selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert
valid addresses on the device address nputs produce valid data on the device data outputs. The device
remains enabled for read access until the command register contents are altered.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode
provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The
appropriate page is selected by the higher address bits A(max)–A3. Address bits A2–A0 in word mode (A2–A-1 in byte mode)
determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word
location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations
specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a
subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of
memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode
to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “Word Program Command Sequence” section has details on
programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
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Memory
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at
logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at
logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The
data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
56F6408
512 Megabit Flash NOR
Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section
contains timing specification tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This
results in faster effective programming time than the standard programming algorithms.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect
codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in
this mode.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that
this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the
If the device is deselected during erasure or programming, the device draws active current until the operation is
completed.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is
driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal
state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws
CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance
state.
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device is in the standby mode, but the standby current is greater. The device requires standard access time (tCE) for
read access when the device is in either of these standby modes, before it is ready to read data.
56F6408
512 Megabit Flash NOR
Table 9: 56F6408 Sector Address (1 of 11)
Memory
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56F6408
512 Megabit Flash NOR
Table 10: 56F6408 Sector Address (2 of 11)
Memory
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56F6408
512 Megabit Flash NOR
Table 11: 56F6408 Sector Address (3 of 11)
Memory
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512 Megabit Flash NOR
Table 12: 56F6408 Sector Address (4 of 11)
Memory
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56F6408
512 Megabit Flash NOR
Table 13: 56F6408 Sector Address (5 of 11)
Memory
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56F6408
512 Megabit Flash NOR
Table 14: 56F6408 Sector Address (6 of 11)
Memory
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512 Megabit Flash NOR
Table 15: 56F6408 Sector Address (7 of 11)
56F6408
Memory
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56F6408
512 Megabit Flash NOR
Table 16: 56F6408 Sector Address (8 of 11)
Memory
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56F6408
512 Megabit Flash NOR
Table 17: 56F6408 Sector Address (9 of 11)
Memory
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56F6408
512 Megabit Flash NOR
Table 18: 56F6408 Sector Address (10 of 11)
Memory
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56F6408
512 Megabit Flash NOR
Table 19: 56F6408 Sector Address (11 of 11)
Memory
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56F6408
512 Megabit Flash NOR
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost sectors. The WP# Hardware Protection feature is
always available, independent of the software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. Password Protection is not supported. It is recommended to
program/select the Persistent Sector protection mode.
The device is shipped with all sectors write protected.
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase
operations in certain sectors.
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ1, DQ0 bits of the Lock Register are programmable by the
user. Users shall not program DQ2. The programming time of the Lock Register is same as the typical word programming time
without utilizing the Write Buffer of the device. During a Lock Register programming sequence execution, the DQ6 Toggle Bit I
toggles until the programming of the Lock Register has completed to indicate programming status. All Lock Register bits are
readable to allow users to verify Lock Register statuses.
- Secured Silicon Sector Protection allows the user to lock the Secured Silicon Sector area
- Persistent Protection Mode Lock Bit allows the user to set the device permanently to operate in the
Persistent Protection Mode
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The Customer Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1 are accessible by all
users. Each of these bits are non-volatile. DQ15-DQ2 are reserved and must be 1's when the user tries to program the DQ1, and
DQ0 bits of the Lock Register. The user is not required to program DQ1 and DQ0 bits of the Lock Register at the same time. This
allows users to lock the Secured Silicon Sector and then set the device either permanently into Persistent Protection Mode and then
lock the Secured Silicon Sector at separate instances and time frames.
56F6408
512 Megabit Flash NOR
Table 20: Lock Register
DQ15
DQ-3- 3
DQ-2
Don't Care
1
1
DQ-1
Persistence Protection Mode
Lock Bit
DQ-0
Secured Silicon Sector
Protection Bit
1) Reserved Bit - Never write 0 to this bit.
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing
flexibility by providing three different sector protection states:
Dynamically Locked-The sector is protected and can be changed by a simple command
Persistently Locked-A sector is protected and cannot be changed
Unlocked-The sector is unprotected and can be changed by a simple command
In order to achieve these states, three types of “bits” are going to be used:
Dynamic Protection Bit (DYB)
The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors
that have the PPB bits cleared, the DYB bits control whether or not the sector is protected or unprotected. By issuing the DYB Set
and DYB Clear command sequences, the DYB bits is protected or unprotected, thus placing each sector in the protected or
unprotected state. These are the socalled Dynamic Locked or Unlocked states. They are called dynamic states because it is very
easy to switch back and forth between the protected and un-protected conditions. This allows software to easily protect sectors
against inadvertent changes yet does not prevent the easy removal of protection when changes are needed.
The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a more static, and difficult to change, level of
protection. The PPB bits retain their state across power cycles because they are Non-Volatile. Individual PPB bits are set with a
program command but must all be cleared as a group through an erase command.
The PPB Lock Bit adds an additional level of protection. Once all PPB bits are programmed to the desired settings, the PPB Lock
Bit may be set to the “freeze state”. Setting the PPB Lock Bit to the “freeze state” disables all program and erase commands to the
Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the PPB bits into their current state. The only way to clear the PPB Lock
Bit to the “unfreeze state” is to go through a power cycle, or hardware reset. The Software Reset command does not clear the PPB
Lock Bit to the “unfreeze state”. System boot code can determine if any changes to the PPB bits are needed e.g. to allow new
system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock Bit to disable any further
changes to the PPB bits during system operation.
The WP# write protect pin adds a final level of hardware protection. When this pin is low it is not possible to change the contents
of the WP# protected sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot
code that could override the choices made while setting up sector protection during system initialization.
It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the
dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is
necessary. The DYB Set and DYB Clear commands for the dynamic sectors switch the DYB bits to signify protected and
unprotected, respectively. If there is a need to change the status of the persistently locked ctors, a few more steps are required.
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A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYB bits are in the
“unprotected state”. Each DYB is individually modifiable through the DYB Set Command and DYB Clear Command. When the
parts are first shipped, all of the Persistent Protect Bits (PPB) are cleared into the unprotected state. The DYB bits and PPB Lock
bit are defaulted to power up in the cleared state or unprotected state - meaning the all PPB bits are changeable.
56F6408
512 Megabit Flash NOR
Table 21: Sector Protect Schemes
The Autoselect Sector Protection Verification outputs the OR function of the DYB bit and PPB bit per sector basis. When the OR
function of the DYB bit and PPB bit is a 1, the sector is either protected by DYB or PPB or both. When the OR function of the
DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB and PPB.
Persistent Protection Mode Lock Bit
The Persistent Protection Mode Lock Bit exists to guarantee that the device remain in software sector protection.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit.
The device defaults to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit is cleared to the unfreeze
state after power-up or hardware reset. The PPB Lock Bit is set to the freeze state by issuing the PPB Lock Bit Set command. Once
set to the freeze state the only means for clearing the PPB Lock Bit to the “unfreeze state” is by issuing a hardware or power-up
reset. Reading the PPB Lock Bit requires a 200ns access time.
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an
Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit
(DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. Bytes 0 - 23 are factory
reserved.
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The above table contains all possible combinations of the DYB bit, PPB bit, and PPB Lock Bit relating to the status of the sector. In
summary, if the PPB bit is set, and the PPB Lock Bit is set, the sector is protected and the protection cannot be removed until the
next power cycle or hardware reset clears the PPB Lock Bit to “unfreeze state”. If the PPB bit is cleared, the sector can be
dynamically locked or unlocked. The DYB bit then controls whether or not the sector is protected or unprotected. If the user
attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to
a protected sector enables status polling for approximately 1 μs before the device returns to read mode without having modified the
contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 μs after which
the device returns to read mode without having erased the protected sector. The programming of the DYB bit, PPB bit, and PPB
Lock Bit for a given sector can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock Status Read commands
to the device.
56F6408
512 Megabit Flash NOR
This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the field.
The factory offers the device with the Secured Silicon Sector customer lockable. The customer lockable version is shipped with the
Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable
version also has the Secured Silicon Sector Indicator Bit permanently set to a 0. Thus, the Secured Silicon Sector Indicator Bit
prevents customer-lockable devices from being used to replace devices that are factory locked. The Secured Silicon sector address
space in this device is allocated as follows:
TABLE 1. SECURED SILICON ADDRESS RANGE
0h - 17h
Reserved
018h - 7Fh
User
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected
At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte Secured Silicon
sector minus the factory reserved 24 bytes. The system may program the Secured Silicon Sector using the write-buffer, unlock
bypass methods, in addition to the standard programming command sequence.
Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure
available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be
modified in any way.
The Secured Silicon Sector area can be protected using one of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region command.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm.
Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region
command sequence to return to reading and writing within the remainder of the array.
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The system accesses the Secured Silicon Sector through a command sequence. After the system has written the
Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses
normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit Secured
Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware
reset, the device reverts to sending commands to sector SA0.
56F6408
512 Megabit Flash NOR
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first sector. Write Protect is one of two
functions provided by the WP# input. If the system asserts VIL on the WP# pin, the device disables program and erase
functions in the first sector group independently of whether those sector groups were protected or unprotected using
the method. Note that if WP# is at VIL when the device is in the standby mode, the maximum input load current is
increased.
If the system asserts VIH on the WP# pin, the device reverts to whether the first sector was previously set
to be protected or unprotected. Note that WP# has an internal pull-up; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during VCC power-up and powerdown transitions, or from system noise.
Low VCC Write Inhibit
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and
WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows
specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device
is ready to read array data. To terminate reading CFI data, the system must write the reset command. The system can also write the
CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI
data at the addresses. The system must write the reset command to return the device to reading array data.
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When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to
the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. The RESET# input pin may
be used when VLKO is exceeded but control signals are unstable.
56F6408
512 Megabit Flash NOR
Table 22: CFI Query Identification String
Table 23: System Interface String
Memory
Note: Values are for commercial specifications. See AC/DC specifications in this document for actuals.
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512 Megabit Flash NOR
Table 24: Primary Vendor-Specific Extended Query
Memory
Reserved
Reserved
WP# Protection
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Writing incorrect
address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is
then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever
happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics
section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device
is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can
read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system
may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more
information.
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512 Megabit Flash NOR
The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes
high during an active program or erase operation, or if the device is in the autoselect mode. See the next section,
Reset Command, for more information.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this
command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets
the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins.
This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend
mode, writing the reset command returns the device to the erasesuspend-read mode. Once programming begins, however, the
device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode,
the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend
mode, writing the reset command returns the device to the erase-suspend-read mode.
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-toBuffer-Abort Reset command sequence to reset the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or
not a sector is protected. The autoselect command sequence may be written to an address that is either in the read or erase-suspendread mode. The autoselect command may not be written while the device is actively programming or erasing.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that
contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of
times without initiating another autoselect command sequence:
- A read cycle at address XX00h returns the manufacturer code.
- Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code.
- A read cycle to an address containing a sector address (SA), and the address 02h on A7–A0 in word mode returns
01h if the sector is protected, or 00h if it is unprotected.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in
Erase Suspend).
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If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erasesuspend-read mode if the device was in Erase Suspend).
56F6408
512 Megabit Flash NOR
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random Electronic
Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter
Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until
the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector
command sequence returns the device to normal operation.
Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles,
followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded
Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally
generated program pulses and verifies the programmed cell margin. When the Embedded Program algorithm is complete, the
device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program
operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands
written to the device during the Embedded Program Algorithm are ignored. Note that the Secured Silicon Sector, autoselect,
and CFI functions are unavailable when a program operation is in progress. Note that a hardware reset immediately
terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program command
sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass
program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock
bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the
unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence.
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Programming is allowed in any sequence of address locations and across sector boundaries. Programming to the same word
address multiple times without intervening erases (incremental bit programming) is permitted. Word programming is supported for
backward compatibility with existing Flash driver software and for occasional writing of individual words. Use of Write Buffer
Programming is faster for general programming use when more than a few words are to be programmed. The effective
word programming time using Write Buffer Programming is much shorter than the single word programming time. Any bit
cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase
operations can convert a 0 to a 1.
56F6408
512 Megabit Flash NOR
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This
results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command
sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming occurs. The fourth cycle writes the sector address and the number
of word locations, minus one, to be programmed. For example, if the system programs six unique address locations, then 05h
should be written to the device. This tells the device how many write buffer addresses are loaded with data and therefore when to
expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the
operation aborts.
The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits
AMAX–A4. All subsequent address/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining
address/data pairs into the write buffer. Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer
Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be
performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the
operation aborts.)
Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash
command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The
device then begins programming. Data polling should be used while monitoring the last address location loaded into the write
buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming.
The write-buffer programming operation can be suspended using the standard program suspend/resume
commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
- Load a value that is greater than the page buffer size during the Number of Locations to Program step.
- Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
- Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address
during the write buffer data loading stage of the operation.
- Write data other than the Confirm Command after the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A
Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation.
Write buffer programming is allowed in any sequence. Note that the Secured Silicon sector, autoselect, and CFI functions are
unavailable when a program operation is in progress. This flash device is capable of handling multiple write buffer programming
operations on the same write buffer address range without intervening erases. Any bit in a write buffer address range cannot be
programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status
bits to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase operations can
convert a 0 to a 1.
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Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decremented for every data
load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements
for each data load operation, not for each unique writebuffer-address location. Note also that if an address location is loaded more
than once into the buffer, the final data loaded for that address is programmed.
56F6408
512 Megabit Flash NOR
Figure 11: Write Buffer Programming Operation
Memory
Notes
1. When Sector Address is specified, any address in the selected sector is acceptable.
However, when loading Write-Buffer address locations with data, all addresses must fall
within the selected Write-Buffer Page.
2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.
3. If this flowchart location was reached because DQ5= 1, then the device FAILED. If this
flowchart location was reached because DQ1= 1, then the Write to Buffer operation was
ABORTED. In either case, the proper reset command must be written before the device can
begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.
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512 Megabit Flash NOR
Figure 12: Program Operation
Memory
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming
operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a
programming process, the device halts the program operation within 15 μs maximum (5 μs typical) and updates the status bits.
Addresses are not required when writing the Program Suspend command.
After the programming operation is suspended, the system can read array data from any non-suspended sector. The
Program Suspend command may also be issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the
Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter
and exit this region. Note that the Secured Silicon Sector autoselect, and CFI functions are unavailable when program
operation is in progress.
The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can
read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation.
After the Program Resume command is written, the device reverts to programming. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits, just as in the standard program operation.
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56F6408
512 Megabit Flash NOR
The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend
mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resume programming.
Figure 13: Program Suspend/Program Resume
Memory
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming
operation so that data can be read from any non-suspended sector. When the Program uspend command is written during a
programming process, the device halts the program operation within 15 μs maximum (5 μs typical) and updates the status bits.
Addresses are not required when writing the Program Suspend command.
After the programming operation is suspended, the system can read array data from any non-suspended sector. The Program
Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read
from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time
Program area), then user must use the proper command sequences to enter and exit this region. Note that the Secured Silicon
Sector autoselect, and CFI functions are unavailable when program operation is in progress.
The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can
read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation.
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56F6408
512 Megabit Flash NOR
After the Program Resume command is written, the device reverts to programming. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits, just as in the standard program operation.
The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue
the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be
written after the device has resume programming.
Figure 14: Program Suspend/Program Resume
Memory
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512 Megabit Flash NOR
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations.
When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The
system can determine the status of the erase operation by using DQ7, DQ6, or DQ2.
Any commands written during the chip erase operation are ignored, including erase suspend commands. However, note that a
hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should
be reinitiated once the device has returned to reading array data, to ensure data integrity.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation in is
progress.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command.
After the command sequence is written, a sector erase time-out of 50 μs occurs. During the time-out period, additional
sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles
must be less than 50 μs, otherwise erasure may begin. Any sector erase address and command following the
exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this
time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the
read mode. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an erase
operation in is progress. The system must rewrite the command sequence and any additional addresses and
commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. The time-out begins from the rising
edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer latched. The system can determine the status of the erase
operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for
information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command
sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
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Memory
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data pattern prior to electrical erase.The system is not required
to provide any controls or timings during these operations.
56F6408
512 Megabit Flash NOR
Figure 15: Erase Operation
Memory
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data
to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 μs time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 s maximum of 20
s) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the
device immediately terminates the time-out period and suspends the erase operation.
After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can read data from or program
data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address
within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation.
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512 Megabit Flash NOR
In the erase-suspend-read mode, the system can also issue the autoselect command sequence.To resume the sector erase operation,
the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this
command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has
resumed erasing. It is important to allow an interval of at least 5 ms between Erase Resume and Erase Suspend.
Lock Register Command Set Definitions
The Lock Register Command Set permits the user to one-time program the Secured Silicon Sector Protection Bit, Persistent
Protection Mode Lock Bit. The Lock Register bits are all readable after an initial access delay.
The Lock Register Command Set Entry command sequence must be issued prior to any of the following commands
listed, to enable proper command execution.
Note that issuing the Lock Register Command Set Entry command disables reads and writes for the flash memory.
Lock Register Program Command
Lock Register Read Command
Note that only the Persistent Protection Mode Lock Bitcan be programmed. The Lock Register Program operation
aborts if there is an attempt to program the Persistent Protection Mode.
The Lock Register Command Set Exit command must be initiated to re-enable reads and writes to the main
memory.
Non-Volatile Sector Protection Command Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the Persistent Protection Bits (PPB bits),
erase all of the Persistent Protection Bits (PPB bits), and read the logic state of the Persistent Protection Bits (PPB
bits).
The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the
commands listed following to enable proper command execution. Note that issuing the Non-Volatile Sector Protection
Command Set Entry command disables reads and writes for the main memory.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB bit. Each PPB bit is individually programmed (but is bulk
erased with the other PPB bits). The specific sector address (A22 - A16) is written at the same time as the program command. If the
PPB Lock Bit is set to the freeze state, the PPB Program command does not execute and the command times-out without
programming the PPB bit.
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Memory
The Lock Register Command Set Exit command must be issued after the execution of the commands to reset the
device to read mode. Otherwise the device hangs. If this happens, the flash device must be reset. Please refer to
RESET# for more information. For either the Secured Silicon Sector to be locked, or the device to be permanently set
to the Persistent Protection Mode the associated Lock Register bits must be programmed.
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512 Megabit Flash NOR
All PPB Erase Command
The All PPB Erase command is used to erase all PPB bits in bulk. There is no means for individually erasing a specific PPB bit.
Unlike the PPB program, no specific sector address is required. However, when the All PPB Erase command is issued, all Sector
PPB bits are erased in parallel. If the PPB Lock Bit is set to freeze state, the ALL PPB Erase command does not execute and the
command times-out without erasing the PPB bits.
The device preprograms all PPB bits prior to erasing when issuing the All PPB Erase command. Also note that the total number of
PPB program/erase cycles has the same endurance as the flash memory array.
PPB Status Read Command
The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the
device. This requires an initial access time latency.
The Non-Volatile Sector Protection Command Set Exit command must be issued after the execution of the
commands listed previously to reset the device to read mode.
Note that issuing the Non-Volatile Sector Protection Command Set Exit command re-enables reads and writes for the
main memory.
The Global Volatile Sector Protect on Freeze Command Set permits the user to set the PPB Lock Bit and reading the
logic state of the PPB Lock Bit. The Global Volatile Sector Protection Freeze Command Set Entry command sequence
must be issued prior to any of the commands listed following to enable proper command execution. Reads and writes
from the main memory are not allowed.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock Bit to the freeze state if it is cleared at reset. There is no
PPB Lock Bit Clear command. Once the PPB Lock Bit is set to the freeze state, it cannot be cleared unless the device
is taken through a power-on clear (for Persistent Protection Mode).
PPB Lock Bit Status Read Command
The programming state of the PPB Lock Bit can be verified by executing a PPB Lock Bit Status Read command to the
device.
The Global Volatile Sector Protection Freeze Command Set Exit command must be issued after the execution of
the commands listed previously to reset the device to read mode.
Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB) to the protected
state, clear the Dynamic Protection Bit (DYB) to the unprotected state, and read the logic state of the Dynamic
Protection Bit (DYB).
The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the
commands listed following to enable proper command execution.
Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes from main
memory.
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Memory
Global Volatile Sector Protection Freeze Command Set
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512 Megabit Flash NOR
DYB Set Command / DYB Clear Command
The DYB Set and DYB Clear commands are used to protect or unprotect a given sector. The high order address bits
are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the
data write cycle. The DYB bits are modifiable at any time, regardless of the state of the PPB bit or PPB Lock Bit. The
DYB bits are cleared to the unprotected state at power-up or hardware reset.
DYB Status Read Command
The programming state of the DYB bit for a given sector can be verified by writing a DYB Status Read command to the
device. This requires an initial access delay.
The Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed
previously to reset the device to read mode.
Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes to the main
memory.
Secured Silicon Sector Entry Command
The Secured Silicon Sector Entry command allows the following commands to be executed
- Program to Secured Silicon Sector
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command has to be issued
to exit Secured Silicon Sector Mode.
Secured Silicon Sector Exit Command
The Secured Silicon Sector Exit command may be issued to exit the Secured Silicon Sector Mode.
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Memory
- Read from Secured Silicon Sector
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512 Megabit Flash NOR
Command Definitions
Table 25: Memory Array Commands (x16)
Memory
Legend
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the falling edge of WE# or CE# pulse, whichever occurs later.
PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.
SA = Sector Address. Any address that falls within a specified sector.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write
the reset command to return reading array data.
5. No unlock or command cycles required when bank is reading array data.
6. Reset command is required to return to reading array data in certain cases.
7. Data in cycles 5 and 6 are listed.
8. The data is 00h for an unprotected sector and 01h for a protected sector. PPB Status Read provides the same data but in inverted form.
9. If DQ7 = 1, region is factory serialized and protected. If DQ7 = 0, region is unserialized and unprotected when shipped from factory.
10.Command is valid when device is ready to read array data or when device is in autoselect mode.
11. Total number of cycles in the command sequence is determined by the number of words written to the write buffer.
12.Command sequence resets device for next command after write-to-buffer operation.
13.Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data.
14.System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
15.Erase Resume command is valid only during the Erase Suspend mode.
16.Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may
otherwise be placed in an unknown state.
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Commad Sequence
Lock
Register Bits
Non‐volatile
Sector
Protection
(PPB)
Volatile Sector
Protection
(DYB)
3
2
1
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
Bus Cycle
Second
First
Addr
555
XX
0
XX
555
XX
XX
SA
XX
555
XX
XXX
XX
555
xx
XX
SA
XX
Data
AA
A0
Data
90
AA
A0
80
RD(0)
90
AA
A0
RD(0)
90
AA
a0
A0
RD(0)
90
Addr
2AA
XXX
Data
55
Data
XXX
2AA
SA
0
00
55
00
30
XX 2AA
XX
00
55
00
XX
2AA
sa
SA
00
55
00
01
XX
00
Third
Addr
555
Data
40
555
C0
555
50
555
E0
Memory
Global
Volatile Sector
Protection Freeze
(PPB Lock)
Command Set Entry
Program
Read
Command Set Exit
Command Set Entry
PPB Program
All PPB Erase
PPB Status Read
Command Set Exit
Command Set Entry
PPB Lock Bit Set
PPB Lock Bit Status Read
Command Set Exit
Command Set Entry
DYB Set
DYB Clear
DYB Status Read
Command Set Exit
CYCLES
Table 26: Sector Protection Commands (x16)
Legend
X = Don’t Care
RA = Address of the memory location to be read
SA = Sector Address. Any address that falls within a specified sector.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If unprotected, DQ0 = 1.
NOTES
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state.
The system must write the reset command to return the device to reading array data.
5. Entry commands are required to enter a specific mode to enable instructions only available within that mode.
6. No unlock or command cycles required when bank is reading array data.
7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state.
8. “All PPB Erase” command pre-programs all PPB’s before erasure to prevent over-errasure.
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512 Megabit Flash NOR
Table 27: Memory Array Commands (x8)
Memory
Legend
X = Don’t care
RA = Read Address
RD = Read Data
PA = Program Address. Addresses latch on the falling edge of WE# or CE# pulse, which ever comes first.
PD = Program Data. Data Lartches on the rising edge of WE# or CE# which ever comes first..
SA = Sector Address. Any address that falls within a specified sector.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend or notes are don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect addresses or data values or writing them in an improper sequence may place the device in an unknown state. The system
must write the reset command to return reading array data.
5. No unlock or command cycles required when bank is reading array data.
6. Reset command is required to return to reading array data in certain cases.
7. The data is 00h for an onprotected sector. PPB Stus Read provides the same data but in inverted form.
8. If DQ7 = 1, region is factory serialized and protected. If DQ7 = 0, region is unserialized and unprotected when shipped from factory.
9. Command is valid when device is ready to read array data or when device is in autoselect mode.
10. Total number of cycles in the command sequence is determined by the number of words written to the write buffer.
11. Command sequence resets device for next command after write-to-buffer operation.
12. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data.
13. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. TheErase
Suspend is valid only during a sector erase operation.
14. Erase Resume command is valid only during the Erase Suspend mode.
15. Requires Entry command sequence prior to execution. Secure Silicon Sector Exit Reset command is reqquired to exit this mode ;
device may otherwise be placed in an unknown state.
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512 Megabit Flash NOR
Table 28. Sector Protection Commands (x8)
Memory
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512 Megabit Flash NOR
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. DQ7
and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also
provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress
or is completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or
completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the
command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This
DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If
a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 μs, then the device returns to
the read mode.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 μs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at
an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7
appears on successive read cycles.
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Memory
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is
complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid status information on DQ7.
56F6408
512 Megabit Flash NOR
Figure 16: Data# Polling Algorithm
Memory
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the
sector being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ& may change simultaneously with DQ5.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete.
The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain
output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend
mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode.
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512 Megabit Flash NOR
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The
system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 μs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device
is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is
written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the
Embedded Program algorithm is complete.
Memory
Figure 17:Toggle Bit Algorithm
The system should recheck the toggle bit evn if DQ5 = 1 because the toggle bit may stop toggling
as DQ5 changes to 1.
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512 Megabit Flash NOR
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use
either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode information.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether
a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to
0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when
the timing limit is exceeded, DQ5 produces a 1.
In all these cases, the system must write the reset command to return the device to the reading the array (or to erasesuspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has
begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is
complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be
assumed to be less than 50 μs, the system need not monitor DQ3.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure that the device has
epted the command sequence, and then read DQ3.
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Memory
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation
successfully, and the system must write the reset command to return to reading array data.
56F6408
512 Megabit Flash NOR
If DQ3 = 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are
ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase
commands. To ensure the command is accepted, the system software should check the status of DQ3 prior
to and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1. The
system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data.
Table 29: Write Operation Status
Memory
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation.
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56F6408
512 Megabit Flash NOR
POD
Memory
56 PIN RAD-PAK® FLAT PACKAGE
SYMBOL
DIMENSION
MIN
NOM
MAX
A
0.156
0.175
0.194
b
0.006
0.008
0.010
c
0.005
0.006
0.008
D
0.817
0.825
0.833
e
0.025 BCS
E
0.544
0.550
0.556
L
--
0.460
--
Q
0.014
0.021
0.027
S
0.005
0.070
--
Note: All dimensions in inches
Top and Bottom of the package are connected internally to ground.
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56
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56F6408
512 Megabit Flash NOR
Important Notice:
These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
Memory
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57
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56F6408
512 Megabit Flash NOR
Product Ordering Options
Model Number
56F6408
RP
F
X
Option Details
Feature
Screening Flow
Monolithic1
S = Maxwell Class S
B = Maxwell Class B
I = Industrial (testing @ -55°C, +25°C, +125°C)
E = Engineering (testing @ +25°C)
Memory
F = Flat Pack
Package
Radiation Feature
RP = RAD-PAK® package
Base Product
Nomenclature
512 Megabit Flash NOR
1) Products are manufactured and screened to Maxwell Technolgies’ self-defined Class B and Class S.
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