69F1608 - FLASH, 128 Mb (16Mb x 8)

69F1608
128 Megabit (16M x 8-Bit)
Flash Memory Module
FEATURES:
DESCRIPTION:
• Single 5.0 V supply
Maxwell Technologies’ 69F1608 high-performance flash memory is a 16M x 8-bit NAND Flash Memory with a spare 128K
(131,072) x 8-bit. A program operation programs the 528-byte
page in 250 µ s and an erase operation can be performed in 2
ms on an 8K-byte block. Data within a page can be read out at
50 ns cycle time per byte. The on-chip write controller automates all program and erase functions, including pulse repetition, where required, and internal verify and margining of data.
Even write-intensive systems can take advantage of the
69F1608’s extended reliability of 1,000,000 program/erase
cycles by providing either ECC (Error Correction Code) or real
time mapping-out algorithm. These algorithms have been
implemented in many mass storage applications. The spare
16 bytes of a page combined with the other 512 bytes can be
utilized by system-level ECC. The 69F1608 is an optimum
solution for large non-volatile storage applications such as
solid state data storage, digital voice recorders, digital still
cameras and other applications requiring nonvolatility.
• Organization:
•
•
•
•
•
•
•
- Memory cell array: (4M + 128k) bit x 8bit
- Data register: (512 + 16) bit x 8bit
- Contains 4 (32 Megabit) Die
Automatic program and erase
- Page program: (512 + 16) Byte
- Block erase: (8K + 256) Byte
- Status register
528-Byte page read operation
- Random access: 10 µ s (max)
- Serial page access: 50 ns (min)
Fast write cycle time
- Program time: 250 µ s (typ)
- Block erase time: 2 ms (typ)
Command/address/data multiplexed I/O port
Hardware data protection
- Program/erase lockout during power transitions
Reliable CMOS floating-gate technology
- Endurance: 1,000,000 program/erase cycles
- Data retention: 10 years
Command register operation
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. Capable of surviving in space environments, the
69F1608 is ideal for satellite, spacecraft, and space probe
missions. It is available with packaging and screening up to
Maxwell Technologies self-defined Class K.
03.07.08 REV 3
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Memory
Logic Diagram (1 of 4 Die)
128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
TABLE 1. PINOUT DESCRIPTION
PIN
SYMBOL
DESCRIPTION
1
VSS
Ground
2
Command Latch Enable
(CLE)
The CLE input controls the path activation for commands sent to
the command register. When active high, commands are latched
into the command register through the I/O ports on the rising
edge of the WE signal.
3
Address Latch Enable
(ALE)
The ALE input controls the path activation for address and input
data to the internal address/data register. Addresses are latched
on the rising edge or WE with ALE high, and input data is latched
when ALE is low.
4
Write Enable
(WE)
The WE input controls writes to the I/O port. Commands,
address and data are latched on the rising edge of the WE
pulse.
5
Write Protect
(WP)
The WP pin provides inadvertent write/erase protection during
power transitions. The internal high voltage generator is reset
when the WP pin is active low.
6, 7, 18, 19
Chip Enable Inputs
The CE input is the device selection control. When CE goes high
during a read operation, the device is returned to standby mode.
However, when the device is in the busy state during program or
erase, CE high is ignored, and does not return the device to
standby mode.
CE1 - CE4
8, 9, 10, 11
14, 15, 16, 17
I/O Port:
I/O0 ~I/O7
The I/O pins are used to input command, address and data, and
to output data during read operations. The I/O pins float to HighZ when the chip is deselected or when the outputs are disabled.
12
VSS
Ground
13
VCCQ
Output Buffer Voltage
20
Spare Area Enable (SE)
The SE input controls the spare area selection when SE is high,
the device is deselected the spare area during Read1, Sequential data input and page Program.
21
Read/Busy
(R/B)
The R/B output indicates the status of the device operation.
When low, it indicates that a program, erase or random read
operation is in process and returns to high state upon completion. It is an open drain output and does not float to High-Z condition when the chip is deselected or when outputs are disabled.
22
Read Enable
(RE)
The RE inputs is the serial data-out control, and when active
drives the data onto the I/O bus. Data is valid tREA after the falling
edge of RE which also increments the internal column address
counter by one.
23
NC
No Connection
24
Vcc
Supply Voltage
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69F1608
128 Megabit (16M x 8-Bit) Flash Memory Module
TABLE 2. 69F1608 ABSOLUTE MAXIMUM RATINGS 1,2
PARAMETER
SYMBOL
MIN
MAX
UNIT
VIN
-0.6
7.0
V
Operating Temperature
TBIAS
-40
125
°C
Storage temperature
TSTG
-65
150
°C
IOS
--
5
mA
Voltage on any pin relative to VSS
Short circuit output current
1. Minimum DC voltage is -0.3 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 30 ns.
Maximum DC voltage on input/output pins is VCC + 0.3 V which, during transitions, may overshoot to VCC + 2.0 V for periods <
20 ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect reliability.
TABLE 3. 69F1608 RECOMMENDED OPERATING CONDITIONS
(VCC = 5 V ± 10%, TA = -40 TO 125° C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Supply voltage
VCC
4.5
5.0
5.5
V
Supply voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.4
--
VCC ±0.5
V
Input Low Voltage
VIL
-0.3
--
0.8
V
TABLE 4. DELTA LIMITS
PARAMTER
CONDITION
ICC1
±10%
ISB1
±10%
ISB2
±10%
TABLE 5. 69F1608 AC TEST CONDITION
(VCC = 5 V ± 10%, TA = -40 TO 125° C, UNLESS OTHERWISE NOTED)
PARAMETER
MIN
MAX
UNIT
Input pulse levels
0.4
2.6
V
Input rise times
--
5.0
ns
0.8
2.0
V
Input and output timing levels
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69F1608
128 Megabit (16M x 8-Bit) Flash Memory Module
TABLE 6. 69F1608 DC AND OPERATING CHARACTERISTICS
(VCC = 5 V ± 10%, TA = -40 TO 125° C, UNLESS OTHERWISE NOTED)
PARAMETER
Operating current1
SYMBOL
Sequential
read
ICC1
Program
ICC2
Erase
ICC3
TEST CONDITIONS
tCYCLE = 80 ns
SUBGROUPS
MIN
TYP
MAX
UNIT
1, 2, 3
--
15
30
mA
1, 2, 3
--
15
30
1, 2, 3
--
25
40
CEX = VIL
IOUT = 0 mA
Stand-by-current (TTL)
ISB1
CE 1-4 = VIH
WP = SE = 0V or VCC
1, 2, 3
--
--
4
mA
Stand-by current (CMOS)
ISB2
CE1-4 = VCC - 0.2
WP = SE = 0V or VCC
1, 2, 3
--
40
400
uA
Input leakage current2
ILI
VIN = 0 to 5.5 V
1, 2, 3
-40
--
40
uA
Output leakage current
ILO
VOUT = 0 to 5.5 V
1, 2, 3
-40
--
40
uA
Input high voltage, all inputs
VIH
1, 2, 3
2.0
--
--
V
Input low voltage, all inputs
VIL
1, 2, 3
--
--
0.8
V
Output high voltage level
VOH
IOH = -400 µ A
1, 2, 3
2.4
--
--
V
Output low voltage level
VOL
IOL = 2.1 mA
1, 2, 3
--
--
0.4
V
VOL = 0.4 V
1, 2, 3
8
10
--
mA
IOL (R/B)
Outuput low current (R/B)
1. Only one (1) CE 1-4 active at a time.
2. CE1-4 Leakage Current = +/- 10uA.
TABLE 7. 69F1608 CAPACITANCE 1
SYMBOL
SUBGROUPS
TEST
CONDITION
MIN
MAX
UNIT
Input/Output capacitance
CI/O
4, 5, 6
VIL = 0V
--
40
pF
Input capacitance (CE1-4 = 10pF)
CIN
4, 5, 6
VIN = 0V
--
40
pF
PARAMETER
1. Capacitance Guarenteed by design.
TABLE 8. 69F1608 MODE SELECTION
CLE
ALE
CE
H
L
L
H
WE
RE
SE
WP
L
H
X
X
L
H
X
X
03.07.08 REV 3
MODE
Read Mode
Command Input
Address Input (3
Clock)
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69F1608
128 Megabit (16M x 8-Bit) Flash Memory Module
TABLE 8. 69F1608 MODE SELECTION
CLE
ALE
CE
H
L
L
WE
RE
SE
WP
MODE
L
H
X
H
H
L
H
X
H
L
L
L
H
L/H 1
H
Data Input
L
L
L
H
L/H 1
X
Sequential Read & Data Output
L
L
L
H
H
L/H 1
X
During Read (Busy)
1
H
During Program (Busy)
Write Mode
Address Input (3
Clock)
X
X
X
X
X
L/H
X
X
X
X
X
X
H
During Erase (Busy)
X
X
X
X
L
Write Protect
X
0V/VCC3
0V/VCC3
X
X
X
2
X
H
X
Command Input
Stand-by
1. When SE is high, spare area is deselected.
2. X can be VIL or VIH.
3. WP should be biased to CMOS high or CMOS low for standby.
TABLE 9. 69F1608 PROGRAM/ERASE CHARACTERISTICS
(VCC = 5 V ± 10%, TA =-40 TO +125C, UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program time
tPROG
--
0.25
1.5
ms
Number of partial program cycles in the same page
NOP
--
--
10
cycles
Block erase time
tBERS
--
2
10
ms
03.07.08 REV 3
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69F1608
128 Megabit (16M x 8-Bit) Flash Memory Module
TABLE 10. 69F1608 AC TIMING CHARACTERISTICS FOR COMMAND/ADDRESS/DATA INPUT
(VCC = 5 V ± 10%, TA =-40 TO +125 C, UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
MAX
UNIT
CLE set-up time
tCLS
9, 10, 11
0
--
ns
CLE hold time
tCLH
9, 10, 11
10
--
ns
CE setup time
tCS
9, 10, 11
0
--
ns
CE hold time
tCH
9, 10, 11
10
--
ns
WE pulse width
tWB
9, 10, 11
25
--
ns
ALE setup time
tALS
9, 10, 11
0
--
ns
ALE hold time
tALH
9, 10, 11
10
--
ns
Data setup time
tDS
9, 10, 11
20
--
ns
Data hold time
tDH
9, 10, 11
10
--
ns
Write cycle time
tWC
9, 10, 11
50
--
ns
WE high hold time
tWH
9, 10, 11
15
--
ns
TABLE 11. 69F1608 AC CHARACTERISTICS FOR OPERATION
(VCC = 5 V ± 10%, TA = -40 TO +125° C, UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
MAX
UNIT
tR
9, 10, 11
--
10
µs
ALE to RE delay (read ID)
tAR1
9, 10, 11
150
--
ns
ALE to RE delay (read cycle)
tAR2
9, 10, 11
50
--
ns
CE to RE delay (ID read)
tCR
9, 10, 11
100
--
ns
Ready to RE low1
tRR
9, 10, 11
20
--
ns
RE pulse width
tRP
9, 10, 11
30
--
ns
WE high to busy
tWB
9, 10, 11
--
100
ns
Read cycle time
tRC
9, 10, 11
50
--
ns
RE access time
tREA
9, 10, 11
--
35
ns
RE high to output Hi-Z1
tRHZ
9, 10, 11
15
30
ns
Hi-Z1
tCHZ
9, 10, 11
--
20
ns
tREH
9, 10, 11
15
--
ns
Output Hi-Z to RE low1
tIR
9, 10, 11
0
--
ns
Last RE high to busy (at sequential read)
tRB
9, 10, 11
--
100
Data transfer from cell to register
CE high to output
RE high hold time
ns
3
CE high to ready (in case of interception by CE at
read) 2
tCRY
9, 10, 11
--
50 + tr (R/B)
CE high hold time (at the last serial read) 4
tCEH
9, 10, 11
100
--
ns
RE low to status output
tRSTO
9, 10, 11
--
35
ns
03.07.08 REV 3
ns
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69F1608
128 Megabit (16M x 8-Bit) Flash Memory Module
TABLE 11. 69F1608 AC CHARACTERISTICS FOR OPERATION
(VCC = 5 V ± 10%, TA = -40 TO +125° C, UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
MAX
UNIT
CE low to status output
tCSTO
9, 10, 11
--
45
ns
RE high to WE low
tRHW
9, 10, 11
0
--
ns
WE high to RE low
tWHR
9, 10, 11
60
--
ns
tREADID
9, 10, 11
--
35
ns
tRST
9, 10, 11
--
5/10/500
µs
RE access time (read ID)
Device resetting time (read/program/erase) after
erase suspend
1. Not Tested
2. If CE goes high within 30 ns after the rising edge of the last RE, R/B will not return to VOL.
3. The time to Ready depends on the value of the pull-up resistor tied to R/B pin.
4. To break the sequential read cycle, CE must be held high for longer than tCEH.
TABLE 12. 69F1608 VALID BLOCKS 1,2
PARAMETER
Valid Block Number
SYMBOL
MIN
TYP
MAX
UNIT
NVB
502
508
512
Blocks
1. The device may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to
access these invalid blocks for program and erase. During its life time of 10 years and/or 1 million program/erase cycles, the
minimum number of valid blocks are guaranteed though its initial number could be reduced.
2. The 1st block, which is placed on the 00h block address, is guaranteed to be a valid block.
NAND FLASH TECHNICAL NOTES
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by the
manufacturer. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block(s) is
called the invalid block information. The invalid block information is written to the 1st or the 2nd page of the invalid
block(s) with 00h data. Devices with invalid block(s) have the same quality level as devices with all valid blocks and
have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s)
because it is isolated from the bit line and the common source line by a select transistor. The system design must be
able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased (FFh) prior to shipping. Therefore, the system must be able to create the invalid block
table via the following suggested flow chart (Figure 1).
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 1. FLOW CHART TO CREATE INVALID BLOCK TABLE
Error in write or read operation
Over its lifetime, additional invalid blocks may occur. The following possible failure modes should be considered to
implement a highly reliable system. In the case of status read failure after erase or program, block replacement should
be done. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not
include those reclaimed blocks.
FAILURE MODE
Write
Read
DETECTION AND COUNTERMEASURE
Erase failure
Status read after erase / Block replacement
Program failure
Status read after program / Block replacement
Read back (verify after program) / Block replacement or
ECC correction
Single bit failure
Verify ECC correction
ECC: Error Correcting Code / Hamming Code, etc.
Example. 1-bit correction and 2-bit detection
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 2. PROGRAM FLOW CHART
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 3. ERASE FLOW CHART
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 4. READ FLOW CHART
FIGURE 5. BLOCK REPLACEMENT
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
Pointer Operation:
The 69F1608 has three modes to set the destination of the pointer. The pointer is set to “A” area by the “00h” command, to “B” area by the “01h” command, and to “C” area by the “50h” command. The Destination Pointer Table shows
the destination of the pointer, and the block diagram shows the diagram of its operation.
TABLE 12. DESTINATION OF POINTER TABLE
FIGURE 6. BLOCK DIAGRAM OF POINTER OPERATION
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 7. EXAMPLES OF PROGRAMMING WITH SUCCESSIVE POINTER OPERATION
TABLE 13. POINT STATUS AFTER EACH OPERATION
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown
below. The internal 528 byte page registers are utilized as seperate buffers for this operation and the system design
gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, deactivating CE during the data-loading and reading would provide significant savings in power consumption.
03.07.08 REV 3
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 8. PROGRAM OPERATION WITH CE DON’T CARE
FIGURE 9. READ OPERATION WITH CE DON’T CARE
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 10. COMMAND LATCH CYCLE
FIGURE 11. ADDRESS LATCH CYCLE
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 12. INPUT DATA LATCH CYCLE
FIGURE 13. SEQUENTIAL OUT CYCLE AFTER READ (CLE = L, WE = H, ALE = L)
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 14. STATUS READ CYCLE
FIGURE 15. READ1 OPERATION (READ ONE PAGE)
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 16. READ1 OPERATION (INTERCEPTED BY CE)
FIGURE 17. READ2 OPERATION (READ ONE PAGE)
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 18. SEQUENTIAL ROW READ OPERATION
FIGURE 19. PAGE PROGRAM OPERATION
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 20. BLOCK ERASE OPERATION (ERASE ONE BLOCK)
FIGURE 21. MANUFACTURE & DEVICE ID READ OPERATION
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing
00h to the command register along with three address cycles. Once the command is latched, it does not
need to be written for the following page read operation. Three types of operations are available : random
read, serial page read and sequential read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the
selected page are transferred to the data registers in less than 10 us(tR). The CPU can detect the completion
of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50 ns cycle time by sequentially pulsing RE with CE staying low. High to low
transitions of the RE clock output the data starting from the selected column address up to the last column
address(column 511 or 527 depending on state of SE pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential
read.
Waiting 10 µ s again allows for reading of the selected page. The sequential read operation is terminated by
bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main
area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the
Read2 command with SE pin low. Toggling SE during operation is prohibited. Addresses A0 to A3 set the
starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted,
the page address is automatically incremented for sequential read as in Read1 operation and spare sixteen
bytes of each page may be sequentially read. The Read1 command (00h/01h) is needed to move the
pointer back to the main area. Figures 22 thru 25 show typical sequence and timings for each read operation.
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 22. READ1 OPERATION
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 23. READ2 OPERATION
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 24. SEQUENTIAL ROW READ1 OPERATION
FIGURE 25. SEQUENTIAL READ2 OPERATION (SE = FIXED LOW)
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of
a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial
page programming operation within the same page without an intervening erase operation must not exceed
ten. The addressing may be done in any random order in a block. A page program cycle consists of a serial
data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. Serial data
loading can be started from 2nd half array. About the pointer operation, please refer to the attached technical
notes.The serial data loading period begins by inputting the Serial Data Input command (80H), followed by
the three cycle address input and then serial data loading. The bytes other than those to be programmed do
not need to be loaded.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without
perviously entering the serial data will not initiate the programming process. The internal write controller
automatically executes the algorithms and timings necessary for program and verify, thereby freeing the
CPU for other tasks. Once the program process starts, the Read Status Register command may be entered,
with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit (I/O6) of the Status Register. Only the Read Status command
and Reset command are valid while programming is in progress. When the Page Program is complete, the
Write Status Bit (I/O0) may be checked (Figure 26). The internal write verify detects only errors for "1"s that
are not successfully programmed to "0"s. The command register remains in Read Status command mode
until another valid command is written to the command register.
FIGURE 26. PROGRAM & READ STATUS OPERATION
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
BLOCK ERASE
The Erase operation can erase on a block (8K Byte) basis. Block address loading is accomplished in two
cycles initiated by an Erase Setup command (60h). Only address A13 to A21 is valid while A9 to A12 is
ignored. The addresses of the block to be erased to FFh. The Erase Confirm command (D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by
execution ensures that memory contents are not accidentally erased due to external noise conditions. At the
rising edge of WE after the erase confirm command input, the internal write controller handles erase and
erase-verify. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 27
details the sequence.
FIGURE 27. BLOCK ERASE OPERATION
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is
complete, and whether the program or erase operation completed successfully. After writing 70h command
to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of
each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not
need to be toggled for updated status. Refer to table 14 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status
register is read during a random read cycle, a read command (00h or 50h) should be given before sequential
page read cycle.
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
TABLE 14. READ STATUS REGISTER DEFINITION
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed
by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device
code (E3h) respectively. The command register remains in Read ID mode until further commands are issued
to it. Figure 28 shows the operation sequence.
FIGURE 28. READ ID OPERATION
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128 Megabit (16M x 8-Bit) Flash Memory Module
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RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in
Busy state during random read, program or erase modes, the reset operation will abort these operation. The
contents of memory cells being altered are no longer valid, as the data will be partially programmed or
erased. Internal address registers are cleared to "0"s and data registers to "1"s. The command register is
cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high.
Refer to table 15 for device status after reset operation. If the device is already in reset state a new reset
command will not be accepted to by the command register. The R/B pin transitions to low for tRST after the
Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 29 below.
FIGURE 29. RESET OPERATION
TABLE 15. DEVICE STATUS
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An
internal voltage detector disables all functions whenever VCC is below about 2V. WP pin provides hardware
protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 30.
The two step command sequence for program/erase provides additional software protection.
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 30. AC WAVEFORMS FOR POWER TRANSITION
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program
or erase command is written to the command register or random read is begin after address loading. It
returns to high when the internal controller has finished the operation. The pin is an open-drain driver
thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by following equation.
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
FIGURE 31. READY/BUSY
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
24 PIN RAD-PAK® FLAT PACKAGE
DIMENSION
SYMBOL
MIN
NOM
MAX
A
0.284
0.310
0.336
A2
0.030
0.035
0.040
b
0.013
0.016
0.018
c
0.006
0.008
0.010
D
0.810
0.820
0.830
D2
0.780
0.800
0.820
E
1.132
1.140
1.148
E1
--
--
1.170
E2
2.020
2.240
2.464
E3
0.960
0.980
1.000
e
0.050 BSC
L
0.410
0.420
0.430
Q
0.212
0.230
0.248
S1
0.000
0.038
--
N
24
Note: All dimensions in inches
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128 Megabit (16M x 8-Bit) Flash Memory Module
69F1608
Important Notice:
These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
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69F1608
128 Megabit (16M x 8-Bit) Flash Memory Module
Product Ordering Options
Model Number
69F1608
RP
F
X
Option Details
Feature
Screening Flow
MCM1
K= Maxwell Self-Defined Class K
H= Maxwell Self-Defined Class H
I = Industrial (testing @ -40°C,
+25°C, +125°C)
E = Engineering (testing @ +25°C)
Package
F = Flat Pack
Radiation Feature
RP = RAD-PAK® package
Base Product
Nomenclature
128 Megabit (16M x 8-Bit) Flash
Memory
1) Products are manufactured to Maxwell Technologies self-defined Class H and Class K flows.
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