69FxxxG24 – Flash, NAND; 12, 24, 96 or 192 Gb x24

NAND Flash Module
Preliminary
69F12G24, 69F24G24,
69F96G24, 69F192G24
FEATURES:
69F12Gb, 69F24Gb (4Gb die)
High density
4Gbit per FLASH NAND die
Supports higher speed designs with less
capacitance/fewer I/O's to drive
NAND Flash Interface
Single Level Cell (SLC) Technology
ONFI 1.0 Compliant
Operating Voltage
VCC 3.0 - 3.6V
Page Size
2112 bytes (2048 + 64 spare bytes)
Includes internal BCH correction algorithms (4 bit
correction per 528 bytes)
Features
High reliability data storage for demanding space
applications
Ceramic hermetic package with built-in TID
shielding
Three separate FLASH memory banks, supports
TMR error correction
FEATURES: 69F 96Gb, 69F192Gb (32Gb die)
High density
32Gbit per FLASH NAND die
Supports higher speed designs
with less capacitance/fewer I/O's
NAND Flash Interface
Single Level Cell (SLC) Technology
ONFI 2.2 Compliant
Operating Voltage
VCC 3.0 - 3.6V
VCCQ 1.7 - 1.95V or 3.0-3.6V
Page Size
8640 bytes (8192 + 448 spare
Supports external BCH correction
algorithms (up to 16 bit
correction per 540 bytes)
Features
High reliability data storage for
demanding space applications
Ceramic hermetic package with
built-in TID shielding
Three separate FLASH memory
banks, supports TMR error
Class E, I, H or K
Class E, I, H or K
Speed
Speed
Asynch: Up to asynch timing mode 5 (50MT/sec)
Temperature Range
-55⁰C to 125⁰C
Endurance
100,000 cycles
10.07.15 Rev 1
Asynch: Up to asynch timing
mode 5 (50MT/sec)
Synch: Up to synchronous timing
mode 5 (200MT/sec)
Temperature Range
-55⁰C to 125⁰C
Endurance
60,000 cycles
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
1
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Supported Commands:
Reset
Synchronous Reset
Reset LUN
Get Features
Set Features
Read Status
Read Status Enchanced (Multi-LUN)
Change Read Column (Random data output)
Change Read Column Enhanced
Change Write Column (Random data input)
Change Row Address
Read Mode
Read Page
Read Page Interleaved
Read Page Cache Sequential *
Read Page Cache Random *
Read Page Cache Last *
Program Page
Program Page Interleaved
Program Page Cache *
Erase Block
Erase Block Interleaved
Copyback Read
Copyback Program
Copyback Program Interleaved
Read Unique ID
Read Parameter Page
Read ID
* These commands supported with internal ECC disabled
4Gb die
FFh
-
EEh
EFh
70h
78h
05h
06h
85h
E0h
E0h
-
00h
00h
00h
31h
00h
3Fh
80h
80h
80h
60h
60h
00h
85h
85h
EDh
ECh
90h
30h
00h, 30h
31h
10h
11h-85h,10h
15h
D0h
D1h
35h
10h
11h
-
32Gb die
FFh
FCh
FAh
EEh
EFh
70h
78h
05h
E0h
06h
E0h
85h
85h
00h
00h
30h
00h
32h
31h
00h
31h
3Fh
80h
10h
80h
11h
80h
15h
60h
D0h
60h
D1h
00h
35h
85h
10h
85h
11h
EDh
ECh
90h
-
Not Supported
Non-sequential page programming
16 bit data bus width per Target/LUN
Extended ECC
Synchronous Mode: clock stopped for data input
10.07.15 Rev 1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
2
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Array Organization: 4Gb Die
Cycle
First
Second
Third
Fourth
Fifth
DQ7
CA7
L
BA7
BA15
L
DQ6
CA6
L
BA6
BA14
L
DQ5
CA5
L
PA5
BA13
L
DQ4
CA4
L
PA4
BA12
L
DQ3
CA3
CA11
PA3
BA11
L
DQ2
CA2
CA10
PA2
BA10
LUN/BA18
DQ1
CA1
CA9
PA1
BA9
BA17
DQ0
CA0
CA8
PA0
BA8
BA16
CA[n] = Column Address
PA[n] = Page Address
BA[n] = Bank Address
LUN = Logical Unit Address
Row Address = LUN, Bank, Page Address
BA[6] = Plane Select
Column Addresses above 2111 are invalid (page size =2048 + 64)
Memory Organization
Bytes per page: 2048
Spare ECC bytes per page: 64
Pages per block: 64
Blocks per LUN: 4096
LUNs per chip enable: 2
Column address cycles: 2
Row address cycles: 3
Bits per cell: 1
Bad blocks maximum per LUN: 80
Block endurance: 100,000
Programs per page: 4
Number of bits ECC required: 1 (for 512 Bytes)
Number of interleave address bits: ?
10.07.15 Rev 1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
3
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Array Organization: 32Gb Die
Cycle
First
Second
Third
Fourth
Fifth
DQ7
CA7
L
BA7
BA15
L
DQ6
CA6
L
PA6
BA14
L
DQ5
CA5
CA13
PA5
BA13
L
DQ4
CA4
CA12
PA4
BA12
L
DQ3
CA3
CA11
PA3
BA11
LUN
DQ2
CA2
CA10
PA2
BA10
BA18
DQ1
CA1
CA9
PA1
BA9
BA17
DQ0
CA0
CA8
PA0
BA8
BA16
CA[n] = Column Address
PA[n] = Page Address
BA[n] = Bank Address
LUN = Logical Unit Address
Row Address = LUN, Bank, Page Address
BA[7] = Plane select
Column Addresses above 8639 are invalid (page size = 8192 + 448)
Memory Organization
Bytes per page: 8192
Spare ECC bytes per page: 448
Pages per block: 128
Blocks per LUN: 4096
LUNs per chip enable: 2
Column address cycles: 2
Row address cycles: 3
Bits per cell: 1
Bad blocks maximum per LUN: 80
Block endurance: 60,000
Programs per page: 4
Number of bits ECC required: 8 (for 512 Bytes)
Number of interleave address bits: 1
10.07.15 Rev 1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
4
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Package Organization
12Gb X 24
96Gb X 24
Package
Sync
Async
CE#-1
DQS-1
CLK-1
DQ[7-0]-1
CE#-1
N/A-1
WE#-1
DQ[7-0]-1
Target-1
LUN 1
Target-2
CE#-2
DQS-2
CLK-2
DQ[7-0]-2
LUN 1
CE#-2
N/A-2
WE#-2
DQ[7-0]-2
R/B#
Target-3
CE#-3
DQS-3
CLK-3
DQ[7-0]-3
ALE
W/R#
CLE
WP#
LUN 1
CE#-3
N/A-3
WE#-3
DQ[7-0]-3
ALE
RE#
CLE
WP#
Architecture
Independent 8 bit buses per package: 3
Targets per 8 bit bus: 1
LUNS per Target:
(1 die per 8 bit bus)
(3 die per package)
DQ[7-0]-1 CE#-1
WE-1#/CLK-1
DQS-1
DQ[7-0]-2 CE#-2
WE#-2/CLK-2
DQS-2
DQ[7-0]-3 CE#-3
WE#-3/CLK-3
DQS-3
Shared
10.07.15 Rev 1
ALE
RE#, W/R#
CLE
WP#
RB#
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
5
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Package Organization
24Gb X 24
192Gb X 24
Package
Sync
Async
CE#-1
DQS-1
CLK-1
DQ[7-0]-1
CE#-1
N/A-1
WE#-1
DQ[7-0]-1
Target-1
LUN 1
LUN 2
Target-2
CE#-2
DQS-2
CLK-2
DQ[7-0]-2
LUN 1
CE#-2
N/A-2
WE#-2
DQ[7-0]-2
LUN 2
R/B#
Target-3
CE#-3
DQS-3
CLK-3
DQ[7-0]-3
ALE
W/R#
CLE
WP#
LUN 1
CE#-3
N/A-3
WE#-3
DQ[7-0]-3
LUN 2
ALE
RE#
CLE
WP#
Architecture
Independent 8 bit buses per package: 3
Targets per 8 bit bus: 1
LUNS per Target: 2
(2 die per 8 bit bus)
(6 die per package)
DQ[7-0]-1 CE#-1
WE-1#/CLK-1
DQS-1
DQ[7-0]-2 CE#-2
WE#-2/CLK-2
DQS-2
DQ[7-0]-3 CE#-3
WE#-3/CLK-3
DQS-3
Shared
10.07.15 Rev 1
ALE
RE#, W/R#
CLE
WP#
RB#
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
6
©2015 Maxwell Technologies
All rights reserved
NAND Flash
10.07.15 Rev 1
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
7
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Pinout
Description
4Gb die
Differences
→
→
→
→
→
→
→
→
WE#-1
→
WE#-2
VCC
VSS
WE#-3
RE#
→
→
→
DNC
VCC
VSS
→
→
→
→
VCC
VSS
→
→
→
→
VCC
VSS
→
→
Description
32Gb die
Aysnc/Sync
VCC
VSS
CLE
CE#-1
CE#-2
CE#-3
VCC
VSS
WE# / CLK-1
RB#
WE# / CLK-2
VCCQ
VSSQ
WE# / CLK-3
RE#/W/R#
ALE
VCC
VSS
DNU / DQS-1
VCCQ
VSSQ
DQ7
DQ6
DQ5
DQ4
VCCQ
VSSQ
DQ3
DQ2
DQ1
DQ0
VCCQ
VSSQ
VCC
VSS
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pin # Description
32Gb die
Aysnc/Sync
70
VCCQ
69
VSSQ
68
DQ16
67
DQ17
66
DQ18
65
DQ19
64
VCCQ
63
VSSQ
62
DQ20
61
DQ21
60
DQ22
59
DQ23
58
VCCQ
57
VSSQ
56
DNU / DQS-3
55
VCC
54
VSS
53
WP#
52
DNU / DQS-2
51
VCCQ
50
VSSQ
49
DQ15
48
DQ14
47
DQ13
46
DQ12
45
VCCQ
44
VSSQ
43
DQ11
42
DQ10
41
DQ9
40
DQ8
39
VCCQ
38
VSSQ
37
VCC
36
VSS
Description
4Gb die
Differences
VCC
VSS
←
←
←
←
VCC
VSS
←
←
←
←
VCC
VSS
NC
←
←
←
NC
VCC
VSS
←
←
←
←
VCC
VSS
←
←
←
←
VCC
VSS
←
←
Three 8 bit buses; Each with its own CS[0-2], DQS[0-2] & WE#CLK[0-2]
Three chip selects for 6 die using Multi-LUN operation.
All other control signals are shared; CLE, RB#, RE#-W/R#,ALE & WP#
Arrow indicates the same signal between die types
VCCQ and VSSQ are not separated from VCC and VSS for 4Gb die
10.07.15 Rev 1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
8
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Feature Summary
Description
ONFI 1.0, 2.0, 2.1, 2.2
Program page register clear enhancement
Extended parameter page
Interleaved read operations
Synchronous interface
Odd to even page copyback
Interleaved Porgram and erase operations
Non-sequential page programming
Multiple LUN operations
16 bit data bus width per LUN
RESET LUN command
Small data move
CHANGE ROW ADDRESS
CHANGE READ COLUMN ENHANCED
READ UNIQE ID
COPYBACK
READ STATUS ENHANCED
GET FEATURES & SET FEATURES
Read cache commands
PROGRAM PAGE CACHE
Number of data bytes per page
Number of spare bytes per page
Number of bytes per partial page
Numpber of spare bytes per partial page
Number of pages per block
Number of blocks per LUN
Number of LUNs per chip enable
Number of address cycles
Column address cycles
Row address cycles
Number of bits per cell
Bad blocks maximum per LUN
Block endurance
Guaranteed valid blocks at beginning
Block endurance for guranteed valid blocks
Number of programs per page
Number of bits ECC correctability
Number of interleaved address bits
Interleaved read cache
Interleaved address restrictions for cache operations
Interleaved program cache support
Interleaved block address restrictions
Overlapped/concurrent interleaving
I/O pin maximum capacitance per target
Driver Strength; Overdrive 1 & 2
tPROG Typical (Page Program)
tBERS Typical (Block Erase)
tR max (Page Read)
tCCS Typical (change column setup)
Input pin capacitance, typical
10.07.15 Rev 1
4Gb die
1.0
Yes
Yes
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
2048
64
512
16
64
4096
2
2
3
1
80
100000
1
0
4
4
1
Yes
Yes
No
No
20 pf/ 10pf
600 us
3 ms
25 us
100 ns
10 pf
32Gb die
1.0 to 2.2
Yes
No
Yes
Yes
Yes
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8192
448
128
4096
2
2
3
1
80
60,000
1
0
4
8
1
Yes
Yes
Yes
No
No
Yes
515 us
7 ms
35 us
200 ns
6 pF
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
9
©2015 Maxwell Technologies
All rights reserved
69F12Gb24, 69F24Gb24, 69F96Gb24, 69F192Gb24
NAND Flash
Product Ordering Options
69F
XXX G
24
XX
F
X
Screening Flow
K = Maxwell Class K
H = Maxwell Class H
I = Industrial (testing @ -55⁰C, +25⁰C +125⁰C )
E = Engineering (testing at +25⁰C )
Package
F = Flat Pack
Radiation Feature
RP = RAD -PAK® Package Shielding
RT = Kovar Lid
Data Width
24 = 24 bits wide
Total Gbits
12 = 12Gb
24 = 24Gb
96 = 96Gb
192 = 192Gb
Base Product 3.3V by 24 NAND FLASH SLC
Nomenclature
10.07.15 Rev 1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
10
©2015 Maxwell Technologies
All rights reserved
Similar pages