IGLOO2 FPGA Fabric DDR Controller Configuration

IGLOO2 FPGA
Fabric DDR Controller Configuration
IGLOO2 FPGA Fabric DDR Controller Configuration
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
A Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction
The IGLOO2 FPGA has an embedded Fabric DDR (FDDR) controller for access to an external DDR
memory from the FPGA Fabric. The FDDR controls off-chip DDR memories.
When you use System Builder to build a system block, System Builder configures the FDDR controller
for you based on your entries and selections; no separate FDDR configuration is required. For details,
please refer to the IGLOO2 System Builder User Guide.
System Builder
Invoke System Builder to configure the FDDR automatically.
1. In the Device Features tab of System Builder, check Fabric External DDR Memory (FDDR).
2. In the Memories tab of System Builder, select the DDR Memory Type:
–
DDR2
–
DDR3
–
LPDDR
3. Select the Width of the DDR Memory: 8, 16 or 32
4. Check ECC if you want to have ECC for the DDR.
5. Enter the DDR memory setting time. This is the time the DDR memory requires to initialize.
6. Click Import Register Configuration to import the Register values for the FDDR from an existing
text file containing the register values. See Table 1 for the register configuration file syntax.
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Libero automatically stores this configuration data in the eNVM. Upon FPGA reset, this configuration
data will automatically be copied into the FDDR.
Figure 1 • System Builder and FDDR
Table 1 • Register Configuration File Syntax
ddrc_dyn_soft_reset_CR 0x00 ;
ddrc_dyn_refresh_1_CR 0x27DE ;
ddrc_dyn_refresh_2_CR 0x30F ;
ddrc_dyn_powerdown_CR 0x02 ;
ddrc_dyn_debug_CR 0x00 ;
ddrc_ecc_data_mask_CR 0x0000 ;
ddrc_addr_map_col_1_CR 0x3333 ;
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1 – Port Description
DDR PHY Interface
These ports are exposed at the top level of the System Builder generated block. For details, consult the
IGLOO2 System Builder User Guide. Connect these ports to your DDR memory.
Table 1-1 • DDR PHY Interface
Port Name
Direction
Description
FDDR_CAS_N
OUT
DRAM CASN
FDDR_CKE
OUT
DRAM CKE
FDDR_CLK
OUT
Clock, P side
FDDR_CLK_N
OUT
Clock, N side
FDDR_CS_N
OUT
DRAM CSN
FDDR_ODT
OUT
DRAM ODT
FDDR_RAS_N
OUT
DRAM RASN
FDDR_RESET_N
OUT
DRAM Reset for DDR3
FDDR_WE_N
OUT
DRAM WEN
FDDR_ADDR[15:0]
OUT
Dram Address bits
FDDR_BA[2:0]
OUT
Dram Bank Address
FDDR_DM_RDQS[4:0]
INOUT
Dram Data Mask
FDDR_DQS[4:0]
INOUT
Dram Data Strobe Input/Output - P Side
FDDR_DQS_N[4:0]
INOUT
Dram Data Strobe Input/Output - N Side
FDDR_DQ[35:0]
INOUT
DRAM Data Input/Output
FDDR_FIFO_WE_IN[2:0]
FDDR_FIFO_WE_OUT[2:0]
IN
OUT
FIFO in signal
FIFO out signal
FDDR_DM_RDQS ([3:0]/[1:0]/[0])
INOUT
Dram Data Mask
FDDR_DQS ([3:0]/[1:0]/[0])
INOUT
Dram Data Strobe Input/Output - P Side
FDDR_DQS_N ([3:0]/[1:0]/[0])
INOUT
Dram Data Strobe Input/Output - N Side
FDDR_DQ ([31:0]/[15:0]/[7:0])
INOUT
DRAM Data Input/Output
FDDR_DQS_TMATCH_0_IN
IN
FDDR_DQS_TMATCH_0_OUT
FDDR_DQS_TMATCH_1_IN
FDDR_DQS_TMATCH_1_OUT
OUT
IN
OUT
FIFO in signal
FIFO out signal
FIFO in signal (32-bit only)
FIFO out signal (32-bit only)
FDDR_DM_RDQS_ECC
INOUT
Dram ECC Data Mask
FDDR_DQS_ECC
INOUT
Dram ECC Data Strobe Input/Output - P Side
FDDR_DQS_ECC_N
INOUT
Dram ECC Data Strobe Input/Output - N Side
FDDR_DQ_ECC ([3:0]/[1:0]/[0])
INOUT
DRAM ECC Data Input/Output
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Table 1-1 • DDR PHY Interface
Port Name
Direction
FDDR_DQS_TMATCH_ECC_IN
FDDR_DQS_TMATCH_ECC_OUT
IN
OUT
Description
ECC FIFO in signal
ECC FIFO out signal (32-bit only)
Note: Port widths for some ports change depending on the selection of the PHY width. The notation "[a:0]/
[b:0]/[c:0]" is used to denote such ports, where "[a:0]" refers to the port width when a 32-bit PHY
width is selected, "[b:0]" corresponds to a 16-bit PHY width, and "[c:0]" corresponds to an 8-bit PHY
width.
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A – Product Support
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Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
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So, before you contact us, please visit our online resources. It is very likely we have already answered
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Technical Support
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information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the website.
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
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We constantly monitor the email account throughout the day. When sending your request to us, please
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The technical support email address is [email protected].
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My Cases
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Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
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ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations
(ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR
drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.
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