5 4 3 2 1 DIR TP8 TP1 JP5 EXT_VDD J2 MISO SDI STCK 1 SPI_IN VS VREG JP2 J3 2 4 6 8 10 FLAG CK nCS STBY_RESET MISO SDO 1 1 3 5 7 9 DIR D DIR VDD JP1 1 3 5 7 9 2 4 6 8 10 MORSV-508-2P VS 1 1 EXT_VDD EXT_VDD 1 2 FLAG VS GND CK nCS STBY_RESET J1 JP3 MISO D SDO SPI_OUT CON-FLAT-5X2-180M JP4 STCK STCK TP2 STBY/RES TP3 Application reference VDD TP4 VDD VREG TP5 VREG 1 1 R2 50k 2 C3 C4 + 100nF/6.3V 10uF/4V VS D1 C5 100nF/4V C6 2 1 C7 C8 C10 + 100nF/50V 100nF/50V 100nF/50V C9 100uF/63V 3 C2 + 47uF/6.3V C1 220nF/16V 1 VREG C C VDD VREG 3 BAV99 C11 100nF/50V OPTION 10nF/50V VS 7 ADCIN R6 39k C14 1nF/4V C15 1nF/4V C16 1nF/4V 10 11 2 26 12 16 1 2 1A 2A 28 J5 MORSV-508-2P 2 1 1B 2B 15 J6 MORSV-508-2P AGND PGND PGND OUT2B 14 9 13 27 VDD 1 B OUT1B STCK DIR CS CK SDI SDO C9A 100uF/63V L6474 STBY_RES FLAG SYNC EPAD 25 4 23 19 20 18 STCK DIR nCS CK SDI SDO DL1 3.3nF/4V 3 24 22 29 C13 ADCIN DGND 1 OSCOUT 21 1 2 STBY_RESET FLAG OUT1A OUT2A 5 RED OSCIN + VSA VSA VSB VSB N.M. R4 39k 8 FLAG TP7 R5 470 B R3 39k 2 1 R1 39k CP J4 VDD VBOOT VDD VREG U1 17 6 VDD J7 N.M. 1 SYNC A A TP6 GND Title 1 L6474H easySPIN Demonstration board. Size A4 Date: 5 4 3 2 Document Number EVAL6474H Monday, December 19, 2011 Rev 1.0 Sheet 1 1 of 1