TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 D D D D D D D D D D D Single-Chip With Eight Physical-Layer (PHY) Interfaces for Internetworking Applications Each PHY Is Full-Duplex Capable for Simultaneous Transmit and Receive Compliant With IEEE Std 802.3 10BASE-T Specification Integrated Filters on Both Receive and Transmit Circuits – No External Filters Are Required – Meets IEEE Std 802.3 (Section 14.3) Electrical Requirements Implements IEEE Std 802.3 Autonegotiation to Establish the Highest Common Protocol Electrostatic Discharge (ESD) Human Body Model (HBM) Protection 1.5 kV Per JEDEC JESD22-A114A Digital Signal Processor (DSP)-Based Digital Phase-Locked Loop (PLL) Loopback Mode for Test Operations Integrated Manchester Encoding/Decoding Receive-Clock Regeneration for All Input Channels Using Digital PLL FIFOs Accommodate 8x IEEE Limit on Per-Channel-Pair Frequency Mismatch Across All Eight Channels (IEEE Std 802.3, Sec 7.3.2) D D D D D D D D D D D D D D Intelligent Squelch With Selectable Threshold Link-Pulse Detection and Autonegotiation Intelligent Rejection of MLT-3 Encoded Data Transmit Pulse Shaping Reduces Electromagnetic Interference (EMI) Clock Synchronization Between Channels Collision Detection Built-In Jabber Detection Automatic Reversed-Polarity Detection and Correction Sufficient Current Drive to Directly Connect LED Status Indicators CMOS Technology Enables Low Power Consumption 3.3-V Operation IEEE Std 1149.1 (JTAG)† Test-Access Port (TAP) Direct Drive to Network Coupling Magnetics Packaged in 120-Pin Plastic Quad Flatpack (PQFP) description The TNETE2008 OctalPHY is a physical-layer (PHY) interface device for up to eight 10BASE-T networks using a multiplexed medium access controller (MAC) interface compatible with TNETX3110, TNETX3151, TNETX3190, or TNETX3270 switch devices, or equivalent. A digital-signal-processor (DSP)-based phase-locked loop (PLL) is used on each channel to recover data. Integrated wave shaping of the output eliminates the need for filters to meet electromagnetic interference (EMI) testing. DSP-based wave-shaping techniques used internally reduce the required number of external components to a coupling transformer, four resistors, and a capacitor per channel. The multiplexed host interface reduces the number of terminals required to connect eight networks to eight MAC engines, allowing the use of a single package. The TNETE2008 operation is fully automatic. It can be taken from reset to full operation without parameter downloads or interaction with a host central processing unit (CPU). Some mode terminals affect all of the ports, such as looping back transmit data to the receive path, powering down the PHY, and setting the receiver threshold. There are no management interfaces or internal registers on this device. A directly driven LED matrix provides Ethernet status indicators, i.e., link, activity, collision, and duplex. The TNETE2008 produces and receives IEEE Std 802.3-compliant waveforms when coupled to the network with a suitable transformer. The TNETE2008 also incorporates a JTAG-compliant test port. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † IEEE Std 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture Ethernet is a trademark of Xerox Corporation. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 description (continued) The TNETE2008 provides PHY interface functions for up to eight 10BASE-T network ports as shown in Figure 1. A typical application with external components is shown in Figure 2. To LED Status Indicators PHY Data I/O MAC TNETE2008 Control Signals Interface PHY 0 IEEE Std 1149.1 Test-Access Port PHY 1 LED Drivers Autonegotiation PHY 2 TNETE2008 Control Logic PHY 7 PHY Status and Control Signals Figure 1. OctalPHY Architecture 1. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 To/From 10BASE-T Network TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 RCVN0 RCVP0 XMTN0 XMTP0 IFRXDV IFRXD0 IFRXD1 IFRXD2 IFRXD3 IFSYNC IFCLK TNETX3110, TNETX3151, TNETX3190, TNETX3270 or Compatible Ethernet Controller RCVN1 RCVP1 XMTN1 IFTXD0 IFTXD1 IFTXD2 IFTXD3 XMTP1 RCVN2 IFTXEN IFCRS IFCOL RCVP2 XMTN2 XMTP2 IFLINK IFFORCEHD IFDUPLEX 50 Ω 50 Ω 50 Ω 50 Ω 50 Ω 50 Ω 50 Ω 50 Ω 50 Ω RCVP3 XMTN3 XMTP3 50 Ω 50 Ω 10 µF 0.1 µF RCVP4 XMTN4 XMTP4 50 Ω 50 Ω GND (X4) 10 µF 10 KΩ 0.1 µF 10 KΩ RCVVDD, AVDD, XMTVDD RCVP5 XMTN5 PWRDOWN XMTP5 MLT3BLOCK LOOPBACK RCVN6 RCVTHRESH XMTGND (X16) RCVGND, AGND GND 7.5 KΩ 1% 50 Ω 20-MHz Oscillator Module RJ45C AVDD RJ45C AVDD RJ45C AVDD RJ45C 0.1 µF RCVGND 50 Ω 0.1 µF RCVGND 50 Ω 0.1 µF RCVGND 50 Ω 0.1 µF Bel S553–5999–XX Quad or Equivalent RCVGND 50 Ω RCVP6 XMTN6 XMTP6 50 Ω AVDD RJ45C 50 Ω AVDD RJ45C 50 Ω 50 Ω 50 Ω AVDD RJ45C AVDD RJ45C 0.1 µF RCVGND 50 Ω 0.1 µF RCVGND 50 Ω ARBIAS 2.5 KΩ 1% AVDD RCVN5 50 Ω 10 KΩ RCVGND RCVN4 50 Ω 3.3 V Bel S553–5999–XX Quad or Equivalent RCVN3 50 Ω VDD (X4) 0.1 µF AIREF RCVN7 CLK RCVP7 XMTP7 XMTN7 50 Ω 50 Ω 50 Ω 0.1 µF RCVGND 50 Ω Figure 2. External Components POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 terminal assignments TNETE2008 signal terminals are identified according to the section of the device. All 3.3-V power is labeled VDD and GND for ground. VCC power on terminal 48, JTAG power, is subject to JTAG system requirements. Each terminal has prefix letters indicating the circuit of the device it supplies. RCV is receiver circuits, XMT is transmitter circuits, A is analog circuits, J is JTAG circuits, and IF is interface circuits; NC terminals are not connected to anything inside the device. 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 NC NC NC NC NC XMTGND RCVP0 RCVN0 RCVVDD RCVP1 RCVN1 RCVGND RCVP2 RCVN2 RCVP3 RCVN3 RCVP4 RCVN4 RCVP5 RCVN5 RCVP6 RCVN6 RCVP7 RCVN7 GND GND NC NC NC NC PBE PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NC NC NC NC NC XMTGND ARBIAS XMTVDD ATEST AVDD AIREF AGND CLK RCVTHRESH PWRDOWN RESET LOOPBACK VCC JTDI VDD JTDO JTMS JTCK JTRST GND NC NC NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 XMTP0 XMTN0 XMTGND XMTGND XMTP1 XMTN1 XMTGND XMTGND XMTP2 XMTN2 XMTGND XMTGND XMTP3 XMTN3 XMTGND XMTGND XMTP4 XMTN4 XMTGND XMTGND XMTP5 XMTN5 XMTGND XMTGND XMTP6 XMTN6 XMTGND XMTGND XMTP7 XMTN7 NC – No internal connection 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IFFORCEHD IFTXD0 IFTXD1 IFTXD2 VDD IFTXD3 IFTXEN IFDUPLEX IFSYNC GND IFCLK IFCOL IFCRS IFRXDV VDD IFRXD0 IFRXD1 IFRXD2 IFRXD3 GND IFLINK MTL3BLOCK LLINK LACTIVE LDUPCOL VDD LSEL0,1 LSEL2,3 LSEL4,5 LSEL6,7 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 Terminal Functions controller interface – this block of signals is defined for each channel during its time slot (see Figure 6) TERMINAL NAME NO. I/O DESCRIPTION IFCLK 80 O Interface clock. All ports handled by the interface use the same clock. The clock frequency is 20 MHz. IFCOL 79 O Collision. When asserted, IFCOL indicates a network collision on the current port. IFCRS 78 O Carrier sense. IFCRS indicates a frame carrier signal is being received on the current port. It asserts for transmissions in half-duplex mode. IFDUPLEX 83 O Duplex mode. If IFDUPLEX is low, then the current port is in half duplex, otherwise it is full duplex. If the IFFORCEHD signal is low, then IFDUPLEX also is low. Force half duplex. This terminal has two functions: IFFORCEHD 90 I The first function concerns the values advertised during autonegotiation of link. If IFFORCEHD is low when a channel latches in the control information about which modes it can advertise during autonegotiation (see Figure 9), this channel is forced to half duplex. Values delivered on IFTXD0–IFTXD3 are overridden. If this terminal is high at latch time, the modes are set by the values passed on IFTXD0–IFTXD3 during the period before commencement of fast link pulse (FLP) exchange for this channel. The second function is the ability of the terminal to drive link invalid for this channel during its time slot and restart link validation. Link is driven invalid and reestablishing link starts when IFFORCEHD transitions from one to zero or from zero to one; that is, any edge on IFFORCEHD drives link invalid and starts the process of reestablishing link. Multiple edges in this signal before link is established force multiple restarts of the linking process shown in Figure 9. IFLINK 70 O Interface link. IFLINK indicates the presence of port connection on the current port. Low is no link and high is link made. IFRXD3† IFRXD2 IFRXD1 IFRXD0 72 73 74 75 O Receive data. Receive data bits 3–0 from current port when IFRXDV is asserted. Receive data is clocked out on falling edge of IFCLK. IFSYNC 82 O Interface sync. When IFSYNC is 1, the current port for MAC to TNETE2008 transfers is port 0. This signal has a period of 400 ns and a duty cycle of 1:8. The port number for TNETE2008 → MAC data is always two slots ahead and is port 2 when IFSYNC is high. IFSYNC is sampled by the MAC on the falling edge of IFCLK. IFTXD3† IFTXD2 IFTXD1 IFTXD0 85 87 88 89 I Transmit data bit. Transmit data bits 3–0 for the current port when IFTXEN is asserted. Data should change on the rising edge of IFCLK to be clocked into the TNETE2008 on the following rising edge of IFCLK. IFTXEN 84 I Transmit enable. IFTXEN indicates that valid transmit data is on IFTXD0–IFTXD3. IFRXDV 77 O Receive data valid. This signal indicates the IFXRD0–IFXRD3 contain valid data. † Most significant bit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 Terminal Functions (Continued) JTAG interface TERMINAL NAME NO. I/O DESCRIPTION JTCK 53 I Test clock. JTCK is used to clock state information and test data into and out of the device during operation of the TAP. This terminal should be pulled up to terminal 48 if the JTAG interface is not used. JTDI 49 I Test data input. JTDI is used to serially shift test data and test instructions into the device during operation of the TAP. This terminal should be pulled up to terminal 48 if the JTAG interface is not used. JTDO 51 O Test data output. JTDO is used to serially shift test data and test instructions out of the device during operation of the TAP. JTMS 52 I Test mode select. JTMS controls the operating state of JTAG. This terminal should be pulled up to terminal 48 if the JTAG interface is not used. JTRST 54 I Test reset. JTRST is used for asynchronous reset of the JTAG controller. This terminal should be tied to GND if not used. LED interface TERMINAL NAME 6 NO. I/O DESCRIPTION LACTIVE 67 O LED activity indicator. LACTIVE indicates that the selected PHY is transmitting or receiving data. This signal is low for even-numbered (0, 2, 4, 6) ports and high for odd-numbered (1, 3, 5, 7) ports. LDUPCOL 66 O LED duplex/collision indicator. This LED status terminal has different meaning when in full- or half-duplex mode. In full-duplex mode, LDUPCOL is continuously driven active. In half-duplex mode, it is driven active for 20 ms after a collision. LDUPCOL indicates full-duplex mode and collisions for the currently selected PHY. This signal is active low for even (0, 2, 4, 6) ports and active high for odd (1, 3, 5, 7) ports. LLINK 68 O LED link indicator. LLINK indicates that the selected PHY has established a network link. This signal is low for even (0, 2, 4, 6) ports and high for odd (1, 3, 5, 7) ports. LSEL0, 1 64 O LED select PHY 0, 1. LED select indicator for PHY0 or PHY1, depends on polarity. This signal is high for PHY0 and low for PHY1. LSEL2, 3 63 O LED select PHY 2,3. LED select indicator for PHY2 or PHY3, depends on polarity. This signal is high for PHY2 and low for PHY3. LSEL4, 5 62 O LED select PHY 4,5. LED select indicator for PHY4 or PHY5, depends on polarity. This signal is high for PHY4 and low for PHY5. LSEL6, 7 61 O LED select PHY 6,7. LED select indicator for PHY6 or PHY7, depends on polarity. This signal is high for PHY6 and low for PHY7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 Terminal Functions (Continued) miscellaneous interface TERMINAL NAME NO. TYPE† DESCRIPTION AIREF 41 A Current reference. Used to set a current reference for the analog circuitry. AIREF must be connected to GND by a 2.5-kΩ 1% resistor. ARBIAS 37 A Bias resistor for the analog circuitry. Connect 7.5-kΩ 1% resistor between this pin and GND. ATEST 39 A Manufacturing test terminal. Leave unconnected. CLK 43 I Clock input. CLK connects a 20-MHz clock source to this terminal. The device enters a reset state on loss of CLK. 47 I Loopback. When low, LOOPBACK enables internal loopback in all eight PHYs. When asserted, data is internally wrapped within each PHY and does not appear on the network. While in the looped-back state, all network lines are placed in a noncontentious state. MLT3BLOCK 69 I MLT-3 block. Pulling MLT3 BLOCK terminal high enables the MLT-3 detector circuit and prevents the TNETE2008 from asserting link or carrier sense in the presence of 100BASE-T data. Setting MLT3BLOCK terminal low disables the MLT-3 detectors on all eight ports for applications that require this. RESET 46 I Global reset. RESET is used to reset all eight PHY sections. RCVTHRESH 44 I Receive threshold. RCVTHRESH selects the threshold level of the receiver squelch circuit. For normal IEEE Std 802.3 operation, this pin should be tied low. Setting RCVTHRESH high slightly lowers the threshold level, allowing the PHY to receive data over extended lengths of cable for all eight PHYs. PWRDOWN 45 I Power down. When asserted, PWRDOWN places all eight PHYs in a low power state. Transmitting and receiving are inhibited in this state. LOOPBACK † A = analog, I = input not connected TERMINAL NAME NC DESCRIPTION NO. 31, 32, 33, 34, 35, 56, 57, 58, 59, 60, 91, 92, 93, 94, 116, 117, 118, 119, 120 No connection. No internal connection for these terminals. power interface TERMINAL NAME NO. TYPE‡ DESCRIPTION AGND 42 GND Ground terminal for analog circuitry AVDD GND 40 PWR 55, 71, 81, 95, 96 GND VDD terminal for analog circuitry. Connect to 3.3 V. Logic ground terminals RCVGND 109 GND Ground terminal for receiver circuitry RCVVDD 112 PWR VDD terminals for receiver circuitry. Connect to 3.3 V. XMTGND 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28, 36, 115 GND Ground terminals for transmit circuitry XMTVDD 38 PWR VCC 48 PWR VDD terminal for transmit circuitry. Connect to 3.3 V. Power. Supply for JTAG port interface. Can be 5 V or 3.3 V, depending on test system interface requirements. VDD 50, 65, 76, 86 ‡ GND = ground, PWR = power PWR Logic VDD terminals. Connect these to 3.3 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 Terminal Functions (Continued) 10BASE-T interface TERMINAL TYPE† DESCRIPTION 114 111 108 106 104 102 100 98 A Half of the receive pair to PHY0-PHY7. Differential line-receiver inputs connect to receive pair through transformer isolation. RCVN0 RCVN1 RCVN2 RCVN3 RCVN4 RCVN5 RCVN6 RCVN7 113 110 107 105 103 101 99 97 A Half of the receive pair to PHY0-PHY7. Differential line-receiver inputs connect to receive pair through transformer isolation. XMTN0 XMTN1 XMTN2 XMTN3 XMTN4 XMTN5 XMTN6 XMTN7 2 6 10 14 18 22 26 30 A Half of the transmit pair. Differential line-transmitter outputs from PHY0–PHY7. XMTP0 XMTP1 XMTP2 XMTP3 XMTP4 XMTP5 XMTP6 XMTP7 1 5 9 13 17 21 25 29 A Half of the transmit pair. Differential line-transmitter outputs from PHY0–PHY7. NAME NO. RCVP0 RCVP1 RCVP2 RCVP3 RCVP4 RCVP5 RCVP6 RCVP7 † A = analog 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 functional description Figure 3 is a simplified diagram of one of the eight TNETE2008 PHY interfaces. The diagram indicates the functionality of each PHY but is not a complete representation of the PHY structure or operation. RCVP Receiver RCVN 1 Digital PLL 0 Manchester Decoder Elastic Buffer IFRXD Carrier Sense Intelligent Squelch IFCRS Clock Generator CLK IFCLK LOOPBACK Watchdog Timer IFTXD Manchester Encoder Wave-Shaping Filter D-to-A Converter IFTXEN IFDUPLEX Line Driver XMTP XMTN Link-Pulse Generator Collision Generator IFFORCEHD Disable Duplex Register Link-Pulse Detector IFCOL IFLINK Autonegotiation Figure 3. Block Diagram (x8) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 10BASE-T differential line-transmitter function Each TNETE2008 differential line driver drives a balanced, properly terminated twisted-pair transmission line with a nominal characteristic impedance of 100 Ω. In the idle state, the driver maintains a minimum differential output voltage while staying within the required common-mode voltage range. The driver incorporates an on-chip wave-shaping and high-frequency filtering stage so the outputs can be connected directly to isolation transformers through series-termination resistors. No external filters are required. After transmission has ceased on a PHY, and for a minimum of 250 ns, the driver maintains full differential outputs, which thereafter begin to decay to the minimum differential level. Each PHY also transmits regular link pulses in compliance with IEEE Std 802.3. In half-duplex mode, interface carrier sense (IFCRS) asserts during transmits. 10BASE-T differential line-receiver function The line-receiver terminals of each PHY must be connected to a properly terminated transmission line via an external isolation transformer. The receiver establishes its own common-mode input-bias voltage. Data received from the network is output on the IFRXD terminals of the interface. The receiver incorporates an intelligent squelch function that allows incoming data to pass only if the input amplitude is greater than a minimum signal threshold and a specific pulse sequence is received. This protects against impulse line noise being mistaken for signal or line activity. The squelch circuits quickly deactivate if received pulses fall outside the specifications. Over-long pulses are not mistaken as link pulses. There are two choices for signal thresholds via the RCVTHRESH terminal. Selecting the lower squelch value (selected by pulling RCVTHRESH high) may operate over longer cables but does not meet IEEE minimum squelch levels. For this reason, it is recommended that this terminal be tied low. Each channel’s squelch circuit contains an MLT-3 (100BASE-T data format) detector, which, when enabled via MLT3BLOCK pulled high, prevents the receiver from opening the squelch when MLT-3 data is present. IFCRS is asserted while the squelch function is active to indicate that the circuit is allowing data to pass from the twisted pair. IFCRS is deasserted when the squelch circuit is disabling data flow, although the receive elastic buffer still may be outputting data. jabber detection Each PHY monitors the length of the packet being transmitted. If a single packet exceeds 24 ms, then a jabber condition is flagged. The output is disabled, the IFCOL (collision) signal is asserted, and the IFCRS signal is deasserted. To clear the jabber function, it is necessary to cease transmission for a minimum of 400 ms. link test When not in autonegotiation mode, each PHY transmits link pulses on the XMTP/XMTN outputs, separated by an interval of 19 ms. The receiver looks for valid link pulses on the input pair. If a link pulse is not received within a given time interval, ≅ 100 ms, then the PHY enters a link-fail state. In this state, link pulses continue to be generated, and the receiver constantly looks for the link-pulse pattern. The PHY remains in this state until a valid receive packet or multiple legal link test pulses are received. When link pulses are not detected, the IFLINK signal is deasserted and transmission of data is inhibited. Also, an activated enabled MLT-3 decoder inhibits the receive function for MLT-3 encoded data and can, therefore, prevent assertion of IFLINK or, if already asserted, cause deassertion of IFLINK if the MLT-3 encoded data persists for longer than 100 ms. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 polarity reversal The TNETE2008 can detect reversed polarity of its receiver inputs (e.g., due to incorrect cable wiring). If at any time, seven consecutive inverted link pulses are detected, then, reversed polarity is assumed, and the octal swaps the RCVP and RCVN inputs of the affected PHY. Once a single, correct link pulse is received, good polarity is assumed. autonegotiation The TNETE2008 supports IEEE Std 802.3 autonegotiation to full duplex where allowed by a link partner. Each PHY on the device is capable of independent autonegotiation. When enabled, this feature allows a PHY to negotiate with the other PHY on its link segment, to establish their highest common protocol. Until a PHY has completed its negotiation, it does not assert IFLINK. When autonegotiation is disabled for a PHY, via the extended multiplexed MAC interface, link is indicated on receipt of valid data or link pulses. loopback test mode By asserting the LOOPBACK terminal on the device, the transmit circuit of each PHY is looped to the corresponding receive circuit; therefore, transmit drivers do not forward any further packet data to the network but continue to send link pulses. Since there is only one LOOPBACK terminal on the package, all eight PHYs simultaneously are placed into loopback mode. While in loopback mode, all network receive activity, other than the link pulses, is ignored. However, squelch information is still processed, allowing the link status to be maintained under momentary loopback self-test. During loopback, IFLINK is driven high for all channels, regardless of the state of the links on all channels. When LOOPBACK goes high, the true state of link on each channel is reported. Although the TNETE2008 places no restrictions on the format of transmitted data, looped-back data should begin with a preamble and a start-of-frame delimiter to avoid spurious behavior of the receive-data recovery circuitry. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 LED status indication The TNETE2008 has 7 pins that drive 24 LEDs in a multiplexed format, as shown in Figure 4. 180 Ω LSEL6, 7 DUPCOL6 DUPCOL7 LSEL4, 5 DUPCOL4 LINK7 ACTIVE4 ACTIVE5 LINK4 LINK5 180 Ω DUPCOL2 DUPCOL3 LSEL0, 1 ACTIVE7 LINK6 180 Ω DUPCOL5 LSEL2, 3 ACTIVE6 ACTIVE2 ACTIVE3 LINK2 LINK3 180 Ω DUPCOL0 DUPCOL1 ACTIVE0 ACTIVE1 LINK0 LINK1 LDUPCOL LACTIVE LLINK Figure 4. LED External Connection status LED states 12 LINK LED Illuminates when its PHY has established a valid link. The LED flashes at 2 Hz during autonegotiation. ACTIVE LED Illuminates when its PHY is transmitting or receiving data. The LED flashes at 19 Hz during continuous activity. DUPCOL LED Illuminates continuously when its PHY is in full-duplex mode and illuminates for a minimum duration of 20 ms when collisions occur in half-duplex mode. In the event of continuous or frequent collisions, this LED flashes at 19 Hz. In jabber mode it flashes at 1 Hz. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 LED control signals LACTVE, LLINK, and LDUPCOL Outputs are each capable of sourcing and sinking up to 40 mA; active low for even, active high for odd-numbered channels. LSEL0–LSEL7 Outputs each source/sink 10 mA; active low for odd, active high for even-numbered channels. When RESET is active (low), all LEDs are illuminated during their time slot as a lamp test feature, regardless of the state of the corresponding status signal. CLK input must be driven with a valid clock for this to occur. JTAG test access port Compliant with IEEE Std 1149.1, the TAP is composed of five terminals. These terminals interface serially with the device and the board on which it is installed for boundary-scan testing. The TNETE2008 implements the following JTAG instructions: INSTRUCTION TYPE JTAG OPCODE NAME ACTION Mandatory EXTEST 0000 External boundary-scan test Mandatory SAMPLE/PRELOAD 0001 Initialization for boundary-scan test Optional IDCODE 0100 Scans out TNETE2008 identification code Optional HIGHZ 0011 Sets all digital output pins on TNETE2008 to high impedance Mandatory BYPASS 1111 Connects 1-bit bypass register between TDI and TDO The IDCODE for the TNETE2008 is: CODE VARIANT PART NUMBER MANUFACTURER LEAST SIGNIFICANT BYTE Binary 0000b 0000000001010000 000 0001 0111b 1b The JTAG terminals do not have internal pullup resistors, so, to comply fully with IEEE Std 1149.11, external resistors must be connected to JTMS, JTCLK, JTDI, and JTRST. All other JTAG opcodes are reserved for manufacturing test and should not be used. global reset logic At initial power up, the TNETE2008 performs an internal reset. No external reset circuitry is required. However, operation of the TNETE2008 is not specified for 50 ms after power up. During operation, a full reset of the device can be performed by taking RESET low for not less than 50 µs. Operation of the device is not ensured for 5 ms after reset ends. The device resets itself if CLK is lost for any reason. CLK loss is detected in 200 µs. Data is not valid on the multiplexed MAC interface until normal operation resumes, after any reset, and then after two complete IFSYNC cycles have passed. All signals in the multiplexed MAC interface are driven to 0 during reset, except for IFSYNC, which is driven to 1 during reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 synchronous PHY interface To ease the pin-count burden on switching-application devices, Texas Instruments developed a multiplexed interface, which allows multi-PHY devices to be connected to switching cores without using many terminals. To achieve the reduction in terminal count, the interface takes advantage of the fact that modern silicon is able to operate at frequencies much higher than the 10-MHz data rate of the standard interface. The receive and transmit data are transferred over a nibble-wide bus, (see Figure 5). Table 1 describes the signals on the interface. Any given port only transfers data at 2.5 MHz (2.5 MHz × 4 bits = 10 Mbit/s). The remaining control and status signals are sampled at the reduced rate of 2.5 MHz. PHY IFCLK IFSYNC IFCOL IFCRS IFLINK IFDUPLEX IFRXD3–IFRXD0 IFRXDV IFTXD3–IFTXD0 IFTXEN IFFORCEHD MAC CLK SYNC COL CRS LINK DUPLEX RXD3–RXD0 RXDV TXD3–TXD0 TXEN FORCEHD Figure 5. Multiplexed 17-Pin Interface for Eight Ports The interface runs synchronously to a TNETE2008 generated clock. The information (MAC → TNETE2008) for the first port (port 0) is presented on the interface when IFSYNC is high; the next clock cycle the interface carries the information for the second port. This process continues with each port using the interface for one cycle. When all ports have been processed in this manner, the sequence resumes with the first port and again IFSYNC is asserted. To improve latency-related issues, the data from the TNETE2008 to the MAC is skewed by two slots as shown by the dashed line in Figure 6. This allows the MAC to respond to input signals from the TNETE2008 in the same 400-ns cycle, rather than waiting for the next 400-ns cycle, which would be the case if the signals were not skewed. If the mode to be advertised during autonegotiation arrives on IFTXD3–IFTXD0 during link-invalid, IFFORCEHD can be tied high or used to restart autonegotiation. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 timing diagram The basic signals on the multiplexed interface and their alignment to IFCLK and IFSYNC are shown in Figure 6. All input signals change on the rising edge of IFCLK and are sampled by the TNETE2008 on the rising edge of IFCLK. All output signals, except IFSYNC, change on the falling edge of IFCLK and should be sampled by the MAC on the rising edge of IFCLK. The IFSYNC output changes on the rising edge of IFCLK and should be sampled by the MAC on the falling edge of IFCLK. PORT 0 1 2 3 4 5 6 7 0 1 IFCLK (output) IFSYNC (output) IFTXD3– IFTXD0 (input) M00TXD M01TXD M02TXD M03TXD M04TXD M05TXD M06TXD M07TXD M00TXD M01TXD IFTXEN (input) M00TXEN M01TXEN M02TXEN M03TXEN M04TXEN M05TXEN M06TXEN M07TXEN M00TXEN M01TXEN M01FHD M02FHD M03FHD M04FHD M05FHD M06FHD M07FHD M00FHD M01FHD IFFORCEHD (input) M00FHD IFCOL (output) M02COL M03COL M04COL M05COL IFCRS (output) M02CRS M03CRS M04CRS M05CRS IFLINK (output) M02LINK M03LINK M04LINK M05LINK M02DUPLEX M03DUPLEX M04DUPLEX IFRXD3– IFRXD0 (output) M02RXD M03RXD IFRXDV (output) M02RXDV M03RXDV IFDUPLEX (output) M06COL M07COL M00COL M01COL M02COL M03COL M06CRS M07CRS M00CRS M01CRS M02CRS M03CRS M06LINK M07LNK M00LINK M01LINK M02LINK M03LINK M05DUPLEX M06DUPLEX M07DUPLEX M00DUPLEX M01DUPLEX M02DUPLEX M04RXD M05RXD M06RXD M07RXD M00RXD M01RXD M02RXD M03RXD M04RXDV M05RXDV M06RXDV M07RXDV M00RXDV M01RXDV M02RXDV M03RXDV M03DUPLEX Note: Dashed line shows data from TNETE2008 to MAC is skewed by two slots. Figure 6. MAC Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 bit ordering within nibbles Normally, network packet data is transferred from the TNETE2008 to the MAC for a particular PHY when, during its time slot, IFRXDV and IFLINK are both high. There is an opportunity to send other information to the MAC when either of these two signals is not high. Similarly, the MAC transfers packet information to a particular PHY in the TNETE2008 when IFLINK and IFTXEN are both high during that PHY’s time slot. There is an opportunity to send other information to TNETE2008 when either of these two signals is not high. Currently, the only extended data used in this interface is sending allowed autonegotiating modes to the PHY channels when IFTXEN and IFLINK are both low, and reporting mode, when autonegotiation is successfully completed, and when IFLINK and IFRXDV both are low. Table 1 shows the possible classes of data based on IFLINK and IFTXEN for data to the TNETE2008 from the MAC, and based on IFLINK and IFRXDV for data from the TNETE2008 to the MAC. Table 1. Transmit and Receive Data Nibbles IFLINK IFTXEN IFTXD3–IFTXD0 COMMENT 0 0 0000–1111 Extension-specific information 0 1 Reserved Reserved for future extension 1 0 0000 Normal interframe 1 0 0001–1111 Reserved 1 1 0000–1111 Normal data transmission IFLINK IFRXDV IFRXD3–IFRXD0 COMMENT 0 0 0000–1111 Extension-specific information 0 1 Reserved Reserved for future extension 1 0 0000 Normal interframe 1 0 0001–1111 Reserved 1 1 0000–1111 Normal data transmission Figure 7 defines the bits-to-nibble-to-byte ordering and translation used in the multiplexed interface. MAC Serial Bit Stream First Bit LSB D0 D1 D2 D3 D4 D5 First Nibble D7 MSB Second Nibble LSB D(0) D(1) D(2) MSB D(3) TNETE2008 Nibble Stream Figure 7. Data Stream 16 D6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 non-data MAC-to-PHY and PHY-to-MAC control exchanges Autonegotiation parameters can be sent to the TNETE2008 by the MAC and the results of the link negotiation reported to the MAC using the multiplexed data pins during non-network data time (IFLINK = 0). This signaling system also allows the MAC to force the configuration of the TNETE2008 duplex and pause modes to those it requested. When IFLINK and IFTXEN are deasserted, duplex, pause, speed, and force configuration information is transferred from MAC to TNETE2008 on terminals IFTXD0, IFTXD1, IFTXD2, and IFTXD3, respectively. When IFLINK and IFRXDV are deasserted, duplex, pause, and speed information is transferred from TNETE2008 to MAC on terminals IFRXD0, IFRXD1, and IFRXD2, respectively. Figure 8 shows the control information exchange for the case where the MAC is not forcing the configuration of the link. In this case, the link configuration is determined by autonegotiation. The TNETE2008 latches the final requested values just before FLP exchange commences. The diagrams show only one channel; for clarity, time slices from other PHYs are not shown interspersed with the sample channel. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 IFCLK (output) Clock Must Run Continuously IFTXEN (input) IFTXD3 (input) Force_Conf (0 = no force conf) IFTXD2 (input) Speed (0 = 10 Mbit/s) IFTXD1 (input) Pause (0 = request no pause) IFTXD0 (input) Half Duplex (0 = request, full duplex when IFFORCEHD = 1) IFLINK (output) IFFORCEHD Renegotiation (input) TNETE2008 Latches Final Values, Just Before Autonegotiation FLP Exchange Commences. Restarts Autonegotiation Setup IFRXDV (output) IFRXD3 (output) Must Be 0 IFRXD2 (output) Speed (0 = 10 Mbit/s) IFRXD1 (output) Pause (0 = no pause) IFRXD0 (output) Half Duplex (0 = full duplex) 1200 ms MIN Link Fails OR Renegotiation Autonegotiate Commences IFCLK IFLINK IFRXDX IFRXD Final Value 750 ms MIN 80 ms MIN Link Good Negotiated Link Protocol Latch Final Values When IFLINK↑ (Expanded View) IFLINK = 1: IFRXD Final Value Latched on Previous Edge Figure 8. MAC-to-PHY, PHY-to-MAC Control Exchanges for Not Force Configuration Mode 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 non-data MAC-to-PHY and PHY-to-MAC control exchanges Figure 9 shows the control information exchange for the case where the MAC is forcing the configuration of the link. In this case the link is established by link pulse detection and is configured as specified by the MAC. The TNETE2008 latches the final values just before IFLINK asserts. The force configuration mode should be used only when the abilities of the link partner are known or set to be the same as those forced. Failure to do this could result in an incompatibly configured link, e.g., TNETE2008 full duplex and link partner half duplex. IFLINK going low or any transition on IFFORCEHD can trigger renegotiation. If a new trigger occurs before a negotiation completes, the process starts over at the beginning of an enforced 1.2-s wait. At the end of an undisturbed 1.2-s wait, the state of IFFORCEHD and IFTXD3–IFTXD0 determines the modes advertised to the link partner. IFFORCEHD low commands half duplex; only IFFORCEHD high allows the value clocked from IFTXD0 to determine duplex mode. In the force configuration mode, IFTXD0 alone determines the duplex mode for the next time link is established. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 IFCLK (output) Clock Must Run Continuously IFTXEN (input) IFTXD3 (input) IFTXD2 (input) Force_Conf (1 = force conf) Speed (0 = 10 Mbit/s) IFTXD1 (input) Pause (0 = force no pause) IFTXD0 (input) Half Duplex (0 = full duplex) Octet Latches Final Values, Just Before IFLINK Asserts. IFLINK (output) IFFORCEHD Renegotiation (input) Restarts Autonegotiation Setup IFRXDV (output) IFRXD3 (output) Must Be 0 IFRXD2 (output) Speed (0 = 10 Mbit/s) IFRXD1 (output) Pause (0 = no pause) IFRXD0 (output) Half Duplex (0 = full duplex) Link Pulse Detection Link Fails or Renegotiation Latch Final Values When Link↑ Link Good Figure 9. MAC-to-PHY, PHY-to-MAC Control Exchanges for Force Configuration Mode 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 absolute maximum ratings over operating junction temperature range (unless otherwise noted)† Normal power-supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V ± 5% DC voltage range applied to logic outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.05 V to VDDMAX DC voltage applied to logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V DC differential voltage at receiver pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.25 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 95°C Thermal resistance, junction to ambient, RqJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to GND, and all GND terminals should be routed to minimize inductance to system ground. recommended operating conditions MIN NOM MAX UNIT 3.15 3.3 3.45 V VDD VCC Supply voltage JTAG supply voltage (see Note 2) 5 VCC VIH JTAG supply voltage (see Note 2) 3.3 VIL IOH Low-level input voltage (see Note 3) IOL IOH Low-level output current High-level output current LED function terminals IOL IOH Low-level output current LED function terminals 40 mA –10 mA High-level input voltage 2 –0.5 High-level output current High-level output current LED group select terminals V V VDD+0.5 0.8 V V –4 mA 4 mA –40 mA IOL Low-level output current LED group select terminals 10 mA NOTES: 2. VCC is selected by JTAG test system interface requirements. 3. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOH VOL High-level output voltage IOZ IIH High-impedance current IIL Low-level output current TEST CONDITIONS IOH = MAX IOL = MAX Low-level output voltage High-level output current IDD Supply current Cdin Digital inputs Cdout Digital outputs Clsel Clstat MIN TYP UNIT V VIN = MAX VIN = GND VDD = MAX MAX 2.4 0.5 V ±10 µA ±10 µA ±10 µA See Note 4 110 125 See Note 5 220 280 mA 1.5 pF 1 pF LED select outputs (LSELxx) 3.5 pF LED status outputs 10 pF Cjin JTAG inputs 2.5 pF Cjout JTAG outputs 3 pF NOTES: 4. Full-duplex mode, while transmitting and receiving maximum data packet size with correct line termination and minimum interframe gaps. This is a per-port value. 5. Full-duplex mode, valid link on all PHYs, and no data activity. This is total device value. oscillator requirements MIN CLK frequency NOM MAX 20 CLK frequency error –100 CLK duty cycle VOH Trise, Tfall (see Note 6) UNIT MHz 100 ppm 40 60 % 2 VDD 6 V ns MIN MAX UNIT –2 10 NOTE 6: Measured at 10%–90% transistion low-to-high or high-to-low points operating characteristics over recommended operating conditions clock sync delay (see Figure 10) NO. 1 PARAMETER td(IFSYNC) Delay time from IFCLK↑ to IFSYNC state change IFCLK (output) 1 1 IFSYNC (output) Figure 10. Clock Sync Delay 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 clock limits (see Figure 11) NO. 1 2 3 4 PARAMETER MIN TYP MAX 50 UNIT tc(IFCLK) tw(IFCLK) Cycle time Pulse width high 22.5 27.5 ns ns tw(IFCLK) tr(IFCLK) Pulse width low 22.5 27.5 ns 2 ns 2 ns Rise time (see Note 7) 5 tf(IFCLK) Fall time (see Note 7) NOTE 7: Measured between 10% and 90% levels of IFCLK amplitude 1 2 3 4 5 IFCLK (output) Figure 11. Clock Limits receive output interface (see Figure 12) NO. 2 2 2 2 2 2 PARAMETER MIN MAX UNIT td(IFCOL) td(IFCRS) Delay time, from IFCLK↓ to IFCOL valid (see Note 8) –2 10 ns Delay time, from IFCLK↓ to IFCRS valid (see Note 9) –2 10 ns td(IFLINK) td(IFRXD) Delay time, from IFCLK↓ to IFLINK valid –2 10 ns Delay time, from IFCLK↓ to IFRXD valid (see Note 10) –2 10 ns td(IFRXDV) td(IFDUPLEX) Delay time, from IFCLK↓ to IFRXDV invalid (see Note 11) –2 10 ns Delay time, from IFCLK↓ to IFDUPLEX valid –2 10 ns NOTES: 8. For IFRX data, the TNETE2008 asserts IFCOL during the appropriate time slot if there was a collision event during previous time slot. 9. For IFRX data, the TNETE2008 asserts IFCRS during the appropriate time slot if carrier was detected during previous time slot. 10. The TNETE2008 does not echo transmit data back on the IFRXD3–IFRXD0 terminals during normal operations. 11. The TNETE2008 asserts IFRXDV for IFRX data if there are four valid bits of data in the nibble. Dribble bits at the end of the frame are discarded. IFCLK (output) IFCOL IFCRS IFLINK IFRXD3–IFRXD0 IFRXDV IFDUPLEX (outputs) 2 2 Valid Figure 12. Multiplexed Receive Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 transmit input interface (see Figure 13) NO. 2 PARAMETER MIN UNIT tsu(IFTXEN) tsu(IFTXD) Setup time, from IFTXEN valid to IFCLK↑ 15 ns 2 Setup time, from IFTXD valid to IFCLK↑ 15 ns 2 tsu(IFFORCEHD) Setup time, from IFFORCEHD valid to IFCLK↑ 15 ns 3 Hold time, from IFCLK↑ to IFTXEN invalid 0 ns 3 th(IFTXEN) th(IFTXD) Hold time, from IFCLK↑ to IFTXD invalid 0 ns 3 th(IFFORCEHD) Hold time, from IFCLK↑ to IFFORCEHD invalid 0 ns IFCLK (output) 2 IFTXEN IFTXD3–IFTXD0 IFFORCEHD (inputs) 3 Valid Figure 13. Multiplexed Transmit Interface 24 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 LED drive timing To sample this interface, count 32 clocks from the falling edge of RESET, and take samples every 32 clocks (1600 ns) thereafter. Sampling is shown in Table 2. LED drive (see Figure 14) NO. 1 2 td(Sample X) tw(Sample X) PARAMETER MIN Delay time from RESET↓ to S0 active 625 Pulse duration (see Notes 12 and 13) TYP 1600 MAX UNIT 750 ns ns NOTES: 12. LED interface runs synchronously to CLK signal, 32 clocks/sample at constant numbers of CLK periods. Phase of CLK, relative to LSEL transitions, is not controlled. 13. Active low for odd channels and active high for even channels 32 Clocks 32 Clocks CLK RESET (input) 1 LSEL 0,2,4,6 LSEL 1,3,5,7 (outputs) ÎÎÎÎÎÎ ÎÎÎÎÎÎ 2 2 Sample 0 Sample 1 Figure 14. LED Drive Timing Table 2. LED Drive Timing SAMPLE (SEE NOTE 14) LSEL0,1 LSEL2,3 LSEL4,5 LSEL6,7 0 link1 link3 link5 link7 1 active0 active2 active4 active6 2 dupcol0 dupcol2 dupcol4 dupcol6 3 link0 link2 link4 link6 4 active1 active3 active5 active7 5 dupcol1 dupcol3 dupcol5 dupcol7 6 (same as sample 0) link1 link3 link5 link7 7 (same as sample 1) active0 active2 active4 active6 NOTE 14: In general, sample (n) = sample (n + 6), sample (n – 6). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 receive-data timing The TNETE2008 buffers receive data in an elastic first-in, first-out (FIFO) buffer so that receive data can be synchronous to the TNETE2008 20-MHz clock. receive data (see Figure 15) NO. 1 2 3 4 PARAMETER td(RDLAT) td(CRS) Receive-data latency time td(RDV) td(CRSHO) Delay time, from RCVP/RCVN valid to IFRXD valid Carrier sense assertion delay Delay time, from RCVP/RCVN idle to IFCRS↓ MIN TYP MAX UNIT 1350 1950 2550 ns 125 850 1300 ns 1800 2850 3800 ns 0 0 450 ns RCVP/ RCVN (input) IFCLK (output) IFSYNC (output) IFCRS (output) IFRXDV (output) 2 4 3 1 Figure 15. Receive Data 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 transmit data (see Figure 16) NO. 1 2 PARAMETER td(XMTP/N) td(TDLAT) MIN TYP MAX UNIT Delay time from IFTXEN↑ to XMTP/XMTN active 50 75 100 ns Transmit-data latency time 50 175 500 ns IFCLK (output) IFSYNC (output) IFTXEN (input) IFTXD3– IFTXD0 (input) (for this channel) 1 2 XMTP XMTN (outputs) Figure 16. Transmit Data POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 collision-detection timing IFCOL is asserted for a minimum of 600 ns when transmission and reception of data occur simultaneously and the mode is in half duplex. IFCOL is not active during link fail or in full-duplex mode. Figure 17 shows the collision-detect timing. During a collision, the data output on IFRXD is not valid received data. collision detect (see Figure 17) NO. 1 2 PARAMETER td(IFCOLON) td(IFCOLOFF) MIN TYP MAX UNIT Delay time, collision detect RCVP/RCVN valid to IFCOL↑ 125 475 1300 ns Delay time, collision off IFTXEN↓ to IFCOL↓ 600 700 1450 ns 1 2 RCVP RCVN (input) IFCLK (output) IFSYNC (output) IFTXEN (input) IFCOL (output) Collision Event Figure 17. Collision Detect 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 loopback (see Figure 18) NO. 1 PARAMETER td(RDLAT) td(LCRS) Receive-data latency time 2 3 td(IFRXDV) Delay time from TXEN↑ active to IFRXDV↑ 4 td(LCRSHO) Delay time from receive idle to IFCRS↓ Carrier sense assertion delay MIN TYP MAX UNIT 1350 1900 2550 ns 300 300 300 ns 1750 2300 3100 ns 0 0 300 ns IFCLK (output) IFSYNC (output) IFTXEN (input) IFCRS (output) IFRXDV (output) 2 4 3 1 Figure 18. Loopback POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION tf 90% 10% 1.5 V tr 90% 10% td, th, ts, tw, tc 1.5 V Figure 19. Parameter Measurement 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 V (high) 0.8 V (low) TNETE2008 OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES SPWS042B – DECEMBER 1997 – REVISED JUNE 1998 MECHANICAL DATA PBE (S-PQFP-G120) PLASTIC QUAD FLATPACK 0,45 0,30 0,80 90 0,20 M 61 91 60 120 31 0,16 NOM 1 30 23,20 TYP 28,20 SQ 27,80 31,45 SQ 30,95 Gage Plane 0,25 0,25 MIN 3,60 3,20 0°– 7° 1,03 0,73 Seating Plane 0,10 4,10 MAX NOTES: A. B. C. D. 4040127/B 09/96 All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced molded plastic package with a heat spreader (HSP) Falls within JEDEC MS-022 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 PACKAGE OPTION ADDENDUM www.ti.com 4-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TNETE2008PBE OBSOLETE HQFP PBE Pins Package Eco Plan (2) Qty 120 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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