ADC Scaling UG0657 User Guide Table of Contents Introduction ....................................................................................................................3 Hardware Implementation .............................................................................................4 Inputs and Outputs ........................................................................................................................................ 5 Configuration Parameters .............................................................................................................................. 5 Resource Utilization ....................................................................................................................................... 6 List of Changes ..............................................................................................................7 Product Support.............................................................................................................8 Customer Service .......................................................................................................................................... 8 Customer Technical Support Center ............................................................................................................. 8 Technical Support .......................................................................................................................................... 8 Website .......................................................................................................................................................... 8 Contacting the Customer Technical Support Center ..................................................................................... 8 ITAR Technical Support ................................................................................................................................ 9 2 UG0657: ADC Scaling User Guide Introduction An analog to digital converter (ADC) converts a voltage signal as input to a digital signal in a number of bits that depends on ADC resolution. The signals that are not readily available in voltage form, for example, current, are converted to a voltage signal through some signal processing. The digital signal output of the ADC that is relative to its bit width should be scaled to a value that can be properly interpreted by the system that processes the signal. The digital output of ADC can have an unintended DC offset that could be generated by the signal processing circuit before ADC input or the ADC itself. The offset value in signal measurement should be removed before using it in digital algorithm. The ADC scaling performs the following functions: • Performs auto offset computation initially: Involves disabling PWM and triggering the ADC by a pre-determined number of times (8192) to determine zero current. • • ChX_offset = adc_result_chX_i + ChX_offset EQ1 Scales raw ADC data into phase currents: Iph = (adc_result_chX_i − ChX_offset/8192) ∗ adc_scale_val_i EQ2 Detects over current fault after phase current computation, which can be used to stop the motors immediately. UG0657: ADC Scaling User Guide 3 Hardware Implementation Figure 1 shows the block diagram of ADC scaling. reset_i done_o sys_clk_i calib_done_o adc_results_ready_i adc_scale_val_i ADC Scaling adc_result_ch0_i over_current_fault_o ia_adc_o adc_result_ch1_i ib_adc_o fault_threshold_i Figure 1. System-level Block Diagram of ADC Scaling The ADC scaling accumulates the first 8,192 samples of adc_result_ch0_i and adc_result_ch1_i. The calib_done_o signal is asserted after 8,192 samples are accumulated. The accumulated data is averaged and subtracted from each sample thereafter. This value is multiplied with adc_scale_val_i to give the actual ADC result. The block also asserts the over_current_fault_o when the scaled currents are more than the fault_threshold_i value. During simulation, the block need not accumulate a large number of samples. The g_DEBUG parameter can be set to 1 to reduce the number of samples that are accumulated to 5, while setting it to 0 accumulates 8,192 samples. UG0657: ADC Scaling User Guide 4 Hardware Implementation Inputs and Outputs Table 1 shows the input and output ports of ADC scaling. Table 1. Inputs and Outputs of ADC Scaling Signal Name Direction Description reset_i Input Asynchronous active low reset signal to design. sys_clk_i Input System clock. adc_results_rdy_i Input Trigger indicating ADC inputs are available. adc_scale_val_i Input Scaling value for currents. adc_result_ch0_i Input Channel 0 result from ADC. adc_result_ch1_i Input Channel 1 result from ADC. fault_threshold_i Input Threshold value of current above which a fault is indicated. done_o Output Indicates completion of scaling operations – high for one clock cycle. calib_done_o Output A constant high signal indicates offset calibration is complete. over_current_fault_o Output Indicates that at least one of the currents have exceeded the fault_threshold_i input value. The signal goes back to zero (not latched) when all the currents are less than fault_threshold_i. ia_adc_o Output Scaled current value for phase a (from Channel 0). ib_adc_o Output Scaled current value for phase b (from Channel 1). Configuration Parameters Table 2 shows the description of the configuration parameters used in the hardware implementation of ADC scaling. These are generic parameters and can be varied as per the requirement of the application. Table 2. Configuration Parameters Signal Name g_DEBUG Description When 0 supports Synthesis. When 1 supports Simulation. g_ADC_RESULTS_WIDTH Defines the width of the inputs from ADC Measurements block. g_STD_IO_WIDTH Defines the width of the input and output signals. g_APB3_IF_DATA_WIDTH Defines the width of the data from the APB3 interface. g_NO_MCYCLE_PATH Defines the number of clock delays required before asserting the multiplier done signal. UG0657: ADC Scaling User Guide 5 Hardware Implementation Resource Utilization ® ADC scaling is implemented on the SmartFusion 2 system-on-chip (SoC) field programmable gate array (FPGA) and ® IGLOO 2 devices. Table 3 shows the resource utilization report after synthesis with g_STD_IO_WIDTH value equal to 18. Table 3. Resource Utilization Report of PWM Scaling Cell Usage 6 Count SLE (Sequential) 138 Combinational Logic 260 MACC 1 RAM1Kx18 0 RAM64x18 0 UG0657: ADC Scaling User Guide List of Changes The following table shows important changes made in this document for each revision. Date and Revision Revision 1 (October 2015) Change Initial release. UG0657: ADC Scaling User Guide Page N/A 7 Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. 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