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STEF05
Electronic fuse for 5 V line
Datasheet − production data
Features
■
Continuous current (typ): 3.6 A
■
N-channel on-resistance (typ): 40 mΩ
■
Enable/Fault functions
■
Output clamp voltage (typ): 6.65 V
■
Undervoltage lockout
■
Short-circuit limit
■
Overload current limit
■
Controlled output voltage ramp
■
Thermal latch (typ): 165 °C
■
Uses tiny capacitors
■
Operating junction temp. - 40 °C to 125 °C
■
Available in DFN10 (3x3 mm) package
DFN10 (3x3 mm)
Applications
■
Hard disk drives
■
Solid state drives (SSD)
■
Hard disk and SSD arrays
■
Set-top boxes
■
DVD and Blu-ray disc drivers
Description
The STEF05 is an integrated electronic fuse
optimized for monitoring output current and input
voltage. Connected in series to a 5 V rail, it is
capable of protecting the electronic circuitry on its
output from overcurrent and overvoltage. The
device has a controlled delay and turn-on time.
When an overload condition occurs, the STEF05
limits the output current to a predefined safe
value. If the anomalous overload condition
Table 1.
persists, it goes into an open state, disconnecting
the load from the power supply. If a continuous
short-circuit is present on the board, when power
is re-applied the E-fuse initially limits the output
current to a safe value, and then again goes into
an open state. The device is equipped with a
thermal protection circuit. The intervention of the
thermal protection is signalled to the board
monitoring circuits through a signal on the Fault
pin. Unlike mechanical fuses, which must be
physically replaced after a single event, the Efuse does not degrade in its performance after
short-circuit/thermal protection interventions and
it is reset either by recycling the supply voltage or
using the Enable pin. The companion chip for
12 V power rails is also available with part number
STEF12.
Device summary
Order code
Package
Packaging
STEF05PUR
DFN10 (3x3 mm)
Tape and reel
January 2013
This is information on a product in full production.
Doc ID 019055 Rev 5
1/20
www.st.com
20
Contents
STEF05
Contents
1
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1
Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.2
Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.3
Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.4
Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.5
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
R limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3
Cdv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4
Enable/Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Doc ID 019055 Rev 5
STEF05
Device block diagram
1
Device block diagram
Figure 1.
STEF05 block diagram
AM09891v1
Doc ID 019055 Rev 5
3/20
Pin configuration
2
STEF05
Pin configuration
Figure 2.
Pin configuration (top view)
Source
Source
Source
Source
Source
GND
dv/dt
En/fault
I-Limit
N/C
VCC
AM09867v1
Table 2.
Pin description
Pin n°
Symbol
Note
1 to 5
VOUT/Source
Connected to the source of the internal power MOSFET and to the output terminal of the
fuse
6
NC
7
I-Limit
A resistor between this pin and the Source pin sets the overload and short-circuit current
limit levels.
En/Fault
The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin
must be left floating, or it can be used to disable the output of the device by pulling it to
ground using an open drain or open collector device.
If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a
monitor circuit that the device is in thermal shutdown. It can be connected to another
device of this family to cause a simultaneous shutdown during thermal events.
9
dv/dt
The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The
internal capacitor allows a ramp-up time of around 1 ms. An external capacitor can be
added to this pin to increase the ramp time. If an additional capacitor is not required, this
pin should be left open.
10
GND
Ground pin
11
VCC
Exposed pad. Positive input voltage must be connected to VCC.
8
4/20
Not connected
Doc ID 019055 Rev 5
STEF05
Maximum ratings
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
VCC
Value
Positive power supply voltage (steady state)
-0.3 to 10
Positive power supply voltage (max 100 ms)
-0.3 to 15
Unit
V
VOUT/source
(max 100 ms)
-0.3 to Vcc+0.3
V
I-Limit
(max 100 ms)
-0.3 to 15
V
-0.3 to 7
V
-0.3 to 7
V
-40 to 125
°C
-65 to 150
°C
260
°C
En/Fault
dv/dt
Top
Operating junction temperature range
TSTG
Storage temperature range
TLEAD
Lead temperature (soldering) 10 sec
(1)
1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures
greater than the maximum ratings for extended periods of time.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Thermal data
Symbol
Parameter
Value
Unit
RthJA
Thermal resistance junction-ambient
52.7
°C/W
RthJC
Thermal resistance junction-case
17.4
°C/W
Test conditions
Value
Unit
HBM
2
kV
MM
150
V
CDM
500
V
Table 5.
ESD performance
Symbol
ESD
Parameter
ESD protection
Doc ID 019055 Rev 5
5/20
Electrical characteristics
4
STEF05
Electrical characteristics
VCC = 5 V, VEN = 3.3 V, CI = 10 µF, CO = 47 µF, TJ = 25 °C (unless otherwise specified).
Table 6.
Electrical characteristics for the STEF05
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Under/overvoltage protection
VClamp
Output clamping voltage
VCC = 10 V
5.95
6.65
7.35
V
VUVLO
Undervoltage lockout
Turn-on, voltage rising
3.2
3.6
4
V
VHyst
UVLO hysteresis
0.40
V
500
µs
Power MOSFET
tdly
Delay time
Enabling of chip to ID = 100 mA
with a 1 A resistive load
(1)
RDSon
On-resistance
VOFF
Off state output voltage
-40 °C < TJ < 125 °C
Continuous current
in2
40
pad, TA = 25 °C
60
mΩ
70
VCC = 10 V, VGS = 0, RL = infinite
0.5
ID
20
(2)
35
(2)
100
mV
3.6
A
Minimum copper, TA= 80 °C
1.7
Current limit
IShort
ILim
Short-circuit current limit
RLimit = 22 Ω
Overload current limit
RLimit = 22 Ω
1.9
2.9
3.9
2.9
A
A
dv/dt circuit
dv/dt
Enable to VOUT = 4.7 V, No
Cdv/dt
0.7
1.2
2.5
ms
Low level input voltage
Output disabled
0.35
0.58
0.81
V
Intermediate level input voltage
Thermal fault, output disabled
0.82
1.4
1.95
V
High level input voltage
Output enabled
1.96
2.64
3.3
V
3.4
4.3
5.4
V
-10
-30
µA
Output voltage ramp time
Enable/Fault
VIL
VI(INT)
VIH
VI(MAX)
High state maximum voltage
IIL
Low level input current (sink)
VEnable = 0 V
II
High level leakage current for
external switch
VEnable = 3.3 V
1
µA
Maximum fan-out for fault signal
Total numbers of chips that can
be connected to this pin for
simultaneous shutdown
3
Units
Total device
IBias
6/20
Device operational
0.5
Thermal shutdown
1
Bias current
2
mA
Doc ID 019055 Rev 5
STEF05
Table 6.
Electrical characteristics
Electrical characteristics for the STEF05 (continued)
Symbol
Vmin
Parameter
Test conditions
Min.
Typ.
Minimum operating voltage
Max.
Unit
3.1
V
Thermal latch
TSD
(2)
Shutdown temperature
165
°C
1. Pulse test: Pulse width = 300 µs, duty cycle = 2%
2. Guaranteed by design, but not tested in production
Doc ID 019055 Rev 5
7/20
Typical application
5
STEF05
Typical application
Figure 3.
Application circuit
AM09868v1
Figure 4.
Typical HDD application circuit
AM09869v1
5.1
Operating modes
5.1.1
Turn-on
When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling
the internal control circuitry.
After an initial delay time of typically 500 µs, the output voltage is supplied with a slope
defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the
total time from the Enable signal going high and the output voltage reaching the nominal
value is around 1 ms (refer to Figure 5, 15).
8/20
Doc ID 019055 Rev 5
STEF05
5.1.2
Typical application
Normal operating condition
The STEF05 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with
the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET
RDSOn.
5.1.3
Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically
6.65 V, if the input voltage exceeds this threshold.
5.1.4
Current limiting
When an overload event occurs, the current limiting circuit reduces the conductivity of the
power MOSFET, in order to clamp the output current at the value selected externally by
means of the limiting resistor RLimit (Figure 3).
5.1.5
Thermal shutdown
If the device temperature exceeds the thermal latch threshold, typically 165 °C, the thermal
shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault
pin of the device is automatically set at an intermediate voltage, in order to signal the
overtemperature event. In this condition the E-fuse can be reset either by cycling the supply
voltage or by pulling down the EN pin below the Vil threshold and then releasing it.
5.2
R limit calculation
As shown in Figure 3, the device uses an internal N-channel sense FET with a fixed ratio, to
monitor the output current and limit it at the level set by the user.
The RLimit value for achieving the requested current limitation can be estimated by using the
following theoretical formula, together with the graph in Figure 13: Current limit vs. RLimit.
Equation 1
65
R Limit = -------------I Short
5.3
Cdv/dt calculation
Connecting a capacitor between the Cdv/dt pin and GND allows the modification of the
output voltage ramp-up time.
Given the desired time interval Δt during which the output voltage goes from zero to its
maximum value, the capacitance to be added on the Cdv/dt pin can be calculated using the
following theoretical formula:
Equation 2
C dvdt = 50 × 10 – 9 Δt – 30 × 10 – 12
Where Cdv/dt is expressed in Farads and the time in seconds.
Doc ID 019055 Rev 5
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Typical application
STEF05
The addition of an external Cdv/dt also influences the initial delay time, defined as the time
between the Enable signal going high and the start of the VOUT slope (Figure 5).
The contribution of the external capacitor to this time interval can be estimated by using the
following theoretical formula:
Equation 3
delay time = 500 × 10 –6 + 13.6 × 10 6 × C dvdt
Figure 5.
Delay time and VOUT ramp-up time
AM09870v1
6
VOUT
5
V
4
delay
time
ramp-up
time
EN/Fault
3
2
1
0
Time
5.4
Enable/Fault pin
The Enable/Fault pin has the dual function of controlling the output of the device and, at the
same time, of providing information about the device status to the application.
When it is used as a standard Enable pin, it should be connected to an external open-drain
or open-collector device. In this case, when it is pulled at low logic level, it turns the output of
the E-Fuse off.
If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept
ON in normal operating conditions.
In case of thermal fault, the pin is pulled to an intermediate state (Figure 6). This signal can
be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can
be directly connected to the Enable/Fault pins of other STEFxx devices on the same
application in order to achieve a simultaneous enable/disable feature.
When a thermal fault occurs, the device can be reset either by cycling the supply voltage or
by pulling down the Enable pin below the Vil threshold and then releasing it.
10/20
Doc ID 019055 Rev 5
STEF05
Typical application
Figure 6.
Enable/Fault pin status
5
Normal operating condition
EN/Fault voltage [V]
4
3
2
Thermal fault condition
1
Off/Reset
0
time
Doc ID 019055 Rev 5
AM09871v1
11/20
Typical performance characteristics
6
STEF05
Typical performance characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted,
at TA = 25 °C.
Figure 7.
Clamping voltage vs. temperature
Figure 8.
AM09872v1
7.5
VCC = 10 V
7.3
4
7.1
3.9
6.9
3.8
6.7
3.7
Voltage (V)
Voltage (V)
UVLO voltage vs. temperature
6.5
6.3
AM09873v1
3.6
3.5
6.1
3.4
5.9
3.3
5.7
3.2
-40
5.5
-40
-25
0
25
55
85
125
-25
0
25
55
85
125
150
Temperature °C
150
Temperature °C
Figure 9.
UVLO hysteresis vs. temperature
Figure 10. Off-state voltage vs. temperature
VCC = 10 V, VGS = 0, RL = infinite
180
0.48
160
0.46
0.44
140
0.42
120
Voltage (mV)
Hysteresis (V)
AM09875v1
200
AM09874v1
0.5
0.4
0.38
0.36
100
80
60
0.34
40
0.32
20
0.3
-40
-25
0
25
55
85
125
0
150
-40
Temperature °C
-25
0
25
55
85
125
150
Temperature °C
Figure 11. Bias current (device operational)
Figure 12. ON resistance vs. temperature
AM09876v1
2
AM09877v1
80
VCC = 5 V, RLIMIT = 22 Ω, ILOAD = 1 A
1.8
70
1.6
1.4
RDSON (mΩ)
Current (mA)
60
1.2
1
0.8
50
40
0.6
0.4
30
0.2
20
0
-40
-25
0
25
55
85
125
150
-40
12/20
-25
0
25
55
Temperature °C
Temperature °C
Doc ID 019055 Rev 5
85
125
150
STEF05
Typical performance characteristics
Figure 13. Current limit vs. RLimit
Figure 14. Thermal latch delay vs. power
AM09879v1
AM09878v1
6.00
VCC = 5 V, T = 25 °C
100
ILIM
Thermal Action Time (ms)
Short Circuit Current Limit (A)
5.00
ISHORT
4.00
3.00
2.00
T = 25 °C
T = 55 °C
T = 85 °C
10
1.00
0.00
0
10
20
30
40
50
60
70
80
1
0
10
20
30
40
50
60
External Sense Resistor (Ω )
Power (W)
Figure 15. VOUT ramp-up vs. Enable
Figure 16. VOUT clamping
VCC = 15 V, CIN = 10 µF, COUT = 100 µF, RLIMIT = 22 Ω, No
Cdv/dt
VCC = 15 V, CIN = 10 µF, COUT = 100 µF, RLIMIT = 22 Ω, No
Cdv/dt
Figure 17. Line transient
Figure 18. Startup into output short-circuit
VCC = from 5 to 15 V RLIMIT = 22 Ω; IOUT = 500 mA, TRISE =
100 µs
VCC = 5 V, RLIMIT = 22 Ω, VOUT = Connected to GND
Doc ID 019055 Rev 5
13/20
Typical performance characteristics
STEF05
Figure 19. Thermal latch from 2 A load to
short-circuit
Figure 20. Startup into output short-circuit
(fast rise)
VCC = 5 V, RLIMIT = 22 Ω
VCC = 5 V, RLIMIT = 22 Ω, VOUT = Connected to GND
14/20
Doc ID 019055 Rev 5
STEF05
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 7.
DFN10L (3x3 mm.) mechanical data
mm.
Dim.
A
Min.
Typ.
Max.
0.80
0.90
1.00
0.02
0.05
0.65
0.80
A1
A2
0.55
A3
0.20
b
0.18
0.25
0.30
D
2.85
3.00
3.15
D2
2.20
E
2.85
E2
1.40
2.70
3.00
1.75
E3
0.230
E4
0.365
e
0.50
L
0.30
ddd
3.15
0.40
0.50
0.08
Doc ID 019055 Rev 5
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Package mechanical data
STEF05
Figure 21. DFN10L package outline
7426335_H
16/20
Doc ID 019055 Rev 5
STEF05
Package mechanical data
Tape and reel QFNxx/DFNxx (3x3 mm) mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
330
13.2
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
0.504
0.519
18.4
0.724
Ao
3.3
0.130
Bo
3.3
0.130
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
Doc ID 019055 Rev 5
Max.
17/20
Package mechanical data
STEF05
Figure 22. DFN10L footprint - recommended data (dimensions in mm.)
7426335_H
18/20
Doc ID 019055 Rev 5
STEF05
8
Revision history
Revision history
Table 8.
Document revision history
Date
Revision
Changes
15-Jul-2011
1
Initial release.
08-Aug-2011
2
Modified definition for Top in Table 3: Absolute maximum ratings.
15-Dec-2011
3
Removed Vdv/dt and Idv/dt rows from dv/dt circuit Table 6 on page 6.
06-Mar-2012
4
Updated: package mechanical data Table 7 on page 15, Figure 21
on page 16 and Figure 22 on page 18.
14-Jan-2013
5
Updated: package mechanical data Table 7 on page 15 and
Figure 21 on page 16.
Doc ID 019055 Rev 5
19/20
STEF05
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Doc ID 019055 Rev 5
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