TI TMS416100

TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
•
•
•
•
•
•
•
•
•
•
This data sheet is applicable to all
TMS416100/Ps symbolized with Revision “B”
and subsequent revisions as described on
page 24.
Organization . . . 16 777 216 × 1
Single 5-V Power Supply (±10% Tolerance)
Performance Ranges:
’416100- 60
’416100- 70
’416100- 80
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tRAC
tCAC
tAA
CYCLE
(MAX )
(MAX )
(MAX )
(MIN)
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
Enhanced Page Mode Operation for Faster
Memory Access
CAS-Before-RAS Refresh
Long Refresh Period
– 4096 Cycle Refresh in 64 ms
(TMS416100)
– 256 ms for Extended Refresh Version
(TMS416100P)
3-State Unlatched Output
Low Power Dissipation (TMS416100P Only)
– 500-µA CMOS Standby Current
– 500-µA Self-Refresh Current
– 500-µA Extended Refresh Battery Backup
Current
All Inputs, Outputs and Clocks Are TTL
Compatible
Operating Free-Air Temperature Range:
0°C to 70°C
DJ PACKAGE
( TOP VIEW )
VCC
D
NC
W
RAS
A11
1
26
2
25
3
24
4
23
5
22
6
21
A10
A0
A1
A2
A3
VCC
8
19
9
18
10
17
11
16
12
13
15
14
DGA PACKAGE
( TOP VIEW )
VSS
Q
NC
CAS
NC
A9
VCC
D
NC
W
RAS
A11
1
26
2
25
3
24
4
23
5
22
6
21
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
VCC
8
19
9
18
10
17
11
16
12
15
13
14
VSS
Q
NC
CAS
NC
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A0 – A11
CAS
D
Q
NC
RAS
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In
Data Out
No Internal Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
description
The TMS416100/P series are high-speed, 16 777 216-bit dynamic random-access memories, organized as
16 777 216 words of one bit each. The TMS416100P series feature self refresh and extended refresh. They
employ state-of-the-art EPIC (Enhanced Performance Implanted CMOS) technology for high performance,
reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All inputs, outputs, and clocks
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS416100/P are offered in 300-mil 24/26-lead plastic surface-mount SOJ packages (DJ suffix) and
24/26-lead plastic small-outline packages (DGA suffix). All packages are characterized for operation from 0°C
to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
logic symbol†
9
10
11
12
15
16
17
18
19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
21
8
A11
6
RAS
CAS
W
D
RAM 16 384K × 1
30D12/21D0
A
0
16 383K
31D23/21D11
5
23
4
2
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR DWN]
C31 [COL]
G34
&
33, 31D
A, 32D
33C32
34 EN
A∇
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DJ and DGA packages.
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
Q
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
functional block diagram
CAS
RAS
W
Timing and Control
10
A0
A1
Column Decode
ColumnAddress
Buffers
2
4
Sense Amplifiers
256K Array
4
256K Array
RowAddress
Buffers
Row Decode
A11
12
64
I/O
Buffers
1 of 4
Selection
Data
In
Reg.
Data
Out
Reg.
D
Q
2
256K Array
12
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that can be accessed is determined by tRASP , the maximum RAS-low time.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the addresses and enables the output. This feature allows the TMS416100/P to operate at a higher data
bandwidth than conventional page-mode parts because retrieval begins as soon as the column address is valid
rather than when CAS transitions low. This performance improvement is referred to as enhanced page mode.
Valid column address can be presented immediately after row-address hold time has been satisfied, usually well
in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low),
if tAA max (access time from column address) and tRAC have been satisfied. In the event that the column address
for the next cycle is valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of tCPA or tCAC.
address (A0 – A11)
Twenty-four address bits are required to decode 1 of 16 777 216 storage cell locations. Twelve row-address bits
are set up on inputs A0 through A11 and latched during a normal access and during RAS-only refresh as the
device requires 4096 refresh cycles. Twelve column-address bits are set up on inputs A0 – A11 and latched onto
the chip by CAS. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select,
activating the output buffer as well as latching the address bits into the column-address buffer.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
write enable ( W)
The read or write mode is selected through the write-enable ( W ) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting common
I/O operation.
data in (D)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low and the data is strobed in by W with setup and hold times referenced
to this signal.
data out (Q)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle,
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is low.
CAS going high returns it to the high-impedance state.
refresh
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed by holding CAS at VIL after a read operation and cycling RAS after
a specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid data is
maintained at the output throughout the hidden refresh cycle. An internal address provides the refresh address
during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and
holding it low after RAS falls (see parameter tCHR). For successive CAS-before-RAS refresh cycles, CAS
remains low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh
address is generated internally.
A low-power battery-backup refresh mode that requires less than 500 µA refresh current is available on the
TMS416100P. Data integrity is maintained using CAS-before-RAS refresh with a period of 62.5 µs while holding
RAS low for less than 1 µs. To minimize current consumption, all input levels need to be at CMOS levels
(VIL ≤ 0.2 V, VIH ≤ VCC – 0.2 V).
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
self refresh ( TMS416100P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy tCHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel
read or write on subsequent cycles. While in the test mode, any data sequence can be performed. The device
exits the test mode if a CAS-before-RAS (CBR) refresh cycle with W held high or a RAS-only refresh (ROR) cycle
is performed.
The device is configured as 1024K × 16 bits with a 16-bit parallel read-and-write data path in the test mode.
Column addresses A0, A1, A10, and A11 are not used. During a read cycle, all 16 bits of the internal data bus
are compared. If all bits are in the same data state, the output pin goes high. If one or more bits disagree, the
output pin goes low. Test time is reduced by a factor of 16, compared to normal memory mode.
Entry
Cycle
Test-Mode Cycle
Exit
Cycle
Normal
Mode
RAS
CAS
W
NOTE: The states of W, data input, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Input voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
VIH
Supply voltage
4.5
5
5.5
UNIT
V
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
–1
0.8
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
’416100 - 60
’416100P - 60
MIN
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = – 5 mA
IOL = 4.2 mA
2.4
II
Input current (leakage)†
VI = 0 V to 6.5 V
All other pins = 0 V to VCC
IO
Output current (leakage)†
VO = 0 V to VCC, CAS high
ICC1
Read- or write-cycle
current
(see Notes 3 and 5)
VCC = 5.5 V,
ICC2
Standby current
MAX
MIN
MAX
2.4
’416100 - 80
’416100P - 80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
± 10
± 10
± 10
µA
80
70
60
mA
2
2
2
mA
1
1
1
mA
’416100P
500
500
500
µA
Minimum cycle
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V ( TTL)
After 1 memory cycle,
RAS and CAS high,
high
VIH = VCC – 0.2 V (CMOS)
’416100 - 70
’416100P - 70
’416100
ICC3
Average refresh current
(RAS-only or CBR)
(see Notes 3 and 5)†
RAS cycling,
CAS high (RAS-only);
RAS low after CAS low (CBR)
80
70
60
mA
ICC4
Average page current
(see Notes 4 and 5)†
RAS low,
70
60
50
mA
ICC6
Self-refresh current
(’416100P only)
CAS and RAS < 0.2 V,
Measured after tRASS min
500
500
500
µA
ICC7
Standby current,
output enable
(see Note 5)†
RAS = VIH,
CAS = VIL,
Data out = enabled
5
5
5
mA
ICC10
Extended-refresh battery
backup (’416100P only)
tRC = 62.5 µs,
tRAS ≤ 1 µs,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
500
500
500
µA
CAS cycling
† Minimum cycle, VCC = 5.5 V
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
5. Measured with no load connected
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
7
pF
Co
Output capacitance
NOTE 6: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’416100 - 60
’416100P - 60
’416100 - 70
’416100P - 70
’416100 - 80
’416100P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
tCPA
tRAC
Access time from column precharge
35
40
45
ns
80
ns
tCLZ
tOH
CAS to output in low-impedance state
0
0
0
ns
Output disable time, start of CAS high
3
3
3
ns
Access time from RAS low
60
tOFF Output disable time after CAS high (see Note 7)
NOTE 7: tOFF is specified when the output is no longer driven.
8
POST OFFICE BOX 1443
0
15
• HOUSTON, TEXAS 77251–1443
70
0
18
0
20
ns
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’416100 - 60
’416100P - 60
’416100 - 70
’416100P - 70
’416100 - 80
’416100P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRC
tRWC
Cycle time, random read or write (see Note 8)
110
130
150
ns
Cycle time, read-write (see Note 8)
130
153
175
ns
tPC
tPRWC
Cycle time, page-mode read or write (see Notes 8 and 9)
40
45
50
ns
Cycle time, page-mode read-write (see Note 8)
60
68
75
ns
tRASP
tRAS
Pulse duration, page-mode, RAS low (see Note 10)
60
100 000
70
100 000
80 100 000
ns
Pulse duration, nonpage-mode, RAS low (see Note 10)
60
10 000
70
10 000
80
10 000
ns
tCAS
tCP
Pulse duration, CAS low (see Note 11)
15
10 000
18
10 000
20
10 000
ns
Pulse duration, CAS high
10
10
10
ns
tRP
tWP
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
tASC
tASR
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
tDS
tRCS
Setup time, data (see Note 12)
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
tCWL
tRWL
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
tWCS
Setup time, W low before CAS low (early-write operation only)
0
0
0
ns
tWRP
Setup time, W high before RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tWTS
tCAH
Setup time, W low before RAS low (test mode only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
tDH
tRAH
Hold time, data (see Note 12)
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
tRCH
tRRH
Hold time, W high after CAS high (see Note 13)
0
0
0
ns
0
0
0
ns
tWCH
Hold time, W low after CAS low (early-write operation only)
10
15
15
ns
tWRH
Hold time, W high after RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
Hold time, W low after RAS low (test mode only)
10
10
10
ns
Hold time, RAS high from CAS precharge
35
40
45
ns
tCHS
Hold time, CAS low after RAS high (self refresh)
– 50
NOTES: 8. All cycle times assume tT = 5 ns.
9. To assure tPC min, tASC should be greater than or equal to tCP .
10. In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12. Referenced to the later of CAS or W in write operations
13. Either tRRH or tRCH must be satisfied for a read cycle.
– 50
– 50
ns
tWTH
tRHCP
Hold time, W high after RAS high (see Note 13)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
9
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’416100 - 60
’416100P - 60
MIN
’416100 - 70
’416100P - 70
MAX
MIN
MAX
’416100 - 80
’416100P - 80
MIN
UNIT
MAX
tAWD
tCHR
Delay time, column address to W low (read-write operation only)
30
35
40
ns
Delay time, RAS low to CAS high (CAS-before-RAS refresh only)
10
10
10
ns
tCRP
tCSH
Delay time, CAS high to RAS low
5
5
5
ns
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
tCWD
Delay time, CAS low to RAS low (CAS-before-RAS refresh only)
5
5
5
ns
Delay time, CAS low to W low (read-write operation only)
15
18
20
tRAD
tRAL
Delay time, RAS low to column address (see Note 14)
15
Delay time, column address to RAS high
30
35
40
ns
tCAL
tRCD
Delay time, column address to CAS high
30
35
40
ns
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
tRSH
Delay time, RAS high to CAS low
0
0
0
ns
Delay time, CAS low to RAS high
15
18
20
ns
tRWD
tCPW
Delay time, RAS low to W low (read-write operation only)
60
70
80
ns
Delay time, W low after CAS precharge (read-write operation only)
35
40
45
ns
tRASS
tRPS
Pulse duration, self-refresh entry from RAS low
100
100
100
µs
Pulse duration, RAS precharge after self refresh
110
130
150
ns
tTAA
tTCPA
Access time from address (test mode)
35
40
45
ns
Access time from column precharge (test mode)
40
45
50
ns
tTRAC
Access time from RAS (test mode)
65
75
85
tREF
Refresh time interval
tT
Transition time
30
15
45
’416100
20
64
’416100P
52
15
20
64
256
3
35
256
30
3
30
3
ns
40
60
ns
ms
256
ms
30
ns
PARAMETER MEASUREMENT INFORMATION
VCC = 5 V
RL = 218 Ω
Output Under Test
R1 = 828 Ω
Output Under Test
CL = 100 pF
CL = 100 pF
(a) LOAD CIRCUIT
10
R2 = 295 Ω
(b) ALTERNATE LOAD CIRCUIT
Figure 2. Load Circuits
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ns
64
NOTE 14: The maximum value is specified only to assure access time.
1.31 V
ns
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
CAS
tCAS
tASR
tCP
tRAD
tASC
tRAH
tCAL
tRAL
A0 – A11
Row
Don’t Care
Column
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tOFF
tAA
Q
Hi-Z
(see Note A)
Valid Data Out
tCLZ
tRAC
NOTE A: Output can go from 3-state to an invalid data state prior to the specified access time.
Figure 3. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCAS
tCRP
tCSH
tASR
CAS
tCP
tASC
tCAL
tRAL
tRAH
A0 – A11
tCAH
Row
Column
Don’t Care
tCWL
tRAD
tRWL
tWCH
tWCS
W
Don’t Care
Don’t Care
tWP
tDH
tDS
D
Valid Data
Q
Don’t Care
Hi-Z
Figure 4. Early-Write-Cycle Timing
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
CAS
tCP
tCAL
tRAL
tRAH
A0 – A11
tCAH
Row
Column
Don’t Care
tCWL
tRAD
tRWL
W
Don’t Care
Don’t Care
tWP
tDS
D
tDH
Don’t Care
Don’t Care
Valid Data
tOFF
tCLZ
tOH
Not Valid
Q
Figure 5. Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tRCD
tCRP
tCAS
tASR
CAS
tRAH
tRAD
A0 – A11
tCP
tCAH
tT
tASC
Row
Column
Don’t Care
tCWL
tRCS
tRWL
tAWD
tWP
Don’t Care
W
tCWD
tRWD
tDS
D
Don’t Care
Valid In
tCLZ
(see Note A)
Q
Hi-Z
Don’t Care
tDH
Valid Out
tCAC
tAA
tRAC
NOTE A: Output can go from 3-state to an invalid data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
tOFF
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tRCD
tPC
tCSH
tRAH
tCAL
tCAH
tASR
tASC
Row
tRAL
Column
Column
tAA†
tRCS
W
tCRP
tCAS
CAS
A0 – A11
tRSH
tCP
Don’t Care
tRRH
tRCH
tCAC†
tRAD
tCPA†
tCAC
tAA
tOFF
tRAC
tCLZ
Q
(see Note A)
Valid
Out
Valid
Out
† Access time is tCPA, tCAC, or tAA dependent.
NOTE A: Output can go from 3-state to an invalid data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRHCP
tCSH
tRCD
tPC
tCAS
tASC
CAS
tRAH
tCP
tRAL
tCAH
tASR
A0 – A11
Row
tCAL
Column
tCWL
tCWL
tRWL
tWP
Don’t Care
Don’t Care
(see Note A)
Don’t Care
(see Note A)
tDH
tDS
tDH
(see Note A)
tDS
(see Note A)
D
Don’t Care
Column
tRAD
W
tCRP
tRSH
Valid
In
Valid Data In
Q
Don’t Care
Hi-Z
NOTES: A. Referenced to CAS or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tRSH
tPRWC
tRCD
tCRP
tCP
tCAS
CAS
tRAH
tASC
tRAD
tASR
A0 – A11
tCAH
Row
Column
Column
tCPW
tCWD
tRCS
Don’t Care
tCWL
tAWD
tWP
tRWD
tRWL
W
tDS
tDH
D
Don’t Care
Valid
Don’t Care
tCAC
Valid
Don’t Care
tCPA
tAA
tOFF
tRAC
tCLZ
(see Note A)
Valid
Out
Q
(see Note A)
Valid Out
NOTES: A. Output can go from 3-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
tRPC
Don’t Care
CAS
tRAH
tASR
Don’t Care
A0 – A11
Row
W
Don’t Care
D
Don’t Care
Q
Hi-Z
Don’t Care
Figure 10. RAS-Only-Refresh-Cycle Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
tWRH
W
A0 – A11
Don’t Care
D
Don’t Care
Q
Hi-Z
Figure 11. Automatic (CAS-Before-RAS) Refresh-Cycle Timing
18
tCRP
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Row
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
A0 – A11
Col
Don’t Care
tRRH
tRCS
tWRH
tWRH
tWRH
tWRP
tWRP
tWRP
W
tCAC
tAA
D
Don’t Care
tRAC
tOFF
tCLZ
Valid Data
Q
Figure 12. Hidden-Refresh-Cycle (Read) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
tRAS
Refresh Cycle
tRP
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
A0 – A11
Row
Don’t Care
Col
tWRH
tRRH
tWCS
tWRP
tWP
W
tWCH
tDS
tDH
D
Q
Don’t Care
Hi-Z
Figure 13. Hidden-Refresh-Cycle (Write) Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRASS
RAS
tRPC
tRPS
tCSR
tCHS
CAS
tCP
A0 – A11
Don’t Care
W
Don’t Care
OE
Don’t Care
tOFF
DQ1– DQ4
Hi-Z
Figure 14. Self-Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWTH
tWTS
Don’t Care
W
A0 – A11
Don’t Care
D
Don’t Care
Hi-Z
Q
Figure 15. Test-Mode-Entry-Cycle Timing
tRC
tRP
tRAS
RAS
tRPC
tCSR
tCHR
tT
CAS
tWRP
W
Don’t Care
Don’t Care
tWRH
A0 – A11
Don’t Care
tOFF
Q
Hi-Z
Don’t Care
Figure 16. Test-Mode-Exit-Cycle (CAS-Before-RAS Refresh Cycle) Timing
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
MECHANICAL DATA
DJ– 24 / 26 LEAD PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
R– PDSO– J24 / 26
0.680 (17,27)
0.670 (17,02)
26
14
0.305 (7,75)
0.295 (7,49)
1
0.340 (8,64)
0.330 (8,38)
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) NOM
Seating Plane
0.004 (0,10)
0.020 (0,51)
0.016 (0,41)
0.148 (3,76)
0.128 (3,25)
0.275 (6,99)
0.260 (6,60)
0.050 (1,27) TYP
NOTES: A. All linear dimensions are in inches (millimeters).
B. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
MECHANICAL DATA
DGA– 24 / 26 LEAD PLASTIC THIN SMALL-OUTLINE PACKAGE
R– PDSO– G24/ 26
17, 25 (0.679) ‡
17, 04 (0.671)
26 25 24 23 22 21
19 18 17 16 15 14
7, 72 (0.304) †
7, 52 (0.296)
9, 42 (0.371)
9, 02 (0.355)
Index
1
2
3
4
5
6
8
9
10 11 12 13
1,20 (0.047) MAX
0, 21 (0.008)
0, 12 (0.005)
0, 15 (0.006)
0, 05 (0.002)
1,27 (0.050) TYP
0° to 5°
0, 60 (0.024)
0, 40 (0.016)
8,20
(0.323)
TYP
0, 51 (0.020)
0, 31 (0.012)
† Plastic body width does not include mold protrusion. Maximum mold protrusion is 0,25 ( 0.010) per side from the edge of the package bottom.
‡ Plastic body length does not include mold protrusion. Maximum mold protrusion is 0,15 (0.006) per side from the edge of the package bottom.
NOTE A: All linear dimensions are in millimeters and parenthetically in inches.
device symbolization
P
TI
-SS
TMS416100 DJ
W
B P
Speed (- 60, -70, -80)
Low-Power/Self-Refresh
Code
Package Code
XXX LLL
Lot Traceability Code
Date Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
Printed in U. S. A.
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SMKS611
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated