V ishay I nte r technolog y, I nc . AND TEC I INNOVAT O L OGY Standard Layout Guidelines N HN THIN FILM LED SUBSTRATES O 19 62-2012 Resistors - Standard Layout Guidelines Vishay Electro-Films DESCRIPTION Thin film processing techniques are used for surface-mount LED applications with high current and heat challenges. They feature robust, solid metal-filled vias that provide excellent thermal and electrical interconnects. The substrate acts as the base of the package, the LED is surface-mounted, and a lid or encapsulate is added to form a complete assembly. Key benefits • • • • Substrate is base of package, AL 2O3 or AIN Solid metal-filled vias (Au or Cu) provide thermal and electrical interconnects Thick metals (Au or Cu) can be incorporated to handle high current and heat loads Second-level Au bumps are available to support ultrasonic LED die attach APPLICATIONS • • • • • High-brightness, high-power and/or high-current-draw LED requirements Single-cell or multi-cell LEDs Automotive lighting Consumer backlighting Outdoor lighting Resources • Datasheet: Standard Layout Guidelines - http://www.vishay.com/doc?61081 • For technical questions contact [email protected] One of the World’s Largest Manufacturers of Discrete Semiconductors and Passive Components PRODUCT SHEET 1/2 VMN-PT0158-1202 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 V ishay I nte r technolog y, I nc . I INNOVAT 19 Vishay Electro-Films Standard Layout Guidelines 62-2012 HIGH DENSITY INTERCONNECT Standard Layout Guidelines Vishay Substrate Electro-Films DESIGN CAPABILITIES The wide array of capabilities allows users to find solutions for applications servicing many markets such as: Thin Film High Density Interconnect design guide is directed at engineers looking to design the following: • Simple resistor networks • Integrated resistor-capacitor networks • Multilayer substrate that involve up to 5 layers • Custom thin film substrate on alumina (AI2O3) Aluminum nitride (AlN) or beryllium oxide (BeO) • Substrates with special shapes, vias, and patterns • Substrates for microwave applications • Military • Automotive • Instrumentation - microwave • Telecommunications - CATV, fiber optic and wireless • Aerospace • Medical DIMENSIONS in inches (millimeters) MAXIMUM SUBSTRATE SIZE 4.1" [104] x 4.1" [104] CONDUCTORS & RESISTORS - VALUES & TOLERANCES LAYER TO LAYER REGISTRATION ± 0.0005" [0.01] VALUE TO ± 5 % WIDTH: 0.002" [0.05] MIN. VALUE TO ± 0.1 % WIDTH 0.002" [0.05] MIN. LENGTH: 0.002" [0.05] MIN. LENGTH: 0.005" [0.13] MIN. METAL PULLBACK 0.003" [0.08] PREFERRED 0.005" [0.13] MIN. HALF VIA. EDGE WRAP 0.003" [0.08] MIN. LATERIAL RESISTOR SPACING (FOR LASER ENTRY) AIR BRIDGE LINE SPACING 0.0005" [0.013] MIN. TOL. ± 0.0001" [0.003] MIN. DIA. 0.010" [0.254] OR SUBSTRATE THICKNESS SLOTTED EDGEWRAP 0.007" [0.18] ± 0.005" [0.13] INTRUSION 0.006" [0.15] TYP RADIUS 0.020" [0.51] TYP WIDTH 0.001" [0.025] SQ. MIN CONTACT AIR BRIDGES OR SUPPORTED BACK PATTERN HOLES AND MACHINED FEATURES FRONT TO BACK PATTERN REGISTRATION ± 0.002" [0.05] THIN FILM CAPACITORS VALUE: L x W x 0.15 pF/SQ. MIL (Si3N4) VALUE: L x W x 0.055 pF/SQ. MIL (POLY) CONDUCTOR OVERLAP AREA 0.005" [0.13] FOR PLATED THRU HOLES 0.0025" [0.064] FOR FILLED VIAS 0.004" [0.01] FOR VENTED FILLED VIAS CIRCUIT FEATURE LOCATION TOLERANCE ± 0.002" [0.05] RELATIVE TO CIRCUIT DATUM DIELECTRIC AREA RADIUS ± 0.006" [0.15] MIN. HOLE LOCATION ± 0.002" [0.5] NON-CUMMULATIVE CUTOUT TOLERANCE TO ± 0.003" [0.08] PRODUCT SHEET DIELECTRIC VIAS 0.002" [0.08] DIA. AIR BRIDGE ANNULUS SPACING ± 0.015" [0.38] MIN. 0.020" [0.51] MIN. Document Number: 61081 Revision: 09-Mar-07 MULTILAYER CONDUCTORS (UP TO 5 LAYERS) VIA PAD 0.005" [0.13] TYP. LINE WIDTH 0.0005" [0.013] MIN. TOL. ± 0.0001" [0.003] REGISTRATION VIA TO CIRCUIT ± 0.002" [0.05] Revision 09-Mar-07 Resistors - Standard Layout Guidelines AND TEC O L OGY Standard Layout Guidelines N HN THIN FILM LED SUBSTRATES O GREATER OF 0.020" [0.51] OR HOLE DIAMETER HOLE DIAMETER DIAMOND SAWN TO ± 0.001" [0.025] ± 0.003" [0.08] STD. CUTOUT LASER CUT FEATURES ± 0.003" [0.08] 0.8 x SUBSTRATE THICKNESS FOR PLATED THRU HOLES 0.007" FOR FILLED VIAS AS MEASURED FROM THE LASER EXIT SIDE SURFACE DIAMETER TO ± 0.001" [0.025] For technical questions, contact: [email protected] 2/2 www.vishay.com 11 VMN-PT0158-1202 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000