Download Datasheet

STAP16DPPS05
Low voltage 16-bit constant current LED sink driver with output error
detection and auto power-saving for automotive applications
Datasheet - production data
Description
The STAP16DPPS05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a 16bit D-type storage register. In the output stage,
sixteen regulated current sources are designed to
provide 3 to 40 mA of constant current to drive the
LEDs.
+76623
H[SRVHGSDG
Features
• AECQ100 qualification
• Low voltage power supply down to 3 V
• 16 constant current output channels
• Adjustable output current through external
resistor
• Short and open output error detection
• Serial data IN/parallel data OUT
• 3.3 V micro driver-able
• Auto power-saving
• Output current: 3 - 40 mA
• Auto power-saving
• Max. clock frequency: 30 MHz
• 20 V current generator rated voltage
• Power supply voltage: from 3 V to 5.5 V
• Thermal shutdown for overtemperature
protection
• ESD protection 2.0 KV HBM
Applications
• Dashboard and infotainment backlighting
•
Exterior/interior lighting
•
DTRLs
The STAP16DPPS05 features the open and short
LED detection on the outputs. The detection
circuit checks 3 different conditions which may
occur on the output line: short to GND, short to VO
or open line. The data detection results are
loaded in the shift register and shifted out via the
serial line output. The detection functionality is
implemented without increasing the pin number
through a secondary function of the output enable
and latch pin (DM1 and DM2 respectively). A
dedicated logic sequence allows the device to
enter or leave detection mode. Through an
external resistor, users can adjust the output
current of the STP16DPPS05 thus controlling the
light intensity of the LEDs. In addition, the user
can adjust the intensity of the brightness of the
LED’s from 0% to 100% through the OE/DM2 pin.
The auto power shutdown and auto power-ON
feature allows the device to save power with no
external intervention. The STAP16DPPS05
guarantees a 20 V output driving capability,
allowing users to connect more LEDs in series.
The high clock frequency, 30 MHz also satisfies
the system requirement of high volume data
transmission. The 3.3 V of voltage supply is very
useful for applications interfacing any
microcontroller from 3.3 V micro. Compared with
a standard TSSOP package, the TSSOP exposed
pad increases the capability of heat dissipation by
a factor of 2.5.
Table 1. Device summary
Order code
Package
Packing
STAP16DPPS05XTTR
HTSSOP24 (exposed pad)
2500 parts per reel
November 2015
This is information on a product in full production.
DocID024306 Rev 6
1/33
www.st.com
Contents
STAP16DPPS05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
2
Pin connections and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Error detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
9
2/33
7.1
Phase one: entering error detection mode . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2
Phase two: error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3
Phase three: resuming normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.5
Auto power-saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1
TSSOP24 exposed pad package information . . . . . . . . . . . . . . . . . . . . . 28
8.2
TSSOP24 exposed pad packing information . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID024306 Rev 6
STAP16DPPS05
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical current accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Enable IO: shutdown truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output current vs. REXT resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ISET vs. dropout voltage (Vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Entering error detection mode - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Resuming normal mode - timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Detection conditions (VDD = 3.3 to 5 V, temperature range -40 to 125 °C) . . . . . . . . . . . . 23
TSSOP24 exposed pad mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP24 exposed pad tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID024306 Rev 6
3/33
33
List of figures
STAP16DPPS05
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
4/33
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OE/DM2 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LE/DM1 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLK, SDI terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SDO terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock, serial-in, serial-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock, serial-in, latch, enable, outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output current vs. REXT resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ISET vs. dropout voltage (Vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output current vs. ± ΔIOL(%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Idd ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power dissipation vs. package temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-ON output current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-OFF output current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Entering error detection mode - timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Detection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timing example for open and/or short-circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Error detection sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Auto power-saving feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Auto power-saving feature: first output TON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TSSOP24 exposed pad package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TSSOP24 exposed pad tape and reel outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID024306 Rev 6
STAP16DPPS05
1
Summary description
Summary description
Table 2. Typical current accuracy
Current accuracy
Output voltage
≥ 1.3 V
1.1
Between bits
Between ICs
± 1%
± 2%
Output current
VDD
Temperature
5 to 40 mA
3.3 V to 5 V
25 °C
Pin connections and description
Figure 1. Pin connections
1
24
VDD
SDI
2
23
R-EXT
CLK
3
22
SDO
LE/DM1
4
21
OE/DM2
OUT0
5
20
OUT15
OUT1
6
19
OUT14
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
GND
Note:
The exposed pad is electrically connected to a metal layer electrically isolated or connected
to ground.
DocID024306 Rev 6
5/33
33
Summary description
STAP16DPPS05
Table 3. Pin description
6/33
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE/DM1
Latch input terminal - detect mode 1 (see operation principle)
5-20
OUT-15
Output terminal
21
OE/DM2
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
22
SDO
23
R-EXT
24
VDD
Serial data out terminal
Input terminal for an external resistor for constant current
programming
Supply voltage terminal
DocID024306 Rev 6
STAP16DPPS05
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
Vdd
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
50
mA
VI
Input voltage
-0.4 to Vdd
V
IGND
GND terminal current
800
mA
fCLK
Clock frequency
50
MHz
TOPR
Operating temperature range
-40 to +150
°C
TSTG
Storage temperature range
-55 to +150
°C
Thermal data
Table 5. Thermal data
Symbol
Rthj-amb
Parameter
Thermal resistance
junction-ambient (1)
TSSOP24(2) exposed pad
Value
Unit
37.5
°C/W
1. According to JEDEC standard 51-7B.
2. The exposed pad should be soldered to the PCB in order to derive the thermal benefits.
DocID024306 Rev 6
7/33
33
Electrical ratings
2.3
STAP16DPPS05
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
3.0
-
5.5
V
-
20
V
-
40
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SeriaL-OUT
-
+1
mA
IOL
Output current
Serial-OUT
-
-1
mA
VIH
Input voltage
0.7 VDD
-
VDD
V
VIL
Input voltage
-0.3
-
0.3 VDD
V
3
twLAT
LE/DM1 pulse width
20
-
ns
twCLK
CLK pulse width
10
-
ns
twEN
OE/DM2 pulse width
100
-
ns
8
-
ns
tHOLD(D) Hold time for DATA
5
-
ns
tSETUP(L) Setup time for LATCH
8
-
ns
VDD = 3.0 V to 5.0 V
tSETUP(D) Setup time for DATA
fCLK
Clock frequency
Cascade operation (1)
-
30
MHz
1. If the device is connected in cascade, it may not be possible to achieve the maximum data transfer. Please
consider the timings carefully.
8/33
DocID024306 Rev 6
STAP16DPPS05
3
Electrical characteristics
Electrical characteristics
VDD = 5 V, Tj = -40 °C to 125 °C, unless otherwise specified.
Table 7. Electrical characteristics
Symbol
Parameter
VIH
Input voltage high level
0.7·VDD
VDD
VIL
Input voltage
low level
GND
0.3·VDD
VOL
Test conditions
Min.
Typ.
Max.
V
0.03
0.4
Vo =19 V, OUTn = OFF
0.5
2
VDD = 3.3 V, VO = 0.3 V,
Rext = 3.9 kΩ
±1
±5
VDD = 3.3 V, VO = 0.6 V,
Rext = 980 Ω
±0.5
±4
∆IOL3
VDD = 3.3 V, VO = 1.3 V,
Rext = 490 Ω
±0.5
±4
∆IOL2
VDD = 3.3 V, VO = 0.6 V,
Rext = 980 Ω
±5
VDD = 3.3 V, VO = 1.3 V,
Rext = 490 Ω
±6
VOH
IOH
Serial data output voltage
(SDO)
Output leakage current
∆IOL1
∆IOL2
∆IOL3
Current accuracy
channel-to-channel (1) (2)
Current accuracy deviceto-device(1)
IOL = + 1 mA
IOH = - 1 mA
VDD-0.4
RIN(up)
Pull-up resistor for OE pin
150
300
600
RIN(down)
Pull-down resistor for LE
pin
100
200
400
Rext = 980 Ω, OE = low,
OUT0 to OUT7 = OFF
200
300
Rext = 980 Ω, OE = high,
OUT0 to OUT7 = ON
5
7.5
IDD(OFF2)
Rext = 490 Ω, OE = high,
OUT0 to OUT15 = ON
8
11
IDD(ON1)
Rext = 980 Ω, OE = low,
OUT0 to OUT15 = ON
6
7.5
Rext = 490 Ω, OE = low,
OUT0 to OUT15 = ON
8
11
IDD(AutoOff)
IDD(OFF1)
Supply current (OFF)
Supply current (ON)
IDD(ON2)
Tsd
Unit
µA
%
kΩ
Thermal shutdown(3)
µA
mA
170
°C
1. Test performed with all outputs turned on, but only one output loaded at a time.
2. ΔIOL+ = ((IOLmax - IOLmean)/ IOLmean)*100, ΔIOL - = ((IOLmin - IOLmean)/ IOLmean)*100, where IOLmean =
(IOLout1+IOLout2+…+IOLout16) / 16.
3. Not tested, guaranteed by design.
DocID024306 Rev 6
9/33
33
Electrical characteristics
STAP16DPPS05
VDD = 5 V, Tj = 25 °C, unless otherwise specified.
Table 8. Switching characteristics(1)(2)
Symbol
fclk
Parameter
Clock frequency
Test conditions
Min.
Typ.
Cascade operation
Max.
Unit
30
MHz
CLK-OUTn, LE/DM1 = H,
OE/DM2 = L
VDD = 3.3 V
55
90
tPLH1
VDD = 5 V
30
50
LE/DM1-OUTn,
OE/DM2 = L
VDD = 3.3 V
48
80
tPLH2
VDD = 5 V
30
45
OE/DM2-OUTn, LE\DM1 =
H
VDD = 3.3 V
70
120
tPLH3
VDD = 5 V
45
65
35
CLK-SDO
VDD = 3.3 V
21
tPLH
VDD = 5 V
15
25
CLK-OUTn,
LE/DM1 = H,
OE/DM2 = L
VDD = 3.3 V
28
35
tPHL1
VDD = 5 V
22
40
LE/DM1-OUTn,
OE/DM2 = L
VDD = 3.3 V
13
35
tPHL2
VDD = 5 V
12
18
OE/DM2-OUTn,
LE/DM1 = H
VDD = 3.3 V
24
35
tPHL3
VDD = 5 V
21
30
40
CLK-SDO
VDD = 3.3 V
24
tPHL
VDD = 5 V
17
25
Output rise time
10~90% of voltage
waveform
VDD = 3.3 V
30
55
tON
VDD = 5 V
10
20
Output fall time
90~10% of voltage
waveform
VDD = 3.3 V
4
10
tOFF
VDD = 5 V
3
8
tr
tf
VIH = VDD
VIL = GND CL = 10 pF
IO = 20 mA VL = 3.0 V
RL = 60 Ω
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK rise time (3)
CLK fall time
ns
5
µs
(3)
5
1. All table limits are guaranteed by design.
2. Not tested in production.
3. If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer
between two cascaded devices.
10/33
DocID024306 Rev 6
STAP16DPPS05
4
Equivalent circuit and outputs
Equivalent circuit and outputs
Figure 2. OE/DM2 terminal
Figure 3. LE/DM1 terminal
Figure 4. CLK, SDI terminal
DocID024306 Rev 6
11/33
33
Equivalent circuit and outputs
STAP16DPPS05
Figure 5. SDO terminal
Figure 6. Block diagram
%.
& %.
12/33
DocID024306 Rev 6
STAP16DPPS05
5
Timing diagrams
Timing diagrams
Table 9. Truth table
CLOCK
Note:
LE/DM1
OE/DM2
SERIAL-IN
OUT0............. OUT7................ OUT15
SDO
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
Dn - 15
L
L
Dn + 1
No change
Dn - 14
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
X
H
Dn + 3
OFF
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7. Timing diagram
Note:
Latch and output enable terminals are level-sensitive and are not synchronized with rising or
falling edge of LE/DM1 signal. When LE/DM1 terminal is low level, the latch circuit holds
previous set of data. When LE/DM1 terminal is high level, the latch circuit refreshes new set
of data from SDI chain. When OE/DM2 terminal is at low level, the output terminals Out 0 to
Out 15 respond to data in the latch circuits, either ‘1’ ON or ‘0’ OFF. When OE/DM2 terminal
is at high level, all output terminals are switched OFF.
DocID024306 Rev 6
13/33
33
Timing diagrams
STAP16DPPS05
Table 10. Enable IO: shutdown truth table
CLOCK
LE/DM1
SDI0........... SDI7............ SDI15
SH
Auto powerup
OUTn
H
All = L
Active
Not active (1)
OFF
L
No change
No change
No change
No change
H
One or more = H
Not active
Active
X(2)
1. At power-up, the device starts in shutdown mode.
2. Undefined.
Figure 8. Clock, serial-in, serial-out
14/33
DocID024306 Rev 6
STAP16DPPS05
Timing diagrams
Figure 9. Clock, serial-in, latch, enable, outputs
LE/DM1
OE/DM2
OUTn
Figure 10. Outputs
OUTn
DocID024306 Rev 6
15/33
33
Typical characteristics
6
STAP16DPPS05
Typical characteristics
Figure 11. Output current vs. REXT resistor
25000
R external (Ohm)
20000
15000
10000
5000
0
0
10
20
30
40
50
60
Current (mA)
Table 11. Output current vs. REXT resistor
16/33
REXT (Ω)
Output current (mA)
23700
1
11730
2
6930
3
4090
5
2025
10
1000
20
667
30
497
40
331
60
DocID024306 Rev 6
70
STAP16DPPS05
Typical characteristics
Conditions:
temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50
mA; 60 mA.
Figure 12. ISET vs. dropout voltage (Vdrop)
0LQ'URS9ROWDJHP9
–
$YJ#9
$YJ#9
&XUUHQWP$
$0Y
Table 12. ISET vs. dropout voltage (Vdrop)
Iout (mA)
Avg (mV) @ 3.3 V
Avg (mV)@ 5.0 V
3
36
37
5
71
72
10
163
163
20
346
347
40
724
726
60
1080
1110
DocID024306 Rev 6
17/33
33
Typical characteristics
STAP16DPPS05
TA = 25 °C, VDD = 3.3 V; 5 V
Figure 13. Output current vs. ± ΔIOL(%)
".W
Figure 14. Idd ON/OFF
,GGP$
$9*,''21#9
$9*,''21#9
$9*,''2))#9
$9*,''2))#9
,VHWP$
$0Y
18/33
DocID024306 Rev 6
STAP16DPPS05
Typical characteristics
Figure 15. Power dissipation vs. package temperature
Note:
The exposed pad should be soldered to the PCB to obtain the thermal benefits.
Figure 16. Turn-ON output current
characteristics(1)
Figure 17. Turn-OFF output current
characteristics(2)
$0Y
AM13667v1
1. The reference level for the TON characteristics is 50% of OE/DM2 signal and 90% of output current
2. The reference level for the TOFF characteristics is 50% of OE/DM2 signal and 10% of output current
Electrical conditions:
–
VDD = 3.3 V, Vin = VDD, Vled = 3.0 V, RL = 60 Ω, CL = 10 pF.
–
Ch1 (yellow) = OE/DM2, Ch2 (blue) = SDI, Ch3 (purple) = VOUT, Ch4 (green) =
OUT.
DocID024306 Rev 6
19/33
33
Error detection mode functionality
STAP16DPPS05
7
Error detection mode functionality
7.1
Phase one: entering error detection mode
From the “normal mode” condition the device can switch to “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and diagram:
Table 13. Entering error detection mode - truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 18. Entering error detection mode - timing diagram
CLK
OE/DM2
LE/DM1
AM13668v1
After these five CLK cycles, the device goes into the “error detection mode” and at the 6th
rising edge of the CLK, the SDI data are ready for sampling.
20/33
DocID024306 Rev 6
STAP16DPPS05
7.2
Error detection mode functionality
Phase two: error detection
The 16 data bits must be set to “1” in order to set ON all the outputs during detection. The
data are latched by LE/DM1 and after that the outputs are ready for the detection process.
When the microcontroller switches the OE/DM2 to LOW, the device drives the LEDs in order
to analyze if an OPEN or SHORT condition has occurred.
Figure 19. Detection diagram
The LED status is detected in 1 microsecond (minimum) and after this time the
microcontroller sets OE/DM2 in HIGH state and the output data detection results go to the
microprocessor via SDO.
Detection mode and normal mode both use the same data format. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status, the device must go back in normal mode and re-enter
error detection mode.
DocID024306 Rev 6
21/33
33
Error detection mode functionality
STAP16DPPS05
D.U.T.
D.U.T.
D.U.T.
D.U.T.
D.U.T.
Figure 20. Timing example for open and/or short-circuit detection
22/33
DocID024306 Rev 6
STAP16DPPS05
7.3
Error detection mode functionality
Phase three: resuming normal mode
The sequence for re-entering normal mode is shown in the following table:
Table 14. Resuming normal mode - timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
Note:
For proper device operation, the “entering error detection” sequence must be followed by a
“resume mode” sequence, it is not possible to insert consecutive equal sequences.
7.4
Error detection conditions
Table 15. Detection conditions (VDD = 3.3 to 5 V, temperature range -40 to 125 °C)
Configuration
Note:
Detect mode
Detection results
SW-1 or
SW-3b
Open line or output
==> IODEC ≤ 0.5 x IO
short to GND detected
No error
detected
==> IODEC ≥ 0.5 x IO
SW-2 or
SW-3a
Short on LED or short
to V-LED detected
No error
detected
==> VO ≤ 2.3 V
==> VO ≥ 2.6 V
Where: IO = the output current programmed by the REXT, IODEC = the detected output
current in detection mode.
Figure 21. Detection circuit
STAP16DPPS05
16
AM13669v1
DocID024306 Rev 6
23/33
33
Error detection mode functionality
STAP16DPPS05
Figure 22. Error detection sequence
This LE/DM1 pulse latch
the data to the outputs
Feeding 16 bit of CLK signal af ter
entering the EDM, the SDI signal, set to
1, is loaded in the shif t register
OE/DM2 and LE/DM1
sequence signals to
start the error
detection sequence
Ignore
This OE/DM2 pulse put the
device in Normal Mode
Condition af ter EDM test
On the rising edge of f irst CLK pulse af ter the detection, the SDO
provides the Output status f eedback with the sequence Out 15;
Out 14…Out 0.
In this case all the outputs are in f ault condition (Open or Short)
Turn ON the output with the OE/DM2 pin and wait 1 µs to
have the correct output status acquisition. During this time
a minimum of three CLK pulses are required (2 at the
beginning and 1 at the end) to rewrite the shif t register.
AM13670v1
24/33
DocID024306 Rev 6
STAP16DPPS05
7.5
Error detection mode functionality
Auto power-saving
The auto power-saving feature minimizes the quiescent current if no active data is detected
on the latches and auto powers-up the device as the first active data is latched.
Figure 23. Auto power-saving feature
AM13671v1
Conditions:
–
Temp. = 25 °C, VDD = 3.3 V, Vin = VDD, VLed = 3.0 V, Iset = 20 mA.
–
Ch1 (yellow) = CLK, Ch2 (blue) = SDI, Ch3 (purple) = LE/DM1, Ch4 (green) = IDD.
Idd consumption:
–
Idd (normal operation) = 2.93 mA.
–
Idd (shutdown condition) = 170 µA.
DocID024306 Rev 6
25/33
33
Error detection mode functionality
STAP16DPPS05
Figure 24. Auto power-saving feature: first output TON
AM13672v1
Conditions:
Note:
26/33
–
Temp. = 25 °C, VDD = 3.3 V, Vin = VDD, VLed = 3.0 V, Iset = 20 mA
–
Ch1 (yellow) = CLK, Ch2 (blue) = SDI, Ch3 (purple) = LE/DM1, Ch4 (green) = IDD
When the device goes from auto power-saving to normal operating condition, the first output
switching ON shows the TON condition as seen in the plot above.
DocID024306 Rev 6
STAP16DPPS05
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID024306 Rev 6
27/33
33
Package information
8.1
STAP16DPPS05
TSSOP24 exposed pad package information
Figure 25. TSSOP24 exposed pad package outline
28/33
DocID024306 Rev 6
STAP16DPPS05
Package information
Table 16. TSSOP24 exposed pad mechanical data
mm
Symbol
Min.
Typ.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
7.70
7.80
7.90
D1
4.80
5.00
5.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
3.00
3.20
3.40
e
L
1.05
0.65
0.45
L1
k
1.00
0.60
0.75
1.00
0
aaa
8
0.10
DocID024306 Rev 6
29/33
33
Package information
8.2
STAP16DPPS05
TSSOP24 exposed pad packing information
Figure 26. TSSOP24 exposed pad tape and reel outline
30/33
DocID024306 Rev 6
STAP16DPPS05
Package information
Table 17. TSSOP24 exposed pad tape and reel mechanical data
mm
Dim.
Min.
A
Typ.
Max.
330
C
12.8
D
20.2
N
60
T
13.2
22.4
Ao
6.8
7
Bo
8.2
8.4
Ko
1.7
1.9
Po
3.9
4.1
P
11.9
12.1
DocID024306 Rev 6
31/33
33
Revision history
9
STAP16DPPS05
Revision history
Table 18. Document revision history
32/33
Date
Revision
Changes
21-May-2013
1
Initial release.
01-Jul-2013
2
Added footnote in Table 8: Switching characteristics.
11-Oct-2013
3
Modified TOPR value in Table 4: Absolute maximum ratings.
10-Mar-2014
4
Modified footnote 1 in Table 8: Switching characteristics.
Added footnote 2 in Table 8: Switching characteristics.
Updated Table 1: Pin connections and Table 3: Pin description.
05-Jun-2014
5
Updated Table 16: TSSOP24 exposed pad mechanical data.
Minor text changes.
10-Nov-2015
6
Updated features in cover page.
Minor text changes.
DocID024306 Rev 6
STAP16DPPS05
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
DocID024306 Rev 6
33/33
33
Similar pages