cd00233604

AN2982
Application note
1 x 54 W T5 fluorescent lamp ballast in wide input voltage range
using the L6585DE - STEVAL-ILB005V2
Introduction
This application note describes the STEVAL-ILB005V2 demonstration board equipped with
the L6585DE lighting controller, STD7NM50N MOSFETs and an STTH1L06 Shottky diode
able to drive a 54 W linear T5 fluorescent lamp in a wide input voltage range (88 - 277 Vac).
The design steps, schematic and board performance are also given.
The L6585DE lighting controller embeds both the PFC stage and ballast stage suitable for
driving all kinds of lamps (T8, T5, T4, CFLn,...) and all kinds of topologies having an input
power greater than 25 W.
New T5 lamps are characterized by very high luminous efficiency and compactness. To
optimize their performance, high accuracy in both preheating of the cathodes and steadystate parameters is required. The minimum performance of T5 ballasts together with their
minimum safety requirements are summarized in international norms, especially IEC613472-3, IEC60929, and IEC60081.
The demand for these lamps is rapidly growing and the L6585DE is able to control electronic
ballasts meeting all performance specifications and reliability with low component count and
a small PCB.
The STEVAL-ILB005V2 has been developed to drive a 54 W T5-HO lamp.
Figure 1.
STEVAL-ILB005V2 demonstration board
!-V
March 2010
Doc ID 15599 Rev 1
1/31
www.st.com
Contents
AN2982
Contents
1
2
3
4
2/31
Designing the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Design requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
PFC design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1
Output voltage and dynamic OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2
Boost choke design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3
MOSFET selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.4
Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.5
Bulk capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.6
Multiplier biasing and selection of PFC current sense resistor . . . . . . . 10
1.2.7
Error amplifier compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.8
Input rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.9
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.10
Input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ballast stage design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1
Resonant network and operating point design . . . . . . . . . . . . . . . . . . . . . 15
2.2
Selection of parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3
Half-bridge design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4
End of life detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
IC power supply design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Demonstration board schematic and bill of material . . . . . . . . . . . . . . 23
3.1
Demonstration board performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2
Ballast stage performance and reliability . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 15599 Rev 1
AN2982
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
STEVAL-ILB005V2 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PFC MOSFET frequencies along mains half period (fmains = 50 Hz) for various input
voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Summary of PFC MOSFET power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Multiplier bias points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bode plot with simple compensation network: |Gloop|MAX < 35dB . . . . . . . . . . . . . . . . . . 12
Bode plot with enhanced compensation network: |Gloop|MAX < 35 dB and
F margin > 45° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Complete EMI filter (differential mode inductors are not present in this design). . . . . . . . . 14
Resonant inverter simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Resonance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Parameters setting block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Blocking capacitor to ground topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Charge pump network and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STEVAL-ILB005V2 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input performance - power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input performance - total harmonic distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EMI spectrum at 277 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EMI spectrum at 88 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Steady-state lamp parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Startup sequence with open lamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ballast anti-choke saturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EOL protection (positive deviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EOL protection (negative deviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 15599 Rev 1
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Designing the application
1
AN2982
Designing the application
The STEVAL-ILB005V2 design follows the AN2870 design guidelines. In this section the
design specifications and the equations used are given.
1.1
Design requirements
Table 1.
Summary of design requirements
Description
Values
Input voltage
88 to 277 Vac (110 to 230 Vac ±20%)
Mains frequency
50 Hz – 60 Hz
PF
> 0.975
Current THD
< 10%
Lamp type
T5 -54 W HO (Ilamp = 460 mArms; Vlamp = 117 Vrms)
Max output voltage
900 Vrms
Lamp connection
Current preheated, Cblock to ground topology
Efficiency
90%
Figure 2.
Typical application schematic
6OUT
4PFC
$BOOST
2INVH
2CTRH
#OUT
2ECTIFIER
"RIDGE
2CP #CP
2CTRL
2INVL
#IN
6
#
2ZCD
#BOOT
#COMP
:#$
6IN
2SU
#CTR
-PFC
).6
#/-0
6CC
#42
-HS
"//4
0&'
(3$
,BALLAST
2MULTH
0&##3
,$%
,AMP
/54
-LS
-5,4
2MULT
#MULT
2PFCS
'.$
/3#
2&
#OSC 2PRE
%/)
4#(
%/,0
%/,
("#3
#RES
2EOL
2D
2P
#IGN
2RUN
,3$
#D
2EOL
2HBCS
#EOL
#BLOCK
!-V
4/31
Doc ID 15599 Rev 1
AN2982
Designing the application
1.2
PFC design
1.2.1
Output voltage and dynamic OVP
The maximum input voltage is equal to:
Equation 1
V in,max = 277 V ⋅ 2 = 391.7 V
An output voltage equal to Vout = 420 V is chosen for better PFC performance.
Choosing Rinvh = 3 x 2.2 MΩ, the output voltage is equal to:
Equation 2
⎛ R
Vout = 2.52V ⋅ ⎜⎜1 + invh
Rinvl
⎝
⎞
⎟⎟
⎠
→ Rinvl =
Rinvh
= 39839 Ω → R invi = 39.7 kΩ
⎛ Vout
⎞
− 1⎟
⎜
⎝ 2.52V ⎠
The ripple superimposed on Vout is chosen equal to 5%. Then, the maximum instantaneous
output voltage is equal to 441 V and, therefore, the OVP level must be comprised between
450 V and 500 V.
–
VOVP = 480 V is chosen and the CTR pin voltage divider is dimensioned
accordingly
–
Rctrh = 3 x 825 kΩ
Equation 3
⎛ R
⎞
R ctrh
VOVP = 3.4 V ⋅ ⎜⎜1 + ctrh ⎟⎟ → R ctrl =
= 17656 Ω → R invi = 18 kΩ
V
R
⎛
⎞
OUT,MAX
ctrl ⎠
⎝
⎜⎜
− 1⎟⎟
⎝ 3 .4 V
⎠
1.2.2
Boost choke design
The minimum PFC frequency is chosen equal to fPFC,min > 15 kHz. The maximum
inductance value is equal to:
Equation 4
fPFC,min =
⎛
Vin2
2 ⋅ Vin ⎞⎟
Vin2
⋅ ⎜1 −
→L ≤
2 ⋅ Pin ⋅ fPFC,min
Vout ⎟⎠
2 ⋅ Pin ⋅ L ⎜⎝
⎛
2 ⋅ Vin ⎞⎟
⋅ ⎜1 −
= 2.6 mH
⎜
Vout ⎟⎠
⎝
Lpfc = 1.5 mH is selected. The following graph depicts the frequencies that are obtained
along the mains period for various input voltages.
Doc ID 15599 Rev 1
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Designing the application
Figure 3.
AN2982
PFC MOSFET frequencies along mains half period (fmains = 50 Hz) for
various input voltages
!-V
The maximum choke current is equal to:
Equation 5
IL,max = 2 ⋅ 2 ⋅
Pin
= 1.93 A
Vin,min
A saturation current higher than IL,sat = 2.2 A is used in order to take into account the
tolerance of this parameter.
The RMS current flowing into the choke is equal to:
Equation 6
IL,RMS =
Pin
= 787 mA
3 Vin,min
2
The choke form factor is an EF25 core (Ae = 52 mm2, le = 58 mm, material N87 or
equivalent having Bmax<320 mT).
Its design parameters are as follows:
Equation 7
⎫
⎪
μ0N2A e
⎪
= 2.63 mm
⎬ → lgap = 2 ×
L
L
2⎪
AL = 2 = 49.5 nH / turns
⎪⎭
N
N=
ImaxL
= 174 turns
BmaxA e
The maximum power dissipation of the core should be less than 2.5 W in the worst
condition.
A multi-conductor wire is used in order to reduce the equivalent resistance at high
frequency.
6/31
Doc ID 15599 Rev 1
AN2982
Designing the application
When the maximum RMS current is obtained, the minimum frequency is detected and the
RHF of the choke must be less than:
Equation 8
RHF,max =
PL,Ω
2
IL,RMS
=4Ω
Using a 13 x 0.1 mm2 wire, 3.5 Ω is obtained.
The core losses, at minimum input voltage, are estimated below 0.35 W, therefore the total
losses are lower than 2.5 W as expected. The higher the input voltage is, the lower the
power dissipation (e.g. at 220 Vac the estimated total power losses are lower than 1.8 W).
The transformer ratio can be calculated as:
Equation 9
(
)
Vaux ,zcd = Vout − 2 ⋅ Vin > m ⋅ 1.4 V → m < 14.18 → m = 6 → N sec = 29turns
Considering a maximum ZCD current equal to 1 mA, the limiting resistor is:
Equation 10
R zcd =
1.2.3
2 ⋅ Vin,max
m ⋅ IZCD
→ R zcd > 65.3 kΩ → R zcd = 75 kΩ
MOSFET selection
The PFC MOSFET must have a Vbdss = 500 V and a peak drain current greater than
Id,max = 2.2 A.
The maximum allowed MOSFET dissipation is equal to PMOS,max = 1 W in all conditions.
The total power dissipation is composed of:
●
Conduction losses, dominant at low input voltage:
Equation 11
⎛ P
2
PCOND = R ds,on ⋅ IMOS,RMS = R ds,on ⋅ 8⎜ in
⎜V
⎝ in,rms
2
⎞ ⎡ 1 4 2 Vin,rms ⎤
2
⎟ ⎢ −
⎥ = R ds,on ⋅ 0.5278 A
⎟ 6
π
9
V
⎥
out ⎦
⎠ ⎢⎣
Equation 12
RDS( on) (max) <
●
PCOND,max
0.5278 A 2
Switching losses, directly proportional to the average switching frequency:
Equation 13
fSW =
Vin2,RMS ⎛ 2 2 VIN,RMS ⎞
⎜1 −
⎟
⋅
π
2 ⋅ Pin ⋅ L ⎜⎝
Vout ⎟⎠
Doc ID 15599 Rev 1
7/31
Designing the application
AN2982
Equation 14
Pcross = t f fsw VOUT
●
t f fsw
Pin
=
⋅ 25200
Vin,rms Vin,rms
Capacitive losses, present only when Vin > Vout/2 and have their maximum at Vin,max
The maximum time when the input voltage is greater than Vout/2 can be calculated as
follows:
Equation 15
⎛
Vout
arcsin⎜
⎜ 2⋅ 2 ⋅V
in,rms
⎝
t1 =
2πfmains
t2 =
⎞
⎟
⎟
⎠ → 1.8 ms
1
− t1 → 8.2 ms
2fmains
Within this interval the capacitive losses are:
Equation 16
⎛
Pcap = fsw ⎜⎜ 3.3C oss VDrain
⎝
3
2
+
1
(Crss + Coss + Cext ) VDrain
2
2⎞
⎟
⎟
⎠
where <fsw> = 173 kHz and:
Equation 17
VDrain = 2fmains
∫ [2
t2
t1
]
2 ⋅ Vin,rms sin(ωt ) − Vout dt = 209.7 V
2
Using Equation 11 to 17 with the constraint Ptot < 1 W, the following parameters are found:
–
RDS(on) < 1.4 Ω (Pcond at 88 V < 0.75 W)
–
tf < 10 ns (Pcross at 88 V < 0.10 W)
–
Coss < 110 pF (considering Cext and Crss equal respectively 68 pF and 4 pF)
The following ST MOSFETs meet these constraints:
–
STD5NK50Z
–
STD6NK50Z
–
STD7NM50N
The STD7NM50N has RDS(on) = 1.12 Ω (at 100° C), tf = 9 ns and Coss = 67 pF and therefore
is considered suitable for this design. The total power dissipation is shown in Figure 4.
8/31
Doc ID 15599 Rev 1
AN2982
Designing the application
Figure 4.
Summary of PFC MOSFET power losses
!-V
1.2.4
Boost diode selection
Both the boost diode maximum RMS current and the RMS current are equal to:
Equation 18
Id,rms =
4 2 2
3 π
Pin
VOUT Vin,rms
= 222 mA
Their average current is equal to:
Equation 19
P out
----------- = 142mA
V out
The STTH1L06 Shottky diode is selected, having Vrrm = 600 V and an average forward
current If(AV) = 1 A. Total power dissipation is equal to:
Equation 20
PD = 0.89 ⋅ 0.142 + 0.165 ⋅ 0.222 2 = 134.5 mW
1.2.5
Bulk capacitor selection
The ripple superimposed on the output voltage is equal to ±20 V:
Equation 21
ΔVout = 20 V =
=
Pout
+ [email protected],min ⋅ ICout ,RMS =
4π ⋅ fmains ⋅ Vout ⋅ C out
2.0463 × 10 − 4
+ ESR ⋅ 373 mA
C out
Doc ID 15599 Rev 1
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Designing the application
AN2982
The RMS value of the bulk capacitor current is:
Equation 22
ICout ,RMS =
⎛P
Pin2
32 ⋅ 2
⋅
− ⎜⎜ out
9π
Vin,rms ⋅ Vout ⎝ Vout
2
⎞
⎟ = 373 mA
⎟
⎠
Considering the first term of Equation 21 as dominant, Cout > 10.2 µF, and then Cout = 22 µF
is selected.
The voltage rating of the capacitor is equal to VCout = 450 V and the temperature class is
TCout = 105 °C. With this value the typical ESR is around 2 Ω, adding only 740 mV to the
total ripple.
1.2.6
Multiplier biasing and selection of PFC current sense resistor
The peak values of the input voltage are between 124.4 V and 391.7 V. The ratio between
these two values is equal to 3.15. The MULT pin is biased to 1 V when input voltage is equal
to 124.4 V. If Rmulth = 3x680 kΩ:
Equation 23
VMULT,1
kp =
Vin,min
Figure 5.
= 0.00804 → Rmultl =
pk
kp
Rmulth = 16.53 kΩ → R multh = 16.2 kΩ
1 − kp
Multiplier bias points
!-V
with VCS,1 = 0.75 V:
Equation 24
Rpfccs =
VCS,1
IL,max
=
VCS,1 ⋅ Vin,min
2 ⋅ 2 ⋅ Pin
= 0.364 Ω → R pfccs = 0.33 Ω
A Cmult=1 nF capacitor is used in parallel with Rmultl for HF noise filtering.
10/31
Doc ID 15599 Rev 1
AN2982
1.2.7
Designing the application
Error amplifier compensation
Figure 6.
Control loop block diagram
!-V
Equation 25
2
G(s) =
1 k Mk p Vin,rms R out
4
Vout
Rpfcs
1
1
2
= 0.020308 ⋅ Vin,rms ⋅
R out C out
1 + 0.029623 s
1+ s
2
where:
–
kM = multiplier factor = 0.52
–
kp = mult pin divider = 0.007879
–
Rout = equivalent output resistor = 2.693 kΩ
–
Cout = 22 µF
Using the simplest compensation network (a capacitor placed between the INV and COMP
pin) whose transfer function is equal to:
Equation 26
Gcomp (s ) =
1
1
=
sC compRinvh sC comp ⋅ 6.6 MΩ
and setting an open loop gain less than 0.001 when frequency is equal to twice the mains
frequency, it is possible to calculate the minimum capacitance needed.
Equation 27
⎞
⎛
1
1
⎟ ⋅ 0.020308 ⋅ Vin,rms 2 ⋅
Gloop (s ) = G(s ) ⋅ Gcomp (s ) = ⎜
⎜ sC comp 6.6 MΩ ⎟
1
+
0
.
029623
s
⎠
⎝
= 0.001
s = 2 π100 Hz
A Ccomp = 1 µF ceramic capacitor could be a good trade-off between performance and cost,
but better performance can be obtained using a more complicated structure in order to
obtain a phase margin equal to 45°.
Doc ID 15599 Rev 1
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Designing the application
Figure 7.
AN2982
Bode plot with simple compensation network: |Gloop|MAX < 35dB
!-V
For example, an RC-series network is connected between the INV and COMP pin. The
obtained Gloop(s) can be written as:
Equation 28
⎛ 1 + sC compR comp
Gloop (s ) = G(s ) ⋅ Gcomp (s ) = ⎜
⎜ sC comp 6.6 MΩ
⎝
⎞
1
⎟ ⋅ 0.020308 ⋅ Vin,rms 2 ⋅
⎟
1 + 0.029623 s
⎠
A phase margin equal to 45° is obtained at Vin = 277 Vac using Ccomp=1.5 µF and
Rcomp=39 kΩ. At minimum input voltage the phase margin is equal to 85°.
Higher values of Ccomp or a lower value of Cout can also improve the PFC performance.
Figure 8.
Bode plot with enhanced compensation network: |Gloop|MAX < 35 dB and
Φ margin > 45°
!-V
12/31
Doc ID 15599 Rev 1
AN2982
1.2.8
Designing the application
Input rectifier
A 2KBP06M bridge rectifier is able to sustain 600 V in reverse condition and 2 A of forward
current. Its maximum power dissipation is equal to:
Equation 29
PB = 2 2
1.2.9
Pin
Vin,rms(min)
VF = 1.73 W
Input capacitor
Let r = 10% be the maximum allowed ratio between the high-frequency ripple amplitude
seen at the input of the PFC stage and the mean value of the input current:
Equation 30
Cin,min =
1.2.10
Pin
2π ⋅ r ⋅ fsw
⋅ Vin,RMS(min)
min
2
= 401.87 nF → Cin = 470 nF
Input circuitry
The input circuitry is composed of:
–
A fuse: avoids damage due to ballast breaking or excessive current from the
mains
–
An NTC: limits the inrush current which avoids blowing the fuse and reduces the
effects of a burst from the mains. This component reduces its resistance at a
higher temperature. A 5 Ω NTC (at 25 °C) is used
–
A varistor (not present): absorbs the energy associated with a mains surge
avoiding that Vout increases over the rated voltage of the components (Cout,
MOSFETs, IC,…)
–
An EMI filter: an LC network able to reduce the HF noise coming from the
application and traveling through the mains. This filter has to filter both the
common mode component of the noise (which can be measured between the AC
input and the EARTH) and the differential mode component of the noise (which
can be measured between the two AC inputs)
The first component (the fuse) is filtered by a CM filter (a current transformer that forces the
AC input currents to travel in the opposite way) and two 1 nF capacitor placed between each
AC input and EARTH. The second component (the NTC) is filtered by two capacitors placed
across the AC inputs and by the leakage inductance of the CM filter. In fact by using a CM
transformer having a high leakage inductance, a differential filtering can be obtained. The
differential capacitors are equal to CX = 100 nF, while the CM capacitors are equal to
CY = 1 nF. The CM transformer, TCM, is a B82733F series transformer from EPCOS.
Doc ID 15599 Rev 1
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Designing the application
Figure 9.
AN2982
Complete EMI filter (differential mode inductors are not present in this
design)
!-V
14/31
Doc ID 15599 Rev 1
AN2982
2
Ballast stage design
Ballast stage design
Figure 10. Resonant inverter simplified schematic
!-V
2.1
Resonant network and operating point design
Equivalent voltage applied to the resonant network:
Equation 31
Vbal,pk =
2
Vout = 267.38 Vpk
π
L and C are chosen in order to fit the following constraints:
●
Preheating voltage has to be less than 240 Vac = 339.4 Vpk
●
Maximum striking voltage is equal to 700 Vac
●
Nominal lamp voltage = 117 Vac
●
Nominal lamp current = 0.46 A
Selecting a common value equal to Lres=1.35 mH and Cres=4.7 nF, the following parameters
are obtained:
Equation 32
1
⎧
= 64387 Hz
⎪f0 =
2
L
C
π
res
res
⎪
⎪
L res
⎪
= 526 Ω
⎨Z 0 =
Cres
⎪
⎪
R
⎪Q = lamp = Vrun = 0.4836
⎪⎩
Z0
Irun Z 0
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Ballast stage design
AN2982
The run and preheating frequencies are calculated using the values calculated in Equation
33:
Equation 33
frun = f0
2
⎛
4Vout
1 ⎞
1 ⎞
⎛
⎛
⎜2 − 2 ⎟ + ⎜2 − 2 ⎟ − 4 + ⎜
⎜
Q ⎠
Q ⎠
⎝
⎝
⎝ π ⋅ Z 0 ⋅ Q ⋅ 2Irun
fpre = f0 1 +
fign = f0 1 +
2
⎞
⎟
⎟
⎠
2
= 48.5 kHz
2Vout
> 86 kHz → fpre = 100 kHz
πVpre
2Vout
π ⋅ 2 ⋅ Vign
≈ 72.5 kHz
Figure 11. Resonance curves
!-V
The maximum striking current is equal to:
Equation 34
Iballast,ign
⎛
⎜
⎜
⎜ 2⋅V
out
=⎜
⎜ π ⋅ Z0
⎜
⎜⎜
⎝
⎛ fign
1 + ⎜⎜ Q
⎝ f0
⎡ ⎛f
ign
Q 1 − ⎜⎜
⎢ ⎝ f0
⎣
2⎢
⎞
⎟
⎟
⎠
2⎤
2
⎞
⎟
⎟
⎠
⎛f ⎞
⎥ + ⎜ ign ⎟
⎜ f ⎟
⎥
⎝ 0 ⎠
⎦
2
⎞
⎟
⎟
⎟
⎟ = 2.121 Apk
⎟
⎟
⎟⎟
⎠
This current is also the saturation current of the ballast choke (Isat,ballast > 2.2 A).
Limiting the current to this value, the lamp voltage is limited to 700 Vac (VCres,max > 700
Vac). The half-bridge current sense resistor is chosen according to:
Equation 35
Rhbcs =
16/31
Vhbcsh
Iballast,ign
=
1 .6 V
= 0.7543 Ω → R pfccs = 0.33 Ω
2.121 A
Doc ID 15599 Rev 1
AN2982
Ballast stage design
The RMS value of one side of the half bridge is equal to:
Equation 36
Ihb,RMS ≈
Iballast,pk
2
=
1 2 ⋅ Vout
⋅
2 π ⋅ Z0
⎛ f ⎞
1 + ⎜⎜ Q run ⎟⎟
⎝ f0 ⎠
2
2
⎡ ⎛ f ⎞2 ⎤
⎛ frun ⎞
2⎢
run
⎟ ⎥ + ⎜⎜
⎟⎟
Q 1 − ⎜⎜
⎢ ⎝ f0 ⎟⎠ ⎥
⎝ f0 ⎠
⎣
⎦
= 0.3465 A
The power dissipation of the half-bridge current sense resistor is equal to:
Equation 37
Phbcs ≈ Rhbcs ⋅ I2hbcs ,RMS < 100 mW
A blocking capacitor Cblock = 100 nF (400 Vac) is used.
The choke form factor is an EF25 core (Ae = 52 mm2, le = 58 mm, material N87 or
equivalent having Bmax<300 mT).
Its design parameters are as follows:
Equation 38
⎫
⎪
μ 0N 2 A e
⎪
= 3.37 mm
⎬ → l gap = 2 ×
L
L
A L = 2 = 38.8 nH / turns 2 ⎪
⎪⎭
N
N=
Imax L
= 183 turns
Bmax A e
For this component a multi-conductor wire is also used to reduce the HF equivalent
resistance, and therefore the power dissipation.
2.2
Selection of parameters
Figure 12. Parameters setting block
!-V
Cosc = 1 nF (5% or better) is chosen.
The following constant values are calculated (COSC in pF):
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Ballast stage design
AN2982
Equation 39
k=
499.6 ⋅ 10 3
(COSC )0.872
= 1209.55
Equation 40
e = 1−
1.33
(COSC )0.581
= 0.976
Given the run frequency and the preheating frequency (both in kHz), the following
components are found:
Equation 41
1
Rrun
⎛ k ⎞e
⎟ = 26.99 kΩ → Rrun = 26.7 kΩ
= ⎜⎜
⎟
⎝ frun ⎠
Rpre // Rrun
⎛ k
=⎜
⎜ fpre
⎝
1
⎞e
⎟ = 12.86 kΩ → Rpre = Rrun ⋅ 12.86 kΩ = 24.9 kΩ
⎟
Rrun − 12.86 kΩ
⎠
An ignition time equal to 50 ms is obtained using a Cign corresponding to:
Equation 42
Tign = 3Rpre Cign → C ign = 680nF
A protection time equal to 120 ms is adopted, then:
Equation 43
Tprot = 269740 ⋅ C d → Cd = 470nF
The preheating time is equal to almost 1 s, therefore:
Equation 44
Tpre = 4.63
Cd
ITCH
⎛ 4.63 ⎞
+ R d C d ln⎜
⎟ → R d = 1.755MΩ
⎝ 1 .5 ⎠
The closest commercial resistor for Rd is 1.5 MΩ. With this value Tpre is equal to 865 ms.
2.3
Half-bridge design
The maximum power loss acceptable for half-bridge MOSFETs is equal to 500 mW. Each
MOSFET experiences a conduction loss equal to:
Equation 45
P cond = RDS( on ) ⋅ (Irms ) <0.25 W
2
With Irms2 = 0.120 A2, a maximum RDS(on)= 2.08 Ω is obtained.
18/31
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AN2982
Ballast stage design
The following ST MOSFETs meet these constraints:
–
STD5NK50Z
–
STD6NK50Z
–
STD7NM50N
The STD7NM50N has RDS(on)= 1.12 Ω (at 100°C), therefore the power dissipation related to
the half-bridge MOSFETs is equal to almost 270 mW.
The size of the boostrap capacitor can be calculated by solving the following equation:
Equation 46
C gate + Cboot,min =
Cboot,min ⋅ Vcc
Vcc − ΔV
where:
ΔV = Vcc,min - Vgate,min = 9.6 V - 8 V = 1.6 V
Vcc = 15 V - Vf, Vf = forward voltage of charge pump diode = 0.8 V
Qg = total gate charge of STD7NM50N = 12 nC
Cgate = Qg/Vcc = 845 pF
Cboot,min = 6.6 nF is obtained
A Cboot = 100 nF is selected and the voltage drop is equal to ΔV = 120 mV.
The charging time of the capacitor is calculated to check if ΔV is compensated during the
on-time of the low side. The time the capacitor takes to charge to 95% of Vcc starting from 0
is equal to:
Equation 47
t 0 = 3 ⋅ Rboot ⋅ Cboot = 3 ⋅ 250 Ω ⋅ 100 nF = 75 μs
The time the capacitor takes to charge to 95% of Vcc minus 120 mV starting from 0 is equal
to:
Equation 48
⎛ 0.95 ⋅ Vcc − 0.12 ⎞
⎟ = 2.839 ⋅ Rboot ⋅ Cboot = 71 μs
t1 = −Rboot ⋅ Cboot ⋅ ln⎜⎜1 −
⎟
Vcc
⎠
⎝
The difference t0 - t1 = 4 µs is smaller than the minimum on-time equal to:
Equation 49
Ton,min =
1
− TDEAD,max = 4.11 μs
2fpre
The selected capacitor is able to correctly supply the high-side driver.
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Ballast stage design
2.4
AN2982
End of life detection
In this design the blocking capacitor to ground configuration is chosen.
Figure 13. Blocking capacitor to ground topology
!-V
The tracking configuration with a window of amplitude equal to 240 mV is selected,
connecting EOLP to ground with REOLP = 240 kΩ.
The EOL pin detects the blocking capacitor voltage by means of a voltage divider that, in
normal conditions, sets its voltage to the same value as the CTR pin:
Equation 50
VCTR,0 = Vout
R ctrl
= 3.03 V ← VEOL
R ctrl + R ctrh
Choosing the total upper resistor value equal to Reol1 = 1.36 MΩ (2x680 kΩ), and with the
steady-state value of the blocking capacitor voltage equal to Vout/2, the lower resistor is
calculated as:
Equation 51
Reol2 = R eol1
2VEOL
= 19.9 kΩ → Reol2 = 20 kΩ
VOUT − 2VEOL
A Ceol = 10 nF capacitor is used to filter the lamp frequency, maintaining the ripple. The
obtained cutoff frequency is calculated higher than 100 Hz, but lower than 49 kHz.
Equation 52
fc,eol ≈
20/31
1
= 796 Hz
2π ⋅ Reol2 ⋅ C eol
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AN2982
2.5
Ballast stage design
IC power supply design
The IC current consumption depends on both the PFC frequency and half-bridge frequency.
In the worst case, the mean value of the PFC frequency is equal to 162 kHz and the
maximum half-bridge frequency is equal to 90 kHz.
With these values the maximum supply current is approximately equal to:
Equation 53
IccmA = 0.0192 ⋅ fPFC
kHz
+ 0.0373 fprekHz + 4.56 ≈ 11 mA
This current is delivered to the IC by means of a charge pump connected to the middle point
of the half bridge.
Figure 14. Charge pump network and startup
!-V
The current delivered by the charge pump capacitor is approximately:
Equation 54
Icp = Icp,pk ⋅ Trise ⋅ frun ≥ Icc
where:
Equation 55
Icp,pk = C cp
Vout
Trise
and rearranging the terms:
Equation 56
C cp ≥
Icp
VOUT ⋅ frun
= 558 pF → C cp = 1 nF
The startup network works also as a detector of lamp presence. This feature can be
implemented by placing one or both of the lamp cathodes along the startup network path. If
the lamp is absent, the IC cannot start.
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Ballast stage design
AN2982
The minimum startup current of the L6585DE is equal to Icc,on = 370 µA. This current has to
be delivered to the IC at the minimum input voltage (125 Vpk), therefore a total resistance
equal to:
Equation 57
R su,tot =
Vin,min
Icc,on
= 337 kΩ
The network is divided into 5 x 68 kΩ resistors in order to avoid damage due to the lamp
striking voltage.
A C1 = 10 µF followed by a 100 nF ceramic capacitor is used as the Vcc bulk capacitor.
22/31
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3
Demonstration board schematic and bill of material
Demonstration board schematic and bill of material
Figure 15. STEVAL-ILB005V2 schematic
!-V
Doc ID 15599 Rev 1
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Demonstration board schematic and bill of material
Table 2.
AN2982
BOM
Reference
Value
Note
R1
681 kΩ
R2
681 kΩ
R3
681 kΩ
R4
16.2 kΩ
R5
2.2 MΩ
R6
2.2 MΩ
R7
2.2 MΩ
R8
39.2 kΩ
R9
n.m.
R10
75 kΩ
Rzcd
R11
47 Ω
PFC MOSFET gate resistor
R12
220 Ω
PFC current sense filtering resistor
R13
825 kΩ
R14
825 kΩ
R15
825 kΩ
R16
18 kΩ
Rctr,lo
R18
26.1 kΩ
Rrun
R19
29.4 kΩ
Rpre
R20
1.5 MΩ
RD
R21
0R0
R22
240 kΩ
R23
0R0
R24
47 Ω
High-side MOSFET gate resistor
R25
47 Ω
Low-side MOSFET gate resistor
R26
3.3 Ω
R27
3.3 Ω
R28
68 kΩ
R29
68 kΩ
R30
560 kΩ
R31
120 kΩ
R32
20.5 kΩ
R33
68 kΩ
R34
68 kΩ
R35
68 kΩ
Rmult,hi
Rmult,lo
Rinv,hi
Rinv,lo
Rctr,hi
Reolp
Charge pump limiting resistor
Startup network
24/31
Doc ID 15599 Rev 1
REOL,hi (1)
REOL,lo
Startup network
AN2982
Demonstration board schematic and bill of material
Table 2.
BOM (continued)
Reference
Value
Note
R40
680 kΩ
REOL,hi (2)
R41
n.m.
RS1
0.33 Ω – 0.5 W
Rpfccs
RS2
0.82 Ω – 0.5 W
Rhbcs
C1
22 µF – 450 V
COUT
CA1
0R0
C2
470 nF – 305 Vac
Cin
C3
4.7 nF
MULT filtering capacitor
C4
1 nF
PFCCS filtering capacitor
C5
1 µF
Ccomp
C6
n.m.
C7
10 nF
CTR filtering capacitor
C8
1 nF - 1%
Cosc
C9
1 µF
Cign
C10
470 nF
Cd
C11
100 nF
Cboot
C12
1 nF - 630Vdc
Ccp
C13
10 µF
CVcc
C14
100 nF
CVcc,b
C15
4.7 nF - 2 kV
Cres
C16
100 nF - 630Vdc
Cblock
C17
10 nF
EOL filtering capacitor
C18
1 nF
C20
100 nF, X2, 275Vac
Differential mode EMI filter
C21
100 nF, X2, 275Vac
Differential mode EMI filter
C22
1 nF Y1
Common mode EMI filter (capacitive)
C23
1 nF Y1
Common mode EMI filter (capacitive)
C24
0R0
D1
STTH1L06
Boost diode
D2
1N4148
Charge pump forward diode
D3
1N4148
PFC gate speed-up diode
DZ1
BZX84C15
Charge pump free-wheeling Zener diode
DZ2
0R0
DZ3
0R0
DZ4
n.m.
Doc ID 15599 Rev 1
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Demonstration board schematic and bill of material
Table 2.
3.1
AN2982
BOM (continued)
Reference
Value
Note
B1
2KBP06M
Rectifier bridge
U1
L6585DE
Ballast controller
Q1
STD7NM50N
PFC MOSFET
Q2
STD7NM50N
Half-bridge high-side MOSFET
Q3
STD7NM50N
Half-bridge low-side MOSFET
T1
1.5 mH - 2.6 A
PFC transformer – EPCOS B78313P8140
T2
2 x 68 mH - 0.9 A
Common mode EMI filter – EPCOS B82733F2901
L1
1.3 mH - 2.6 A
Ballast choke – ITACOIL E2543-H
F1
T 2 A – 250 Vac
Fuse
RT1
NTC 5 Ω
Inrush current limiter
Demonstration board performances
Figure 16. Input performance - power factor
Figure 17. Input performance - total harmonic
distortion
34%6!,),"64($
34%6!,),"60&
0&
4($
6IN6AC
Figure 18. EMI spectrum at 277 Vac
!-V
Figure 19. EMI spectrum at 88 Vac
!-V
26/31
6IN6AC
!-V
Doc ID 15599 Rev 1
!-V
AN2982
3.2
Demonstration board schematic and bill of material
Ballast stage performance and reliability
Figure 20 shows the lamp parameters. Small discrepancies between theoretical and real
measurements are due to the tolerance of the passive components of the resonance
network (Lres and Cres).
Figure 20. Steady-state lamp parameters
!-V
Figure 21 summarizes the Tch sequences during preheating and protections. During the
open lamp test, Tch voltage (lower trace) sets the preheating time (Tpre = 805 ms). After that
the lamp voltage (upper trace) increases up to the maximum value allowed by the HBCS
resistor (740 Vrms). The subsequent protection time is shorter than the preheating time
(120 ms).
Figure 21. Startup sequence with open lamp protection
!-V
In Figure 22 a close-up of the waveforms during a ballast choke saturation is shown. The
upper graph illustrates the lamp parameters. While the lamp voltage remains essentially
sinusoidal, the lamp current becomes triangular cycle by cycle. The lower trace illustrates
the half-bridge current sense voltage (VHBCS). As soon as this voltage reaches 2.75 V, the
application is immediately stopped.
The saturation effect does not have a definite threshold. Once the current is close to
saturation, the inductance value starts to decrease slowly and constantly, therefore a current
Doc ID 15599 Rev 1
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Demonstration board schematic and bill of material
AN2982
limiting that maintains the frequency constant is not suitable to counter this effect. Actually
the application should be stopped as soon as the saturation effect is detected.
Figure 22. Ballast anti-choke saturation protection
!-V
Asymmetrical ageing of the lamp is detected by the EOL pin. Figure 23 and 24 illustrate the
behavior of this protection. In the upper trace the lamp voltage and Tch voltage are shown.
When the lamp starts ageing, the lamp voltage increases in one direction. The EOL voltage
(lower trace) moves together with the blocking capacitor voltage. Once the difference
between the CTR voltage and the EOL voltage is higher than 240 mV, a Tch cycle is started
and the application is stopped if this situation persists.
Figure 23. EOL protection (positive deviation)
!-V
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Doc ID 15599 Rev 1
AN2982
Demonstration board schematic and bill of material
Figure 24. EOL protection (negative deviation)
!-V
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Revision history
4
AN2982
Revision history
Table 3.
30/31
Document revision history
Date
Revision
15-Mar-2010
1
Changes
Initial release.
Doc ID 15599 Rev 1
AN2982
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