Details

3.2 mm x 5.0 mm Ceramic Low Noise SMD VCXO
LVCMOS/LVPECL/LVDS
Product Features
Applications
Small Surface Mount Package
Low RMS Phase Jitter
Frequencies to 1500 MHz
Pb Free/ RoHS Compliant
Leadfree Processing
xDSL
Broadcast video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
I641 - Series
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
Frequency
LVCMOS
LVPECL
LVDS
10 MHz to 250 MHz
10 MHz to 1500 MHz
10 MHz to 1500 MHz
Output Level
LVCMOS
LVPECL
LVDS
VOH=90% VDD min., VOL=10 % VDD max.
VOH=VDD-1.03V max. (Nom. Load), VOL=VDD-1.6V max. (Nom. Load)
VOD=(Diff. Output) 350mV Typ.
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
50% ±5% @ 50%VDD
50% ±5% @ 50%*
50% ±5% @ 50%*
3.0 ns max. (90%/10%)*
0.6 ns max. (80%/20%)*
0.6 ns max. (80%/20%)*
Recommended Pad Layout
15pF
50  to VDD - 2.0 VDC
RL=100 /CL=10pF
Frequency Stability
See Table Below
Supply Voltage
3.3 VDC ± 10%, 2.5VDC ± 5%
Current
LVCMOS = 45 mA max., LVPECL = 65 mA max., LVDS = 35 mA max.
Linearity
10% max.
Pullability
See Table Below
Control Voltage
1.65 VDC ± 1.65 VDC @ 3.3V
1.25 VDC ± 1.25 VDC @ 2.5V
50K  min.
Input Impedance
Phase Jitter (RMS)
At 12kHz to 20 MHz
Operating Temp.
Range
Storage
0.5 ps typical
Dimension Units: mm
See Table Below
-40 C to +100 C
Part Number Guide
Package
I641
Input
Voltage
Pin Connection
1
Voltage Control
2
Enable/Disable or N/C
3
GND
4
Output
5
Output or N/C
6
VDD
Operating
Temperature
Sample Part Number:
Stability
(in ppm)
Pullabilty
Output
I641–31AB9H2–155.520
Enable / Disable
(Pin 2)
Complimentary
Ouput (Pin 5) **
3 = 3.3V
1 = 0 C to +70 C
F = 20
B =  50
3 = LVCMOS
H = Enable
1 = N.C.
6 = 2.5V
3 = -20 C to +70 C
A = 25
C = 100
8 = LVDS
O = N/C
2 = Output
2 = -40 C to +85 C
B = 50
9 = LVPECL
Frequency
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between VDD (pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only.
ILSI America Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: [email protected] • www.ilsiamerica.com
11/05/13_D
Specifications subject to change without notice
Page 1
3.2 mm x 5.0 mm Ceramic Low Noise SMD VCXO
LVCMOS/LVPECL/LVDS
I641 - Series
SSB Phase Noise (typ.)
Offset
10Hz
100Hz
1kHz
10kHz
100kHz
77.76 MHz
155.52 MHz
622.08 MHz
-75 dBc/Hz
-105 dBc/Hz
-117 dBc/Hz
-123 dBc/Hz
-125 dBc/Hz
-62 dBc/Hz
-101 dBc/Hz
-112 dBc/Hz
-115 dBc/Hz
-118 dBc/Hz
-47 dBc/Hz
-79 dBc/Hz
-100 dBc/Hz
-104 dBc/Hz
-106 dBc/Hz
Typical Application:
Pb Free Solder Reflow Profile:
*Units are backward compatible with 240C reflow processes
Package Information:
MSL = N.A. (package does not contain plastic, storage life is
unlimited under normal room conditions).
Termination = e4 (Au over Ni over W base metalization).
ILSI America Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: [email protected] • www.ilsiamerica.com
11/05/13_D
Specifications subject to change without notice
Page 2
3.2 mm x 5.0 mm Ceramic Low Noise SMD VCXO
LVCMOS/LVPECL/LVDS
I641 - Series
Tape and Reel Information:
Quantity per
Reel
A
B
C
D
E
F
1000
16 +/-.3
8 +/-.2
7.5 +/-.2
17.5 +/-1
50 / 60 / 80
180 / 250
Environmental Specifications
Thermal Shock
Moisture Resistance
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Hazardous Substance
Solderability
Terminal Strength
Gross Leak
Fine Leak
Solvent Resistance
MIL-STD-883, Method 1011, Condition A
MIL-STD-883, Method 1004
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2007, Condition A
J-STD-020C, Table 5-2 Pb-free devices (except 2 cycles max)
Pb-Free / RoHS / Green Compliant
JESD22-B102-D Method 2 (Preconditioning E)
MIL-STD-883, Method 2004, Test Condition D
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 1014, Condition A2, R1=2x10-8 atm cc/s
MIL-STD-202, Method 215
Marking
Line 1: ILSI and Date Code (YWW)
Line 2: Frequency
ILSI America Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: [email protected] • www.ilsiamerica.com
11/05/13_D
Specifications subject to change without notice
Page 3
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