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PM8851
1 A low-side gate driver with configurable asymmetric sink/source
Datasheet - production data
Description
The PM8851 device is a high frequency single
channel low-side MOSFET driver specifically
designed to work with digital power conversion
microcontrollers, such as the STMicroelectronics
STLUX™ family of products.
SOT23-6L
The PM8851 has complementary output pins to
differentiate sink and source driving with a current
capability of respectively 1 A and 0.8 A.
Features
 Low-side MOSFET driver
 1 A sink and 0.8 A source capability
 Complementary outputs for source and sink
driving
 Ext. reference for input threshold
 Wide supply voltage range (10 V ÷ 18 V)
 Input and output pull-down resistors
 Short propagation delays
 Input and output UVLO
 Wide operating temperature range:
-40 °C to 125 °C
 SOT23-6L package
The input levels of the driver are derived by the
voltage present at the IN_TH pin (between 2 V
and 5.5 V). This pin is typically connected at the
same voltage of the microcontroller supply
voltage.
The PM8851 includes both input and output pulldown resistors.
UVLO circuitry for input and output stages is
present preventing the IC from driving external
MOSFET in unsafe condition.
Table 1. Device summary
Order code
Option
Package
PM8851D
Low input threshold
SOT23-6L
Applications
 SMPS
 Digital lighting
 Wireless battery chargers
 Digitally controlled MOSFETs
October 2014
This is information on a product in full production.
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www.st.com
Block diagram
1
PM8851
Block diagram
Figure 1. Block diagram
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PM8851
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65&
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PM8851
2
Pin connection
Pin connection
Figure 2. Pin connection
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Table 2. Pinning
Symbol
Pin
Description
VCC
1
IC power supply. A voltage comprised between 10 V and 18 V can be connected
between this pin and GND to supply the IC.
GND
2
Reference voltage connection.
IN
3
Digital input signal for driver.
It is internally pulled down to GND with a 100 k (typ.) equivalent resistor.
IN_TH
4
Input for IN pin's threshold definition: a voltage can be applied obtaining the
values for VIH and VIL.
SNK
5
MOSFET gate drive sinking output controlled by the IN pin.
A pull-down equivalent resistor [100 k (typ.)] is present.
SRC
6
MOSFET gate drive sourcing output controlled by the IN pin.
A pull-down equivalent resistor [100 k (typ.)] is present.
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Maximum ratings
3
PM8851
Maximum ratings
Table 3. Thermal data
Symbol
Parameter
Value
Unit
RthJA
Thermal resistance junction to ambient
(2-layer FR4 PCB, TA = 27 °C natural convection)
250
°C/W
RthJC
Thermal resistance junction to case
130
°C/W
TMAX
Maximum junction temperature
150
°C
TSTG
Storage temperature range
-40 to 150
°C
TJ
Junction temperature range
-40 to 150
°C
TA
Operating ambient temperature range
-40 to 125
°C
Table 4. Absolute maximum ratings
Symbol
Value
Unit
Note
19
V
IN unconnected, IN_TH = 3.3 V
- 0.3
V
5.5
V
- 0.3
V
5.5
V
Max. negative allowed voltage
- 0.3
V
ISRC,rms
Maximum RMS output current
40
mA
ISNK,rms
Maximum RMS output current
60
mA
VVCC,max
VIN_TH,max
VIN,max
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Parameter
Maximum IC supply voltage
Max. negative allowed voltage
Max. positive voltage at IN_TH pin
Max. negative allowed voltage
Maximum voltage at IN pin
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PM8851
4
Electrical characteristics
Electrical characteristics
(VCC = 12 V, VIN_TH = 3.3 V, TJ = - 40 ÷ 125 °C, unless otherwise specified).
Table 5. Electrical characteristics
Symbol
Pin
Parameter
Test condition
Min. Typ. Max. Unit
IC SUPPLY
VCC
VCC
Operating range
10
18
V
VCC,on
VCC
Turn-on threshold
9
10
11
V
VUVLO,hyst
VCC
UVLO hysteresis
0.5
1
IST-UP
VCC
Start-up current
VCC = VCC,on - 0.5 V
40
µA
ICC,0
VCC
Static supply current
IN = 0 V
40
µA
ICC,op
VCC
Operating supply current
See Figure 4 and Figure 5
5.5
V
V
IN_TH
VIN_TH
IN_TH Operating range
2
VIN_TH,UV IN_TH IN_TH UVLO
IIN_TH
IN_TH IN_TH pin bias
IN_TH short with IN, rising edge
1.5
current(1)
V
40
µA
INPUT
VIH/VIN_TH
IN
Relative input high level threshold (2)
36
58
%
VIL/VIN_TH
IN
Relative input low level threshold
(2)
25
46
%
VIN_Hyst
IN
Hysteresis
7
25
%
IIN
IN
IN pin bias current
VIN = 5 V
50
µA
RINPD
IN
Input pull-down resistance
VIN = VIN_TH
100
k
TD_LH
IN
IN to GD propagation delay
IN low to high, no load
30
ns
TD_HL
IN
IN to GD propagation delay
IN high to low, no load
30
ns
OUTPUT
VSRC,H
SRC
SRC pin high level (when invoked Isrc = 100 mA, TJ = 25°C
by IN pin)
Isrc = 100 mA, TJ =- 40 ÷ 125 °C(1)
VSNK,L
SNK
SRC pin low level (when invoked
by IN pin)
current(1)
Isnk =100 mA, TJ = 25°C
11.4
V
11.4
0.53
(1)
V
Isnk =100 mA, TJ =- 40 ÷ 125 °C
0.53
VSRC = VCC / 2
940
mA
1.1
A
ISRC
SRC
Source
ISNK
SNK
Sink current(1)
VSNK = VCC / 2
tR
SRC
Rise time
COUT = 470 pF
20
ns
tF
SNK
Fall time
COUT = 470 pF
20
ns
RGPD
SRC
SNK
Pull-down resistor
100
k
1. Not tested in production.
2. Overlapping prevent by hysteresis VIN_Hyst.
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Electrical characteristics
PM8851
Figure 3. Timings
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7'B/+
Figure 4. Operating supply current (no load)
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7'B+/
Figure 5. Operating supply current
(COUT = 470 pF)
Figure 6. VCC power dissipation (PD) when no load is applied
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PM8851
5
Typical applications
Typical applications
Figure 7. Test circuit
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Figure 8. Digitally controlled PFC boost converter
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Typical applications
PM8851
Figure 9. Digitally controlled flyback converter
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Figure 10. Digitally controlled inverse buck converter (e.g.: LED controller)
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PM8851
Application guidelines
6
Application guidelines
6.1
Power supply
The PM8851 driver is intended to drive power MOSFETs used in power conversion
topologies at high speed. The accurate supply voltage definition guarantees an effective
driving in every condition. The voltage present at the IN_TH pin is used for the threshold
definition. It could be the same voltage used to supply the device providing the signal
applied to the IN pin, or it can be derived by the VCC pin, eventually using a voltage divider.
It is mainly suggested to provide IN_TH voltage starting from VCC voltage.
For example, an auxiliary, unregulated voltage can be used to be connected to both
PM8851 VCC pin and the input of a linear regulator that provides a well regulated supply
voltage for logic circuitry. The same low voltage is then provided to the IN_TH pin of the
PM8851.
If the IN_TH is derived directly by the VCC pin, the structure illustrated in Figure 12 can be
used.
Figure 11. Shared supply configuration
Figure 12. Independent supply configuration
It is mandatory to properly connect a 100 nF ceramic cap as close as possible to the VCC
pin to bypass the current's spikes absorbed by VCC during the gate charging.
Also IN_TH voltage should be filtered with a ceramic capacitor (10 nF to 100 nF), especially
when long traces are used to supply it; when derived by VCC a lighter filtering is allowed.
6.2
Layout suggestions
The small package of the PM8851 allows to place it very close to the gate of the driven
MOSFET: this reduces the risk of injecting high frequency noise produced by the driving
current running between the OUT pin and the MOSFET's gate pin.
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Application guidelines
6.3
PM8851
Driving switches
The IN pin truth table is reported in Table 6.
Table 6. PM8851 truth table (levels refer to unloaded condition of SNK and SRC)
PM8851
IN
SRC
SNK
High
Vcc
Hi-Z
Low
Hi-Z
GND
Differential MOSFET's driving strength is seldom necessary in topologies such as flybacks
or boost controlled in the peak current mode. A lower driving current is used to turn-on the
MOSFET in order to reduce the EMI produced by the Miller capacitance activation, while
a stronger turn-off action is suggested to minimize the turn-off delay and, consequently the
deviation between theoretical and practical behaviors.
The same asymmetrical driving strength is required when the IGBT switch is used: in fact
the driving strength control is mandatory to avoid latch-up phenomena intrinsically related
with this kind of the switch. The asymmetrical driving can be realized using different values
for the resistances placed between the MOSFET's gate and the SRC and SNK pins.
When low switching frequencies are required and propagation delays can be compensated,
it is possible to drive contemporary the IN pin and the IN_TH pin to exploit the relevant
UVLO threshold of the device (typ. 1.5 V) using the PM8851 as a fixed threshold device
without any external component: care has to be taken to consider additional propagation
delay (typ. 300 ns) after the falling edge of the input signal.
6.4
Power dissipation
Overall power dissipation can be evaluated considering two main contributions: the device
related consumption (PD) and the gate driving power demand (PG):
Equation 1
PTot = PD + PG
The device power consumption can be found in Figure 6 on page 6, it represents the power
required by the device to supply internal structures and pull-downs resistors.
The gate driving power dissipation is the power required to deliver to and from the
MOSFET's gate the required gate charge:
Equation 2
PG = Qg x Vgs x fsw
The Qg value can be found depicted into the MOSFET's datasheet for any applied Vgs: Vgs
can be considered equal to VCC.
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7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
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Package information
PM8851
Figure 13. SOT23-6L package outline
627/
Table 7. SOT23-6L package mechanical data
Dimensions(1)
Symbol
mm
Min.
inch
Typ.
Max.
A
0.9
A1
Typ.
Max.
1.45
0.035
0.057
0
0.1
0
0.0039
A2
0.9
1.3
0.035
0.0512
b
0.35
0.5
0.014
0.02
c
0.09
0.2
0.004
0.008
D
2.8
3.05
0.11
0.120
E
1.5
1.75
0.059
0.0689
e
0.95
0.037
H
2.6
3
0.102
0.118
L
0.1
0.6
0.004
0.024
 (degrees)
0°
10°
0°
10°
1. Dimensions per JEDEC MO178AB.
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Min.
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PM8851
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Revision history
Revision history
Table 8. Document revision history
Date
Revision
23-Oct-2014
1
Changes
Initial release.
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PM8851
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