CR0021: SmartFusion2 SoC FPGA SERDES Characterization Report

SmartFusion2 SoC
FPGA SERDES
CR0021 Characterization Report
Table of Contents
I.
Introduction ...............................................................................................................................................3
A.
Overview of SmartFusion2 SoC FPGAs ............................................................................................3
B.
Scope of this Report ..........................................................................................................................3
II.
PCISIG Compliance Testing .....................................................................................................................3
Compliance Testing .......................................................................................................................................3
A.
Electrical Testing................................................................................................................................4
B.
Configuration Space Testing ..............................................................................................................4
C.
Link and Transaction Protocol Testing ...............................................................................................5
D.
Interoperability ...................................................................................................................................6
IIl.
Microsemi Test Boards ..........................................................................................................................6
A.
Signal Integrity Board (SI) ..................................................................................................................6
B.
PCIe Validation Board (PV) ...............................................................................................................7
IV.
Device Testing .......................................................................................................................................7
A.
CV Testing .........................................................................................................................................7
Description of Test.....................................................................................................................................7
Results ......................................................................................................................................................8
B.
PTC Testing .......................................................................................................................................9
Description of Test.....................................................................................................................................9
Results ......................................................................................................................................................9
LeCroy PTC Results ................................................................................................................................11
C.
Electrical Testing..............................................................................................................................12
D.
Electrical Testing Equipment/Software ............................................................................................12
E.
Electrical Testing Environment.........................................................................................................13
F. Testing Conditions ...............................................................................................................................13
G.
Transmit Compliance Testing ..........................................................................................................13
PCI Express Transmitter Setup ...............................................................................................................13
Results ....................................................................................................................................................15
H.
PLL Loop Bandwidth Testing ...........................................................................................................18
l.
PCI Express Receiver Testing .............................................................................................................20
V. Interoperability Results ............................................................................................................................22
Vl.
Conclusion ...........................................................................................................................................22
List of Changes ................................................................................................................................................23
2
I.
Introduction
A.
Overview of SmartFusion2 SoC FPGAs
B.
Scope of this Report
The Microsemi SmartFusion®2 SoC FPGA family provides a fully embedded PCI Express® Gen1/2x1/x2/x4 Endpoint. This embedded PCI Express solution is part of the SERDESIF module which supports
4 lanes of SERDES with data rates supported up to 5Gbps. The number of SERDESIF modules on the
SmartFusion2 SoC FPGA depends on the device size. The smaller devices support a single SERDESIF
with a single PCI Express interface. The larger devices support up to 4 SERDESIF modules for a total of
4 PCI Express interfaces. More information on the SmartFusion2 SoC FPGA family can be found on the
Product Page at www.microsemi.com\smartfusion2.
Complete testing and validation of specifications required by Gen 1 and Gen 2 PCI Express standards
were conducted on the SmartFusion2 SoC FPGA device. This report provides the user community a
summary of both PCIe related device testing and characterization as well as results of the compliance
testing conducted at PCISIG testing workshops. Comprehensive testing was done to characterize the
PCIe electrical performance of the device. The testing analyzed voltage, temperature, and process
variations for specific PCIe parameters and higher level testing was conducted to verify link and protocol
functionality of the SmartFusion2 PCIe solution. This report serves as a reference to the specific testing
used to provide high confidence that the devices will perform as expected in PCI Express systems.
II.
PCISIG Compliance Testing
PCISIG is the industry organization chartered to develop and manage the PCI standards. The PCISIG
Compliance Program offers the latest in PCI device testing, including the opportunity to test your system
or Add-in Card with other members' PCI products. Completing testing at the PCISIG Compliance
Workshop will enable devices to be added to the PCISIG Integrators Listing.
A traditional PCI Express system utilizes a CPU connected to a root device, which is responsible for
configuring and enumerating all PCI Express Endpoint devices within the system. A point-to-point PCIe
system requires a switch device to grow the number of Endpoint devices present with one root and one or
more Endpoint devices. An FPGA-based Endpoint provides a high level of integration enabling highperformance, fully compliant PCI Express systems in a single device. The use of the FPGA-based
Endpoint Add-in Cards have become the “de-facto” means for testing PCIe Gen 1 and 2 standards at PCI
Express workshops.
PCI Express Endpoint Add-in Cards developed by Microsemi, provide the physical capabilities to test
devices at the compliance workshop. A standardized interface of the printed circuit boards is utilized to
test the device performance and to exercise the IP used to implement the PCI Express functionality. The
boards are tested for electrical compliance, subjected to link and transaction protocol tests, and checked
for proper configuration space implementation. Participants pass or fail at the compliance workshop by
attending testing sessions.
Compliance Testing
There are four encompassing areas of PCI Express compliance testing for components tested on Add-in
Cards:

Electrical Testing—Examines device and Add-in Card signal quality for eye pattern, jitter, and
2.5/5Gbps data rate analysis.

Configuration Space Testing (CV)—Examines configuration space in PCI Express devices by
verification of required fields and values.
SmartFusion2 SERDES Characterization Report
3

Link and Transaction Protocol Testing (PTC)—Tests device behavior for link-level protocol and
device behavior for transaction-level protocol. Link and transaction layers are exercised for protocol
boundary conditions. Tests include error injection and check error-handling capabilities.

Interoperability Testing—Tests conducted between workshop participants that show compatibility
between PCI Express technologies.
These tests were all conducted and validated by Microsemi. PCIe compliance was verified at a test
compliance workshop held by the PCISIG.
A.
Electrical Testing
PCI Express Electrical Testing was developed to verify product-level physical compliance to the PCI
Express CEM Specification(s). PCI Express Electrical Testing consists of a series of tests used to
evaluate PCI Express products. A series of tests were performed on Microsemi boards in conjunction with
the PCISIG compliance base board (CBB) and the compliance load board (CLB) to validate signal quality
of TX, Ref Clock, and PLL Loop Bandwidth.
Figure 1. PCIe Compliance Test Channel
Once data is collected from the test platforms, analysis software is used on the collected information
determining whether the device meets specifications.
The test criteria are specified in the PCI Express Architecture PHY Electrical Test Considerations
Revision 2.0*.
PCIE Gen1 and Gen2 electrical tests conform to section 4.3 of the
PCI_Express_Base_r2_1_04March09.pdf* and the PCI_Express_CEM_r2.0.pdf*.
B.
Configuration Space Testing
The PCI Express Configuration Verifier (CV) test is a software application provided by PCISIG that runs on
a Windows 7 32-bit PC and exercises access to the configuration space registers of the device under test.
Its purpose is to check for compliance with the PCIe specification for configuration space registers (type 1switch/bridge). A detailed description of tests performed can be found in the document PCI EXPRESS
ARCHITECTURE CONFIGURATION SPACE TEST SPECIFICATION, REV. 2.0*. The tests are conducted
with the Add-in Card placed in a PCI Express slot in the PC. The test software accesses the Add-in Card
and issues configuration read and write requests and checks for the correct response.
These specification documents are only available to PCISIG members at: http://www.pcisig.com/specifications/pciexpress.
*
4
The tests check the following:
 Configuration space registers can be read
 Read-only registers retain their value when attempted to be written to
 Writable registers can be written to
 Registers have the correct default value after reset
 Capabilities lists are valid and correctly linked
 PCI Express 2.0, 1.1, and/or 1.0a specific fields and capabilities are present
The test program also performs functional stress tests to ensure the Endpoint can re-train and re-link in an
acceptable amount of time. It also tests to make sure the card can properly handle hundreds of cycles of
link-up/link-down and all registers are operational (such as the Endpoint firmware has not locked up). In
summary, the CV test suite verifies that the PCI Express Endpoint is truly functional in a PC and covers all
aspects of hardware and operating system interaction. It shows that the card can be recognized by the
PCI Express hardware and can be enumerated and configured by the operating system for access by
software applications.
C.
Link and Transaction Protocol Testing
The PCI Express Link and Transaction Layer protocol testing was developed to test the Add-in Card
compliance to the Link and Transaction protocol specification requirements. The testing utilizes the
E2969B Protocol Test Card 2 (PTC-2) and the test code from Agilent Technologies or the Teledyne
LeCroy Protocol Test Card. Both PTC cards exercise all required tests that the PCISIG will conduct
during its compliance workshops by using this Agilent hardware. The PTC-2 exercises specifications for
the Transaction Layer and the Data Link Layer, and monitors the behavior of the device in response to
certain error conditions. The PTC card is simply attached to the PCI Express Add-in Card under test and
performs all mandatory tests from the PCISIG.
Figure 2. Agilent PTC-2
These vendors test packages contain PTC test code that is compatible with, and requires any of the
Agilent E2960B or LeCroy PTCG2 family software packages, available on the Agilent or LeCroy websites
free of charge. During link testing, the following tests are run using the PTC card. All of the following tests
must be passed in order to be included on the Integrators List.
SmartFusion2 SERDES Characterization Report
5
Table 1.
Link Tests Using PTC Card
Bad CRC
Device detects, drops, and logs (DLLPs and TLPs)
Bad Sequence Number
Device detects, drops, and logs
Duplicate TLP
Device returns data once
Link Retrain
Device will retrain if continued no response
NAK Response
Device will resend after receiving NAK
Replay Count
Device will resend multiple times when no response
Replay Timers
Device will resend packet if no response
Replay TLP Order
Device replays TLPs in proper order
Reserved Fields
Device ignores reserved fields
Undefined Packet
Device ignores undefined packets
D.
Interoperability
The interoperability test sessions are used to show consistent functionality between PCI Express
component vendors. During these sessions, the participants set their own test procedures and must
agree on what comprises a pass or a fail. Participants are expected to demonstrate some degree of
functionality to substantiate that their interface is functional with another vendor’s products.
The PCISIG recognizes that participants may bring designs that are not fully compliant or have unknown
or undisclosed bugs. For this reason, to pass the interoperability tests vendors must only demonstrate a
success rate of 80%. If they have passed 100% of the PCISIG mandatory tests (Gold Tests) and 80%
interoperability, the device is eligible to be included on the Integrators List. The Integrators List is proof a
product has passed the rigorous PCISIG tests and has demonstrated interoperability with others. This
status implies that the device is viable for use in PCI Express systems.
IIl.
Microsemi Test Boards
Testing is performed on two types of boards which are dependent on the test requirements. Both boards
are equipped with a test socket which accommodates testing a variety of parts. The socket slightly
contributes to attenuation and jitter, which will slightly degrade the testing results although the design of
the boards minimizes this effect.
A.
Signal Integrity Board (SI)
The SI board is equipped with a test socket and provides connections to vary power supply conditions. To
ensure the integrity of the characterization measurements, special attention is given to the signal integrity
of the high-speed serial channels. Detailed analysis ensures the board performs as designed. The
transmitter (TX) and receiver (RX) signal paths for each SERDES are carefully routed to high-bandwidth
SMP connectors to ensure good signal integrity and performance. The PCB channel is measured and deembedded when performing tests.
6
Figure 3. SmartFusion2 Signal Integrity Board
B.
PCIe Validation Board (PV)
The PV board is built specifically with PCIe-defined edge fingers. This PCIe validation board provides the
capability to perform detailed PCIe testing on protocol analyzers and standardized PCIe testers. It also
provides an accurate channel representative specified for PCIe Add-on boards. This board has PCIe
edge fingers that will interconnect to PCIe sockets of PC motherboards. This interface allows for
interoperation and evaluations in PCIe systems or industry standard test fixtures and test equipment.
Figure 4. SmartFusion2 Validation Board
IV.
Device Testing
A.
CV Testing
Description of Test
PCIeCV requires installation of software provided to members of the PCISIG group. The testing involves
installation of the PCIe validation board into a PCIe slot on a host PC with the testing software installed.
The PCIe validation board requires a separate power supply from the PC PCIe slot. The standalone
testing will exercise all specific testing as required by the PCISIG configuration verification specification.
Refer to PCIECV 2.0 Configuration User Guide (2/25/2013)*.
These specification documents are only available to PCISIG members at: http://www.pcisig.com/specifications/pciexpress.
*
SmartFusion2 SERDES Characterization Report
7
Results
Configuration Testing
===================
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
8
PCIeCVApp.exe ver 1.5.1.9
DriverInterfaceDLL.dll ver 1.4.7.0
ttpi.dll ver 1.4.9.0
Max Bus Number value: 50
Beginning PCIeCV Test
TEST OPTION SELECTED: Test against 2.0 Spec Only
Virtual Function Detection Disabled.
Test Endpoint was Selected.
Device selected: Vendor ID= 11aa, Device ID= 0846
Bus number= 0001, Device Number= 0000, Function= 0000
Link Enable-Disable chosen as default reset type.
Running the test at the maximum supported speed.
Run All Tests Selected
Link Width chosen:x4.
TD_1_2_PCIExpressCapabilityStructureTest : PASSED
TD_1_3_PCIExpressCapabilitiesRegisterTest : PASSED
TD_1_4_DevCapControlStatusReg : PASSED
TD_1_5_LinkCapControlStatusReg : PASSED
TD_1_6_MSICapabilityStructureTest : PASSED
TD_1_7_AdvancedErrorReportingCap : PASSED
TD_1_8_VirtualChannelCap : PASSED
TD_1_11_CommandStatusRegTest : PASSED
TD_1_12_CacheLnSzMasterLatTimerMinGntMaxLatReg : PASSED
TD_1_13_InterruptPinInterruptLine : PASSED
TD_1_16_PowerManagementCap : PASSED
TD_1_18_BaseAddressRegistersTest : PASSED
TD_1_21_BISTRegisterTest : PASSED
TD_1_23_PCINextCapabilityPointerTest : PASSED
TD_1_24_PCIeNextEnhancedCapabilityPointerTest : PASSED
TD_1_25_MiscType_0_ConfigSpaceHeaderRegTest : PASSED
TD_1_27_Multi-FunctionTest : PASSED
TD_1_32_PCIXCapabilityStructureTest : PASSED
TD_1_39_MultiFunctionFLRTest : PASSED
TD_1_40_DevCap2Control2Status2Reg : PASSED
TD_1_41_LinkCap2Control2Status2Reg : PASSED
TD_1_42_ACSExtendedCapabilityStructureTest : PASSED
TD_1_50_SlotCap2Control2andStatus2RegTest : PASSED
TD_2_1_ConfigurationStressTest : PASSED
TD_2_2_LinkTrainingStressTest : PASSED
TD_2_3_ResponseToControlMessagesTest : PASSED
TD_2_4_ResponseToEarliestConfig : PASSED
TD_2_7_LinkSpeedTest : PASSED
TD_2_8_SupportedLinkWidthTest : PASSED
Test Summary
Total Number of Tests Run: 29
Number of Tests Passed: 29
Functional Testing
===================
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
INFO
PCIeCVApp.exe ver 1.5.1.9
DriverInterfaceDLL.dll ver 1.4.7.0
ttpi.dll ver 1.4.9.0
Max Bus Number value: 50
Beginning PCIeCV Test.
TEST OPTION SELECTED: Test against 2.0 Spec Only
Virtual Function Detection Disabled.
Test Endpoint was Selected..
Device selected: Vendor ID= 11aa, Device ID= 0846
Bus number= 0001, Device Number= 0000, Function= 0000
INFO Link Enable-Disable chosen as default reset type.
INFO Running the test at the maximum supported speed.
INFO Link Width chosen:x4.
INFO Beginning Functional Tests
Time from reset to first command: 250
INFO Upstream ASPM State Support: 3
INFO PCI Express Device ASPM State Support: 3
INFO TD_2_1 Configuration Stress Test Selected.
Device State : D0 - Uninitialized.
INFO TD_2_1_ConfigurationStressTest : PASSED
INFO TD_2_2_LinkTrainingStressTest : PASSED
INFO TD_2_3_ResponseToControlMessagesTest : PASSED
INFO TD_2_4_ResponseToEarliestConfig : PASSED
INFO TD_2_7_LinkSpeedTest : PASSED
INFO TD_2_8_SupportedLinkWidthTest : PASSED
INFO Test Summary
Total Number of Tests Run: 6
Number of Tests Passed: 6
Number of Tests Failed: 0
B.
PTC Testing
Description of Test
The PCIe validation board is installed and connected to the Agilent PTC2 (E2969B) exerciser. The PTC2
and the PCIe validation board require separate power supplies. The PTC2 is connected by the USB port
to the controller PC, which has the PTC software installed. The card must be in PTC mode to perform the
correct add-in tests on the PCIe validation board. Refer to the Test Procedure for Agilent Gen 2 PTC for
the C. Link and Transaction Protocol Testing section.
Results
This section includes example screenshots of the PTC test results.
SmartFusion2 SERDES Characterization Report
9
Figure 5. Gen 1 Agilent PTC Results
Figure 6. Gen 2 Agilent PTC Results
10
LeCroy PTC Results
Table 2.
Add-in Card Checklist – TXN TESTS
Test
TXN Request
Completion
Description
Result
Test 1.1 (TXN.2.7#9, TXN.2.21#15, TXN.2.21#19, TXN.3.1#1, TXN.3.1#2): Verify Basic
Request and Completion handling of slotted Endpoint devices.
Table 3.
Pass
Add-in Card Checklist – LINK TESTS
Test
Description
Result
DLL WrongSeqNum
Test 52-170 (DLL.5.2#17): The intent of this test is to verify that the DUT drops any
ACK DLLP that doesn't have a sequence number corresponding to an
unacknowledged TLP and logs a BAD DLLP error associated with the port.
Pass
DLLP BadCRC
Test 52-150 (DLL.5.2#15): The intent of this test is to ensure that a DUT recognizes a
DLLP with bad CRC, drops it and logs a BAD_DLLP port error.
Pass
DLLP ReservedFields
Test 41-20 (DLL.4.1#2): The intent of this test is to verify that the DUT truly ignores
reserved fields in an ACK DLLP by sending arbitrary data in those fields.
Pass
DLLP
UndefinedEncoding
Test 52-160 (DLL.5.2#16): The intent of this test is to verify that the DUT silently drops
any DLLP with undefined encoding (any pattern for DLLP type that is reserved right
now) and no error is associated with it.
Pass
LinkRecoveryRetryFail
Test 52-20 (DLL.5.2#2, DLL.5.2#7): The intent of this test is to ensure that the link
connected to the DUT will go into retraining after trying for REPLAY_NUM of times to
get a TLP through and failing. It will also test that while in retraining the retry buffer and
link states are not changed and the pending TLP is retransmitted after link retraining
completes.
Pass
LinkRecoveryRetryFail
No Ack Nak
Test 52-20 (DLL.5.2#2, DLL.5.2#7): The intent of this test is to ensure that the link
connected to the DUT will go into retraining after trying for REPLAY_NUM of times to
get a TLP through and failing. It will also test that while in retraining the retry buffer and
link states are not changed and the pending TLP is retransmitted after link retraining
completes.
Pass
ReplayNum
Test 52-12 (DLL.5.2#1.1): The intent of this test is to ensure that a DUT will keep
retransmitting a transaction for which a NAK has been issued on purpose until the
number of times its REPLAY_NUM supports.
Pass
ReplayTimer
Test 52-11 (DLL.5.2#1.1): The intent of this test is to ensure that a DUT's
REPLAY_TIMER is working properly by not sending neither an ACK nor a NAK.
Pass
ReXmitOnNak
Test 52-10 (DLL.5.2#1): The intent of this test is to ensure that a DUT will retransmit a
transaction for which a NAK has been issued.
Pass
TLP BadLCRC(32bit)
Test 53-20 (DLL.5.3#2): The intent of this test is to verify that a receiver discards a
TLP with bad CRC by NAKing it and reports a BAD TLP error associated with the port.
Pass
TLP
DuplicateSeqNum
Test 53-31 (DLL.5.3#3.1): The intent of this test is to verify that the duplicate (TLP with
the same sequence number associated at the link layer as that in the last 2048 TLPs
received) TLPs are handled properly by the DUT.
Pass
TLP ReplayOrder
Test 52-100 (DLL.5.2#10): The intent of this test is to verify that the oldest
unacknowledged TLP is retransmitted first in replay followed by the other
unacknowledged TLPs in the same order they were transmitted first.
Pass
Table 4.
Add-in Card Checklist – TRAINING TESTS
Test
ReservedBitsInTrainingSequences
Description
The intent of this test is to verify that the DUT truly ignores reserved fields in
Training Sequences (TS1 and TS2).
SmartFusion2 SERDES Characterization Report
Result
Pass
11
C.
Electrical Testing
PCI Express I/O electrical characterization testing was completed by Microsemi over device process,
voltage, and temperature variations (PVT). Testing was conducted on a sample of devices representing
process fluctuations across silicon fabrication. These devices were separated from a large sample and
represented the worse-case corners to report the results. The results are correlated and presented in the
data as worst-case. The testing procedures verify the device can achieve critical specification targets
such as:
 Jitter
 Eye mask
 Different De-emphasis levels
 Reference Clock
 Voltage and Jitter margining
 Receiver Margining
All the PCIe electrical characterization tests were conducted for the clocks configuration (below):
1- PCI Express Transmitter testing RefClk was externally generated by an on-board oscillator on
the PCISIG, PCIe CBB Compliance Board
2- PCI Express Receiver and PLL testing RefClk were externally generated by a signal generator
and connected thru SMA’s
The characterization was performed in accordance with PCI Express CEM specification that requires the
Add-In Card be plugged into the PCISIG PCI Express compliance baseboard (CBB2) to perform PCIe
measurements. The PCI Express CEM compliant test setup consists of a necessary compliance channel
(Edge Finger Connector of an Add-In Card with 2” to 3” of trace to the silicon device, the PCI Express
connector itself, and 2.5” to 3” of trace to the SMP connector). Device electrical tests were conducted on
the signal integrity board, which has high-speed SMP connectors for bringing signals on and off the
board. To build a necessary PCIe compliance channel per the PCIe CEM specification with the signal
integrity board, a special setup was assembled. The setup uses the PCISIG compliance load board
(CLB2) mated with a compliance baseboard (CBB2). This setup closely matches the correct PCIe
channel as it is present between the device under test on the signal integrity board and the test
equipment.
Testing was also conducted with the PCIe validation board. In this setup, the CBB provides the physical
means to connect the validation board to the test equipment and provides the required PCIe Add-in Card
channel. This test setup was used to provide a test platform at the PCISIG compliance workshop.
D.
Electrical Testing Equipment/Software
 Agilent DSA91304A, 13GHz Real Time Scope or DSO93204A 32Ghz Real Time Scope
- Agilent N5393C PCI Express Automation Test Application, Version 02.24 or newer
- PCIe SIGTST 3.1.9 or newer
 BitifEye N5990A Test Automation Software Platform
- PCI Express2 Application, Version 1.11.20101207 or newer
 Agilent J-BERT N4903B with A02 Option License
 Agilent N4916A De-Emphasis Signal Converter
 Agilent N6701A Power Supply Mainframe
- Four individually controlled P/S Modules
 BertScope CR12500A, Clock Recovery Module and PLL Bandwidth S/W Application
 Silicon Thermal, Temperature Control Unit
12
- Silicon Thermal Chiller CH400
- Silicon Thermal Linear Power Supply PS190-L
- Silicon Thermal Temperature Controller LB190-L
- Silicon Thermal Head Adapter
 SMA-to-SMA cables
 SMA-to-SMP cables
 PCISIG, Compliance Base Board2 (CBB2) Fixture
 PCISIG, Compliance Load Board2 (CLB2) Fixture
E.
Electrical Testing Environment
Device electrical testing was conducted by Microsemi using variations on power supply voltages and
temperatures. Minimum voltage (Vmin) and maximum voltage (Vmax) were varied by +/-5% of the typical
voltage (Vtyp) supply for the supplies related to the PCIe blocks of the device. The devices were also
tested at the industrial temperature limits (-40°C to +125°C).
F.
Testing Conditions
Table 5.
Voltage and Temperature Matrix
Voltage Dependencies
1.2 V VDD Device Range
xDDR_PLL_VDDA
3.15 V
3.3 V
3.45 V
3.15 V
3.3 V
3.45 V
CCC_xyz_PLL_VDDA
2.375 V
2.5 V
2.625 V
3.15 V
3.3 V
3.45 V
SERDES_x_PLL_VDDA
2.375 V
2.5 V
2.625 V
3.15 V
3.3 V
3.45 V
SERDES_x_L[0:3]VDDAPLL
2.375 V
2.5 V
2.625 V
2.375 V
2.5 V
2.625 V
SERDES_x_L[0:3]VDDAIO
1.14 V
1.2 V
1.26 V
1.14 V
1.2 V
1.26 V
SERDES_x_VDD
1.14 V
1.2 V
1.26 V
1.14 V
1.2 V
1.26 V
VDD (Core Supply)
1.14 V
1.2 V
1.26 V
1.14 V
1.2 V
1.26 V
Temperature
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
0°C
0°C
0°C
0°C
0°C
0°C
25°C
25°C
25°C
25°C
25°C
25°C
85°C
85°C
85°C
85°C
85°C
85°C
100°C
100°C
100°C
100°C
100°C
100°C
G.
Transmit Compliance Testing
PCI Express Transmitter Setup
The PCIe specification requires a transmitter to send a defined compliance pattern. This compliance
pattern is continually sent when not connected to a link partner, since an exit response from electrical idle
is never detected. See the PCI Express specification for full details on the electrical compliance pattern.
With this pattern, a series of tests are conducted to analyze the quality of the transmitter data eye. The
testing produces direct and indirect measured data that is correlated to the PCIe specifications. Refer to
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 2.0* for detailed procedures.
These specification documents are only available to PCISIG members at: http://www.pcisig.com/specifications/pciexpress.
*
SmartFusion2 SERDES Characterization Report
13
Figure 7. Transmitter Test Setup
14
Results
Table 6.
Tx Compliance
test
parameters
Transmitter Compliance Test Results – Gen 1
100°C
85°C
0°C
-40°C
25°C
100°C
85°C
0°C
-40°C
Vmin
Vmin
Vmin
Vmin
Vtyp
Vmax
Vmax
Vmax
Vmax
PT7/
TC101
PT7/
TC102
PT7/
TC104
PT7/
TC105
PT7/
TC124
PT7/
TC80
PT7/
TC81
PT7/
TC83
PT7/
TC84
Units
SPEC
Add-in Card Tx,
Unit Interval
(PCIe 2.0, 2.5
GT/s)
400.03
400.03
400.03
400.03
400.03
400.03
400.03
400.03
400.03
ps
399.880
0 <=
VALUE
<=
400.120
0
Add-in Card Tx,
Median to Max
Jitter (PCIe 2.0,
2.5 GT/s)
19.68
19.95
20.83
22.25
18.71
17.04
18.43
18.26
17.25
ps
VALUE
<=
56.50
Add-in Card Tx,
Eye-Width
(PCIe 2.0, 2.5
GT/s)
355.92
354.90
355.02
353.01
358.41
361.24
359.08
360.19
359.33
ps
VALUE
>=
287.00
mV
360.0m
V <=
VALUE
<=
1.2000
V
mV
360.0m
V <=
VALUE
<=
1.2000
V
Add-in Card Tx,
Peak Differential
Output Voltage
(Transition)
(PCIe 2.0, 2.5
GT/s)
Add-in Card Tx,
Peak Differential
Output Voltage
(NonTransition)
(PCIe 2.0, 2.5
GT/s)
947.50
519.60
935.30
505.40
948.20
517.40
959.30
520.90
SmartFusion2 SERDES Characterization Report
988.60
544.80
1030.80
568.00
1031.90
557.50
1058.30
588.90
1063.30
580.20
15
Table 7.
Tx Compliance
test
parameters
Add-in Card Tx,
Peak Differential
Output Voltage 3.5dB (PCIe
2.0, 5.0 GT/s)
Transmitter Compliance Test Results – Gen 2 (- 3.5dB)
100°C
85°C
0°C
-40°C
25°C
100°C
85°C
0°C
-40°C
Vmin
Vmin
Vmin
Vmin
Vtyp
Vmax
Vmax
Vmax
Vmax
PT7/
TC101
PT7/
TC102
PT7/
TC104
PT7/
TC105
PT7/
TC124
PT7/
TC80
PT7/
TC81
PT7/
TC83
PT7/
TC84
Units
SPEC
902.30
909.80
910.20
914.30
943.70
992.40
990.10
1012.40
1028.30
mV
380.0m
V <=
VALUE
<=
1.2000
V
Add-in Card Tx,
Eye-Width 3.5dB with
crosstalk (PCIe
2.0, 5.0 GT/s)
145.26
147.13
145.10
143.53
148.07
152.51
153.96
152.06
152.81
ps
VALUE
>=
123.00
Add-in Card Tx,
RMS Random
Jitter -3.5dB
with crosstalk
(PCIe 2.0, 5.0
GT/s)
1.70
1.64
1.78
1.90
1.73
1.57
1.55
1.61
1.65
ps
VALUE
<=
20.000
Add-in Card Tx,
Maximum
Deterministic
Jitter -3.5dB
with crosstalk
(PCIe 2.0, 5.0
GT/s)
30.86
29.83
29.84
29.79
27.54
25.39
24.18
25.32
24.01
ps
VALUE
<=
57.000
Add-in Card Tx,
Total Jitter at
BER-12 -3.5dB
with crosstalk
(PCIe 2.0, 5.0
GT/s)
54.74
52.87
54.90
56.47
51.93
47.49
46.04
47.94
47.19
ps
VALUE
<=
77.000
Add-in Card Tx,
Eye-Width 3.5dB without
crosstalk (PCIe
2.0, 5.0 GT/s)
145.26
147.13
145.10
143.53
148.07
152.51
153.96
152.06
152.81
ps
VALUE
>=
126.00
Add-in Card Tx,
RMS Random
Jitter -3.5dB
without
crosstalk (PCIe
2.0, 5.0 GT/s)
1.70
1.64
1.78
1.90
1.73
1.57
1.55
1.61
1.65
ps
VALUE
<=
20.000
Add-in Card Tx,
Maximum
Deterministic
Jitter -3.5dB
without
crosstalk (PCIe
2.0, 5.0 GT/s)
30.86
29.83
29.84
29.79
27.54
25.39
24.18
25.32
24.01
ps
VALUE
<=
54.000
Add-in Card Tx,
Total Jitter at
BER-12 -3.5dB
without
crosstalk (PCIe
2.0, 5.0 GT/s)
54.74
52.87
54.90
56.47
51.93
47.49
46.04
47.94
47.19
ps
VALUE
<=
74.000
16
Table 8.
Tx Compliance
test
parameters
Add-in Card Tx,
Peak Differential
Output Voltage 6.0dB (PCIe
2.0, 5.0 GT/s)
Transmitter Compliance Test Results – Gen 2 (- 6.0 dB)
100°C
85°C
0°C
-40°C
25°C
100°C
85°C
0°C
-40°C
Vmin
Vmin
Vmin
Vmin
Vtyp
Vmax
Vmax
Vmax
Vmax
PT7/
TC101
PT7/
TC102
PT7/
TC104
PT7/
TC105
PT7/
TC124
PT7/
TC80
PT7/
TC81
PT7/
TC83
PT7/
TC84
Units
SPEC
909.80
915.50
930.40
929.80
965.60
1003.30
1009.70
1024.30
1035.70
mV
306.0mV
<=
VALUE
<=
1.2000V
Add-in Card Tx,
Eye-Width 6.0dB with
crosstalk (PCIe
2.0, 5.0 GT/s)
159.77
156.40
155.74
154.74
158.42
162.89
163.11
161.97
162.90
ps
VALUE
>=
123.00
Add-in Card Tx,
RMS Random
Jitter -6.0dB
with crosstalk
(PCIe 2.0, 5.0
GT/s)
1.60
1.71
1.72
1.85
1.72
1.54
1.55
1.59
1.60
ps
VALUE
<=
20.000
Add-in Card Tx,
Maximum
Deterministic
Jitter -6.0dB
with crosstalk
(PCIe 2.0, 5.0
GT/s)
17.70
19.61
20.11
19.24
17.37
15.41
15.04
15.65
14.56
ps
VALUE
<=
57.000
Add-in Card Tx,
Total Jitter at
BER-12 -6.0dB
with crosstalk
(PCIe 2.0, 5.0
GT/s)
40.23
43.60
44.26
45.26
41.58
37.11
36.89
38.03
37.10
ps
VALUE
<=
77.000
Add-in Card Tx,
Eye-Width 6.0dB without
crosstalk (PCIe
2.0, 5.0 GT/s)
159.77
156.40
155.74
154.74
158.42
162.89
163.11
161.97
162.90
ps
VALUE
>=
126.00
Add-in Card Tx,
RMS Random
Jitter -6.0dB
without
crosstalk (PCIe
2.0, 5.0 GT/s)
1.60
1.71
1.72
1.85
1.72
1.54
1.55
1.59
1.60
ps
VALUE
<=
20.000
Add-in Card Tx,
Maximum
Deterministic
Jitter -6.0dB
without
crosstalk (PCIe
2.0, 5.0 GT/s)
17.70
19.61
20.11
19.24
17.37
15.41
15.04
15.65
14.56
ps
VALUE
<=
54.000
Add-in Card Tx,
Total Jitter at
BER-12 -6.0dB
without
crosstalk (PCIe
2.0, 5.0 GT/s)
40.23
43.60
44.26
45.26
41.58
37.11
36.89
38.03
37.10
ps
VALUE
<=
74.000
SmartFusion2 SERDES Characterization Report
17
Figure 8. Transmitter Eye Diagrams
H.
PLL Loop Bandwidth Testing
PLL bandwidth and peaking parameters are specified for 2.5 and 5Gbps operations. The Rx jitter for
2.5Gbps is inherently defined within the minimum eye width. However, the parameters for 5Gbps
operation are separated for two-phase jitter frequency ranges. Each range specifies the allowable random
and deterministic jitter components. The PLL bandwidth when measured with compliance pattern must be
between 5 and 16 MHz if the peaking is less than 1 dB or must be between 8 and 16 MHz with a peaking
of less than 3 dB. For 2.5 Gbps, the 3 dB point must fall between 1.5 and 22 MHz with peaking less than 3
dB.
PCI Express PLL Bandwidth Setup
The same PCI Express CEM Compliance Channel is applied to PCI Express PLL Bandwidth testing. The
Ref CLK+/- is provided by the Tektronix CR125 Clock Recovery unit, and PCIe TX+/- lanes passing
through both boards are connected to DATA_IN+/- of the CR125 unit. The CR125 DATA_OUT+/- must be
terminated with 50 Ω terminators for M2S050-FG896 silicon to begin transmitting PCI Express
Compliance Patterns upon power-up.
18
Figure 9. PLL Bandwidth Test Setup
Table 9.
PLL Bandwith Specifications
Category
Bandwidth Spec
Peaking Spec
1.5 to 22 MHz
< 3.0 dB
PLL Bandwidth Gen 2 Spec A
5 MHz to 16 MHz
< 1.0 dB
PLL Bandwidth Gen 2 Spec B
8 MHz to 16 MHz
< 3.0 dB
PLL Bandwidth Gen 1
Results
Table 10.
PLL Bandwidth Testing Results
Peaking(dB)
Vmax
Bandwidth(MHz)
Vmax
Peaking(dB)
Vmax
Bandwidth(MHz)
Vmax
Peaking(dB)
Vtyp
Bandwidth(MHz)
Vmin
Peaking(dB)
Vmin
Bandwidth(MHz)
Vmin
Peaking(dB)
Vmin
Bandwidth(MHz)
-40°C
Peaking(dB)
0°C
Bandwidth(MHz)
85°C
Peaking(dB)
100°C
Bandwidth(MHz)
25°C
Peaking(dB)
-40°C
Bandwidth(MHz)
0°C
Peaking(dB)
85°C
Bandwidth(MHz)
100°C
Test
Corner/
Device
TC38
PT4
TC 3 9
PT4
TC 4 1
PT4
TC 4 2
PT4
TC 6 1
PT4
TC80
PT4
TC 8 1
PT4
TC 8 3
PT 4
TC84
PT4
Gen1
15.57
0.53
15.86
0. 52
17.23
0. 56
17.66
0. 61
16.69
0.59
15.32
0. 53
15.63
0. 55
16.91
0.60
17.37
0.60
Gen2
8.72
0.90
9. 51
0. 86
13.69
0. 76
15.41
0. 73
12.50
0.78
9.90
0. 89
10.33
0. 86
13.18
0.74
14.91
0.75
Conditions
SmartFusion2 SERDES Characterization Report
19
l.
PCI Express Receiver Testing
Receiver testing stresses the incoming signal to determine its robustness to operate in typical system
environments with a degree of noise and signal fluctuations. The test setup impairs the signal to the
receiver by adding jitter, and determines that it can run normally with a long-term bit error rate target of
-12
10 .
PCI Express Receiver Setup
The same PCI Express CEM Compliance Channel setup is used for the PCI Express Receiver testing.
The JBERT and De-emphasis Box are interconnected together to provide a necessary generator for the
PCI Express Receiver testing. The entire PCI Express CEM setup with an additional 7” of trace is
calibrated to provide PCI Express Compliant Stressed Eye at the RX package balls of the M2S050FG896 silicon under test. A 12 MHz CDR bandwidth was used to test the PCI Express Receiver Jitter
Tolerance testing and was limited to only 5Gbs during the Worst Case Condition Phase of
Characterization. The test equipment stresses the receiver by imposing sinusoidal noise, and monitors
the bit error rate of the system.
Figure 10. Receiver Test Setup
20
Table 11.
RX JTOL Compliance Tests (GEN1 & GEN 2)
100°C
85°C
0°C
-40°C
25°C
100°C
85°C
0°C
-40°C
Vmin
Vmin
Vmin
Vmin
Vtyp
Vmax
Vmax
Vmax
Vmax
Test Corner
TC115
TC116
TC118
TC119
TC138
TC94
TC95
TC97
TC98
BER Results
> 1e-13
> 1e-13
> 1e-13
> 1e-13
> 1e-13
> 1e-13
> 1e-13
> 1e-13
> 1e-13
Conditions
Rx_5GTps_Jitter Tol
PCI Express 2.0 Add-In Card
Figure 11. Typical Receiver Tolerance Test Plot
SmartFusion2 SERDES Characterization Report
21
V.
Interoperability Results
The PCISIG Integrators List confirms that Microsemi has satisfied the PCISIG Compliance Program and
that the Endpoint solution successfully interoperated with other available systems at a PCISIG plug fest.
Microsemi Smartfusion2 SoC FPGAs are listed under the Components section of the Integrators List.
The list below highlights the many different partners that the Microsemi Smartfusion2 Endpoint
successfully interoperated with at the testing sessions.
Table 12.
System
PCIe Interoperability Systems
Chip Set
CPU
Endpoint
System
MindShare
Intel Sandy Bridge Xeon E5
Root Complex
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
X10SLM
Intel Lynx Point
Root Complex
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
RoseCity
Patsburgh
Root Complex
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
Gigabyte GA-Z77X-UD5H
Intel Z77
Root Complex
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
ioMillennia
Intel
Switch/System
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
PLX
PEX 8748
Switch/System
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
PLX 5
PEX 8718
Switch/System
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
PLX 4
PEX 8714
Switch/System
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
PLX 3
PEX 8749
Switch/System
2.0 @ 2.5GT/s, 5.0GT/s
3.0 A 8GT/s
Vl.
Conclusion
The test results demonstrate that the capabilities of the SmartFusion2 PCIe solution systems require high
reliability devices to be robust. This report provides a baseline summary of the thorough testing performed
by Microsemi to assure users that the device will meet the performance and functional requirements
in their customized PCI Express system.
22
List of Changes
The following table shows important changes made in this document for each revision.
Revision
Changes
Page
Revision 2
(July 2015)
Updated Table 8 (SAR 69150).
17
Revision 1
(August 2013)
Initial Release.
NA
SmartFusion2 SERDES Characterization Report
23
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51000021-02/07.15
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