IGLOO2 FPGA Evaluation Kit UG0478 User Guide UG0478: IGLOO2 FPGA Evaluation Kit User Guide Table of Contents 1 – Introduction .........................................................................................................................4 Kit Contents ................................................................................................................................................................ 4 IGLOO2 FPGA Evaluation Kit Web Resources .......................................................................................................... 4 Board Description ....................................................................................................................................................... 4 2 – Installation and Settings ....................................................................................................8 Software Installation ................................................................................................................................................... 8 Hardware Installation .................................................................................................................................................. 8 IGLOO2 Power Sources ........................................................................................................................................... 10 Testing the Hardware ............................................................................................................................................... 10 3 – Key Components Description and Operation ................................................................11 Powering Up the Board............................................................................................................................................. 11 Current Measurement ............................................................................................................................................... 11 Memory Interface ...................................................................................................................................................... 13 SERDES0 Interface .................................................................................................................................................. 14 USB Interface ........................................................................................................................................................... 16 Marvell PHY (88E1340S).......................................................................................................................................... 16 Programming ............................................................................................................................................................ 18 FTDI Interface ........................................................................................................................................................... 19 I2C Port Header ........................................................................................................................................................ 20 System Reset ........................................................................................................................................................... 20 Clock Oscillator ......................................................................................................................................................... 21 Debugging ................................................................................................................................................................ 21 GPIO Header Pin Out ............................................................................................................................................... 23 4 – Pin List...............................................................................................................................25 5 – Board Components Placement........................................................................................38 6 – Demo Design .....................................................................................................................41 M2GL-EVAL-KIT Board Demo Design ..................................................................................................................... 41 7 – Manufacturing Test...........................................................................................................42 M2GL-EVAL-KIT Board Testing Procedures ............................................................................................................ 42 Switches and LED Tests........................................................................................................................................... 54 Debugging the Board ................................................................................................................................................ 54 List of Changes .......................................................................................................................56 Product Support .....................................................................................................................57 Customer Service ..................................................................................................................................................... 57 Customer Technical Support Center ........................................................................................................................ 57 2 UG0478: IGLOO2 FPGA Evaluation Kit User Guide Table of Contents Technical Support ..................................................................................................................................................... 57 Website ..................................................................................................................................................................... 57 Contacting the Customer Technical Support Center ................................................................................................ 57 ITAR Technical Support............................................................................................................................................ 58 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 1 – Introduction ® The IGLOO 2 field programmable gate array (FPGA) Evaluation Kit (M2GL-EVAL-KIT) is RoHS compliant and enables the designer to develop applications that involve one or more of the following: • Motor control • System management • Industrial automation • High speed serial I/O applications like PCIe, SGMII, and user customizable serial interfaces Kit Contents Table 1 lists the contents of the IGLOO2 Evaluation Kit. Table 1 Kit Contents Quantity Description 1 IGLOO2 Evaluation Board with M2GL010T-1FGG484 1 FlashPro4 JTAG programmer for programming and debugging of the IGLOO2 device 1 USB 2.0 A male to mini-B Y-cable for UART/power interface (up to 1A) to PC 1 +12 V/2 A Wall-Mounted power supply - FTDI drivers to perform the MTD test IGLOO2 FPGA Evaluation Kit Web Resources IGLOO2 Evaluation Kit web resources are available at: http://www.microsemi.com/products/fpga-soc/design-resources/dev-kits/igloo2/igloo2-evaluation-kit#overview Board Description The IGLOO2 Evaluation Kit offers a full-featured Evaluation Board for IGLOO2 FPGAs. This kit inherently integrates the following on a single chip: • Reliable flash-based FPGA fabric • Advanced security processing accelerators • Digital signal processing (DSP) blocks • Static random-access memory (SRAM) • Embedded nonvolatile memory (eNVM) • Industry-required high-performance communication interfaces The board has numerous interfaces including an RJ45 for 10/100/1000 Ethernet, one Full-Duplex SERDES Lane through sub miniature version A (SMA) connectors, a 64-bit GPIO Header, and various connectors for SPI support. The IGLOO2 memory management system is supported by 512 Mb of on board mobile LPDDR SDRAM memory and 64 Mb SPI flash. The serializer and deserializer (SERDES) block can be accessed through the peripheral component interconnect express (PCIe) edge connector or high speed SMA connectors. 4 • The board supports the M2GL010T device in an FG484 package • The board is eight layers PCB and manufactured with FR4 dielectric material. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 1 – Introduction Block Diagram Figure 1 shows the IGLOO2 evaluation kit block diagram. J1 GPIO Header U15 SPI flash W25Q64FV SSIG SPI_0 Bank2 LPDDR MT46H32M16LF 8 Meg x 16 x 4 banks Debug Switches-4 MSIO Bank1 MSIO Bank4 MSIO Bank7 Lane 0 PCIE edge connector REFCLK0 MDDR Bank0 Lane 1 SERDES0 SMA Connectors Lane 2 Bank2 SMA Connectors REFCLK1 Mux IGLOO2 FPGA – M2GL010T-1FGG484 Debug LEDs-8 Bank7 Lane 3 SGMII MDIO Bank7 PHY 88E1340S On Board Oscillator125MHz RJ45 JTAG PHY Bank2 Bank1 JTAG Bank4 ETM Bank1 SC_SPI FT4232 USB mini B connector 23-pin header USB3320 ETM Header RVI Header FP4 Header J9 J4 J5 USB micro AB connector P1 Figure 1 IGLOO2 FPGA Evaluation Kit Block Diagram Board Overview Figure 2 shows an overview of the IGLOO2 Evaluation Kit Board features. Figure 2 IGLOO2 FPGA Evaluation Kit Board Overview Note: Microsemi recommends SMA Male to SMA Male Precision Cable 12 Inch length using PE-SR405FLJ Coax, RoHS to use with IGLOO2 Evaluation Kit. For more information refer to http://www.pasternack.com/sma-malesma-male-pe-sr405flj-cable-assembly-pe39429-12-p.aspx UG0478: IGLOO2 FPGA Evaluation Kit User Guide 5 1 – Introduction I/O Voltage Rails Table 2 lists the bank I/Os with voltage rails. Table 2 I/O Voltage Rails IGLOO2 Bank I/O Rail Voltage Bank0 VDDI0 1.8 V Bank1 VDDI1 3.3 V Bank2 VDDI2 3.3 V Bank3 VDDI3 3.3 V Bank4 VDDI4 3.3 V Bank5 VDDI5 2.5 V Bank6 VDDI6 2.5 V Bank7 VDDI7 3.3 V Table 3 describes the IGLOO2 FPGA Evaluation Kit Board components. Table 3 IGLOO2 FPGA Evaluation Kit Board Components Name Description M2GL010T-1FGG484 Microsemi IGLOO2 FPGA Mobile Low-Power DDR SDRAM 512 Mb (MT46H32M16LF – 8 Meg x 16 x 4 banks) for storing the data bits. SPI flash 64 Mb SPI flash Winbond electronics W25Q64FVSSIG connected to SPI port 0 of the IGLOO2 FPGA high performance memory system (HPMS). Ethernet RJ45 connector (Ethernet jack with magnetic) interfacing with Marvell 10/100/1000 BASE-T PHY chip 88E1340S in serial gigabit media independent interface (SGMII) mode, interfacing with the Ethernet port of the IGLOO2 FPGA (on-chip MAC and external PHY). RVI header RVI header for application programming and debugging from Keil ULINK or IAR J-Link. FP4 header FlashPro4 programming header for IGLOO2 programming and debugging with Microsemi tools. Future Technology Devices International (FTDI) programmer FTDI programmer interface (J18) to program the external SPI flash. Embedded trace (ETM) cell header ETM header for debugging. macro GPIO header General purpose input/output (GPIO) header for multi standard I/O (MSIO) signals to be routed. PCIe edge connector PCI Express edge connector with one lane Dual in-line package (DIP) switch Debug switch for user application. Light-emitting diodes (LEDs) Three active high LEDs that are used for power supply indication. Push–button reset Push-button system reset for IGLOO2 system. Push–button switches Four push-button switches for test and navigation. USB interface USB micro AB connector, interfacing with the high speed USB2.0 ULPI transceiver chip 6 Eight active low LEDs that are connected to some of the user I/Os for debug. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 1 – Introduction Name Description USB3320, interfacing with FPGA pins of the IGLOO2 HPMS. OSC-125 125 MHz clock oscillator (differential output) OSC-50 50 MHz clock oscillator OSC-32 32.768 KHz low-power oscillator UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 2 – Installation and Settings Software Installation ® Download and install the latest release of Microsemi Libero System-on-Chip (SoC) software v11.1 or later, from the Microsemi website and register for a free Gold license. For instructions on how to install Libero and SoftConsole, refer to the Libero Installation and Licensing Guide available on the Microsemi website. Refer to the Installing IP Cores and Drivers User Guide to download and install Microsemi DirectCores, SGCores, and driver firmware cores. These must be localized on the PC where Microsemi Libero is installed while designing with Microsemi FPGAs. Hardware Installation The FlashPro4 programmer can be used to program the M2GL-EVAL-KIT board. Jumpers, Switches, LEDs, and DIP Switch Settings The recommended default jumpers, switches, LEDs, and DIP switch settings are defined in Table 4 through Table 6. • Table 4 Jumper Settings • Table 5 LEDs • Table 6 Test Points Connect the jumpers using the default settings to enable the pre-programmed demonstration design to function correctly. Table 4 shows the jumpers along with default settings. Note: Location of all the jumpers and test points are searchable in Figure 18 of 5 – Board Components Placement section. Table 4 Jumper Settings Jumper Function Default Settings Jumper to select switch-side Mux inputs of A or B to the line side. – Pin 1-2 (Input A to the line side) that is on board 125 MHz differential clock oscillator output will be routed to line side. Closed Pin 2-3 (Input B to the line side) that is external clock required to source through SMA connectors to the line side. Open Jumper to select the output enables control for the line side outputs. – Pin 1-2 (Line side output enabled) Closed J22 Pin 2-3 (Line side output disabled) Open J24 Jumper to provide the VBUS supply to USB when using in Host mode. Open JTAG selection jumper to select between RVI header or FP4 header for application debug. – Pin 1-2 FP4 for SoftConsole/FlashPro Closed J23 Pin 2-3 RVI for Keil ULINK™/IAR J-Link ® Open J8 Pin 2-4 for Toggling JTAG_SEL signal remotely using GPIO capability of FT4232 chip. Open J3 Jumpers to select either SW2 input or signal ENABLE_FT4232 from FT4232H chip. – 8 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 2 – Installation and Settings Jumper Function Default Settings Pin 1-2 for Manual power switching using SW7 switch. Closed Pin 2-3 for Remote power switch using GPIO capability of FT4232 chip. Open Table 5 lists the power supply and Ethernet LEDs. Table 5 LEDs LED Comment DS1 - Green Indicates the 5 V rail. DS2 - Green Indicates the 3.3 V rail. DS3 - Green Indicates the 12 V power source. DS5 - Green Connected to parallel LED output port 0 (P0_LED[0]) of Marvell PHY. DS4 - Green Connected to parallel LED output port 0 (P0_LED[2]) of Marvell PHY. DS6 - Green Connected to parallel LED output port 0 (P0_LED[3]) of Marvell PHY. Table 6 lists the USB, ground, and other test points. Table 6 Test Points Test Point Description TP8 USB switch in/out for DP signal. TP9 USB switch in/out for DM signal. TP1, TP2, TP4, TP5, TP6, TP7, TP10, TP11 GND TP3 Test point for DDR_VTT TP12 Test point to measure the voltage at TP12 with reference to GND. TP14 1.2 V current sensing test point TP15 1.8 V current sensing test point TP16, TP17 Test points across current sense resistor 0.05 Ohms for 1.2 V TP18, TP19 Test points across current sense resistor 0.05 Ohms for 1.8 V UG0478: IGLOO2 FPGA Evaluation Kit User Guide 9 2 – Installation and Settings IGLOO2 Power Sources All the power supply devices used in the IGLOO2 FPGA Evaluation Kit are Microsemi devices. For more information on power supply devices refer to http://www.microsemi.com/product-directory/ics/853-power-management Voltage rails (12 V, 5 V, 3.3 V, 2.5 V, 1.8 V, 1.5 V, and 1.0 V) provided on the board is shown in Figure 3. 12P0V CORE 1P2V 5P0V LDO 5P0V_REG EN DC/DC LX7165 NX9548 0.9V for LPDDR DDR_VTT VDDI 1, 2, 3, 4, 7 3P3V I/P TPS51200 LX7165 VDDI 5, 6 2P5V LX7175 1P0V_PHY LX7186 LPDDR, VREF0, VDDI 0, PHY_1P8V, 1P8V VDDAPLL, 2P5V_LDO LX7167 LX8240 SERDES_0_Lxy_VDDAPLL VPP, PLL Supply 3P3V_LDO SERDES_0_Lxy_REFRET LX13043 IGLOO2 SERDES_0_PLL_VDDA SERDES_0_PLL_VSSA Figure 3 Voltage Rails in the IGLOO2 FPGA Evaluation Kit Testing the Hardware If the board is shipped directly from Microsemi, it contains a test program that determines whether or not the board works properly. If you suspect that the board is damaged, you can rerun the Manufacturing Test to verify the key interfaces of the board functionality. Refer to 7 – Manufacturing Test section for manufacturing test procedures. 10 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 – Key Components Description and Operation This chapter describes the key component interfaces. For device datasheets, refer to: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=132042. Powering Up the Board The board can be powered through either of two 12 V sources that are, external +12 V/2 A DC jack or PCIe connector as shown in Figure 4. Protection mechanism enables the external DC jack supply, if both the sources are available, simultaneously. When both the power sources are ON, board takes the power from external DC jack as Diode D3 becomes reverse biased and path will be open for 12P0_PCIE. When the external DC voltage is not present, the board can be powered up using the PCIe connector. 12P0V_IN 12P0V J6 +12 V DC Jack SW7 PCIe CON1 2 J3 ENABLE_FT4232 5 1 3 4 6 Figure 4 Powering Up the Board Current Measurement 1.2 V Current Sensing for Normal Operation For applications which require current measurement high precision Operational Amplifier circuitry (U31 with gain 100) is placed on the board to measure the output voltage at TP14 test point with reference to the ground. Core power can be measured by following these steps: 1. Measure the output voltage (VOUT) at TP14. 2. I = (VOUT/5) 3. Core Power consumed P= (1.2 V)*I For example, when the voltage measured across TP14 as 0.5 V, then the consumed core power is 0.12 W. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 11 3 – Key Components Description and Operation Figure 5 shows the onboard core power measurement circuitry. 5.0 V 5.0 V 1.2 V Gain 100 TP14 U31 0.05Ω_1% 1.2 V Regulator TP16 TP17 LX7165 Figure 5 Core Power Measurement 1.2 V Current Sensing for Flash*Freeze The IGLOO2 device consumes very low power in Flash*Freeze mode. The voltage across the sense resistor (0.05 ohms) needs to be measured directly using a precision digital multi-meter that can read sub milli-volts. Test points TP16 and TP17 can be used to directly measure voltage across the 1.2 V sense resistor. To convert the voltage measured across sense resistor to power, use the following equation: 𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 = ( voltage_measured_in_milli_volts 1.8 V Current Sensing 0.05 ) ∗ 1.2 For applications which require current measurement high precision Operational Amplifier circuitry (U32 with gain 100) is placed on the board to measure the output voltage at TP15 test point with reference to the ground. 1.8 V power can be measured by following these steps: 1. Measure the output voltage (VOUT) at TP15. 2. I = (VOUT/5) 3. Power consumed P= (1.8 V)*I For example, when the voltage measured across TP15 as 0.5 V, then the consumed power is 0.18 W. 5.0 V 5.0 V 1.8 V Gain 100 TP15 U32 0.05Ω_1% 1.8 V Regulator LX7167 Figure 6 1.8 V Power Measurement Figure 6 shows the onboard 1.8 V power measurement circuitry. Note: The measured accuracy is ± 10%. 12 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 – Key Components Description and Operation Memory Interface Dedicated I/Os are provided for HPMS DDR and fabric DDR for the IGLOO2 device. Apart from the dedicated I/Os, regular I/Os can also be used to connect to other memory devices. Refer to Figure 7. Mobile LPDDR SDRAM An individual chip, 512 Mb LPDDR SDRAM memory is provided as flexible volatile memory for user applications. The LPDDR interface is implemented in bank 0. The specifications of LPDDR SDRAM are listed below: • MT46H32M16LF – 8 Meg x 16 x 4 banks • Density: 512 Mb • Data rate: LPDDR 16-bit at 166 MHz clock rate Note: For more information, refer to page 3 of Board Level Schematics document (provided separately). SPI Serial Flash The specifications of SPI Flash are listed below: • Density: 64 Mb • Voltage: 2.7 V - 3.6 V • Frequency: 104 MHz • Supports: SPI modes 0 and 3 • IGLOO2 HPMS - SPI0 interfaced to SPI flash Note: For more information, refer to page 8 of Board Level Schematics document (provided separately). Micron CLK MDDR- Bank0 DQ[15:0] A[13:0] IGLOO2 FPGA Bank2 LPDDR MT46H32M16LFBF-6 Control lines SPI_0 SPI Flash W25Q64FVSSIG Winbond Electronics Figure 7 IGLOO2 Memory Interface The IGLOO2 Evaluation Kit design uses the LPDDRI and LVCMOS18 standards for LPDDR interface. The default board assembly available for the LPDDRI standard has RC terminations. The LVCMOS18 I/O standard has lower power characteristics than the LPDDRI (SSTL18) standard for the LPDDR memories. For low power characteristics (LPDDR in LVCMOS18 mode), perform the following steps: 1. Change the I/O type in the design example to LVCMOS18. 2. Remove the RC terminations. (For more information, refer to the board schematics on page 8) UG0478: IGLOO2 FPGA Evaluation Kit User Guide 13 3 – Key Components Description and Operation SERDES0 Interface The SERDES0 has four lanes connected as shown below: 1. 2. Lane0 is directly routed to the PCIe connector. • TX Pad trace AC Coupling trace via (to bottom layer) trace PCIe connector pad • RX Pad trace PCIe connector pad Lane1 is used for loopback testing. This path is routed between the Tx and Rx with a 6 inch trace and 2 vias. • 3. 4. TX Pad via (to Bottom layer) trace AC Coupling trace via (to top layer) RX pad Lane2 routed to SMA connectors. • TX Pad trace AC Coupling trace SMA connector pad • RX Pad trace via (to bottom layer) trace via (to top layer) SMA connector Pad Lane3 is routed to Marvell PHY (88E1340S). • TX pad trace AC Coupling trace via trace routed in (6th layer) via (to top layer) Marvel PHY pin • RX pad via trace routed in 6th layer via (to top layer) trace AC Coupling trace Marvel PHY pin SERDES0 reference clock 0 is routed directly from the PCIe connector to IGLOO2 FPGA. SERDES0 reference clock 1 is routed from the onboard 125 MHz clock oscillator and optionally routed from SMA connectors through LVDS Mux/Buffer chip. Expected SERDES reference clock specifications: • Voltage level: 3.3 (± 0.3)V • Differential LVDS Symmetry: 50% (± 10%) Rise/Fall Time: 1nsec Max @ 20% to 80% of supply (3.3 V) Output Voltage Levels: “0”=0.90 Minimum, 1.10 Typical Differential Output Voltage: 247 mV Minimum, 454 mV Maximum “1”=1.43 Typical, 1.60 Maximum 14 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 – Key Components Description and Operation RXD1 Lane1 TXD1 Loopback RXD0 Lane0 SERDES0 TXD0 RXD3 Lane3 TXD3 Marvell PHY PCIe Connector RXD2 Lane2 TXD2 SMA REF CLK0 IGLOO2 FPGA REF CLK1P REF CLK1N A O/Ps B Marvell PHY On board Oscillator SMA MUX 3.3 V J23 MUX Sel 3.3 V MUX Circuit O/P Sel J22 Figure 8 SERDES0 Interface For more information on J22 and J23 jumpers, refer to Table 4. Note: • SERDES0 TXD pairs are capacitively coupled to the IGLOO2 device. Series AC coupling capacitors are used to provide Common mode voltage independence. • The AC coupling capacitors are not provided for SERDES 0 RXD signals. The mating board must have the AC coupling capacitors. • For more information, refer to page 4 of Board Level Schematics document (provided separately). UG0478: IGLOO2 FPGA Evaluation Kit User Guide 15 3 – Key Components Description and Operation USB Interface The SMSC USB3320 is a high speed USB 2.0 ULPI transceiver. It includes full support for the optional OTG protocol. CPEN: External 5 V supply enables. It controls the external VBUS power switch. CPEN U19 U20 5P0V MAX1823B REFCLK Jumper 26 MHz XO OTG Capable VBUS IGLOO2 FPGA 1K J24 VBUS 2.2uF P1 VBUS ID USB- PHY USB3320 Micro-AB USB Connector DM Control lines Bank2 DP DATA[7:0] ESD Diodes Figure 9 USB Interface Note: For more information, refer to page 10 of Board Level Schematics document (provided separately). Marvell PHY (88E1340S) The IGLOO2 Evaluation Kit utilizes the on board Marvell Alaska PHY device (88E1340S) for Ethernet communications at 100 or 1000 Mbps. 88E1340S has four independent Gigabit Ethernet transceivers, but the board uses only one transceiver. Each transceiver performs all the physical layer functions for 100BASE-TX and 1000BASE-T full or half duplex Ethernet on CAT5 twisted pair cable. The PHY connection to a user-provided Ethernet cable is through an RJ-45 connector with built-in magnetics. The 88E1340S device supports the quad SGMII for direct connection to an IGLOO2 chip. Refer to Figure 10. The 88E1340S is configured through the CONFIG [3:0] pins and CLK_SEL [1:0]. CLK_SEL [1:0] is used to select the reference clock input option. On board, the status of CLK_SEL0 is High and CLK_SEL1 is Low. REF_CLK is the 125 MHz reference differential clock input. It consists of LVDS differential inputs with a 100Ω differential internal termination resistor. • RCLK – Gigabit recovered clock • SCLK – 25 MHz synchronous input reference clock • Expected reference clock (REF_CLK) specifications Voltage level: 3.3 (± 0.3)V Differential LVDS Symmetry: 50% (± 10%) Rise/Fall Time: 1nsec Max @ 20% to 80% of supply (3.3 V) Output Voltage Levels: “0”=0.90 Minimum, 1.10 Typical “1”=1.43 Typical, 1.60 Maximum 16 Differential Output Voltage: 247 mV Minimum, 454 mV Maximum UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 – Key Components Description and Operation SERDES0 LANE3 0 SGMII 1 P0 Bank7 MDC/ MDIO/ INT/ PHY_RST 2 Magnetics/Jack J13 3 Clocks G1 H1 IGLOO2 FPGA RCLK1 RCLK2 Differential Clocks Mux SMA Connectors Marvell PHY 88E1340S On Board Oscillator125MHz 1588 REFCLK+ 1588 REFCLK- REF_CLKP REF_CLKN SCLK 25 MHz XTAL_IN XTAL_OUT U14 USB FT4232H JTAG Figure 10 IGLOO2 Marvell PHY Interface Note: For more information, refer to page 11 and 12 of Board Level Schematics document (provided separately). UG0478: IGLOO2 FPGA Evaluation Kit User Guide 17 3 – Key Components Description and Operation Programming The IGLOO2 device can be programmed through the JTAG interface. Figure 11 shows various ways of IGLOO2 programming. 3P3V J9 ETM Trace Debugger FLASH_GOLDEN_N MUX RVI HEADER I0 JTAG Jlink Tracer Cable J4 I1 FP4 Header IGLOO2 FPGA S FP4 Cable J5 3.3V J8 CD1 JTAG_SEL U14 FT4232H SC_SPI Figure 11 IGLOO2 Programming Interface JTAG_SEL: JTAG_SEL is used to switch between FP4 header (High) and RVI header or ETM header (Low). For more information on J8 jumper, refer to Table 4. RVI Header One 10X2 RVI header is provided on the board for debugging. This header allows plugging in the Keil ULINK debugger or IAR J-Link debugger. FlashPro4 Programming Header The IGLOO2 device on the Evaluation Kit can be programmed using a FlashPro4 programmer. In addition, FlashPro4 is used for software debugging by SoftConsole. Note: 18 • For more information, refer to page 13 of Board Level Schematics document (provided separately). • For more details, refer to the IGLOO2 and SmartFusion2 Programming User Guide. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 – Key Components Description and Operation FTDI Interface FT4232H chip features are listed below: • USB 2.0 high speed (480 Mbps) to UART/MPSSE IC • Single-chip USB to quad serial ports with a variety of configurations • Entire USB protocol handled on the chip. USB specific firmware programming is not required • USB 2.0 high speed (480 Mbps) and Full Speed (12 Mbps) compatible • Two MPSSE on channel A and channel B, to simplify synchronous serial protocol (USB to JTAG, I2C, SPI, or bit-bang) design • Fully assisted hardware or X-On/X-Off software handshaking • +1.8 V (chip core) and +3.3 V I/O interfacing (+5 V tolerant) FT4232H J2 IGLOO2 FPGA SC_SPI A J18 U10 88E1340S JTAG B DM USB_MINI_RECEP DP Power Control Remotely IGLOO2 FPGA MSIO UART C ESD Diodes EEPROM D OSCI OSCO Serial EEPROM 12 MHz Figure 12 FTDI Interface Note: For more information, refer to page 14 of Board Level Schematics document (provided separately). UG0478: IGLOO2 FPGA Evaluation Kit User Guide 19 3 – Key Components Description and Operation I2C Port Header Table 7 shows the two I2C ports routed to header – H1: Table 7 I2C Port Header Pin Number IGLOO2 Pin Name Board Signal Name Header - H1 MSIO28NB1 I2C0_SCL 10, 14 G17 MSIO28PB1 I2C0_SDA 11, 15 R22 MSIO11NB2/CCC_NE0_CLKI2 I2C1_SCL 2, 6 P22 MSIO11PB2/CCC_NE0_CLKI1 I2C1_SDA 3, 7 G16 Note: For more information, refer to page 8 of Board Level Schematics document (provided separately). System Reset The DEVRST_N signal (active low) is asserted, if the power supply level 3.3 V or 1.2 V fall below the threshold level or by pressing the SW6 (push-button switch). DEVRST_N is an input-only reset pad that allows assertion of a full reset to the chip at any time. 1.2 V Sense TPS3808G09 Reset 3.3V 10K 3.3 V U3 DEVRST_n DS1818 Reset SW6 1uF IGLOO2 FPGA Push button switch Figure 13 System Reset Interface Note: For more information, refer to page 13 of Board Level Schematics document (provided separately). 20 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 – Key Components Description and Operation Clock Oscillator 50 MHz Clock Source Figure 14 shows the 50 MHz clock oscillator with +/-50 ppm is available on the board. This clock oscillator is connected to the FPGA fabric to provide a system reference clock. An on-chip IGLOO2 PLL can be configured to generate a wide range of high precision clock frequencies. Table 8 50 MHz Clock IGLOO2 Kit IGLOO2- Pkg No IGLOO2 Pin Name K1 MSIOD85PB6/CCC_NE1_CLKI1 50MHZ_ SECLK_ WST_K1 2P5V TRISTATE VDD Osc- 50MHz GND 50MHZ_ SECLK_ WST_K1 IGLOO2 FPGA OUT Figure 14 Clock Oscillator Interface Note: For more information, refer to page 6 of Board Level Schematics document (provided separately). Different Clock Sources The following are the different clock sources used in M2GL-EVAL-KIT: 1. 125 MHz clock oscillator. For more information refer to SERDES0 Interface. 2. 32.768 KHz crystal oscillators for main and auxiliary oscillators of IGLOO2 FPGA. Debugging User LEDs The board provides user access to eight active low LEDs, which are connected to the IGLOO2 device for debugging applications. Table 9 lists the onboard debugging LEDs. Table 9 LEDs IGLOO2 Eval Kit IGLOO2 - Pkg No IGLOO2 Pin Name LED0 - Yellow E1 MSIO73PB7 LED1 – Yellow F4 MSIO74NB7 LED2 – Green F3 MSIO74PB7 LED3 – Green G7 MSIO75NB7 LED4 – Red H7 MSIO75PB7 LED5 – Red J6 MSIO76NB7 LED6 – Blue H6 MSIO76PB7 LED7 - Blue H5 MSIO77NB7 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 21 3 – Key Components Description and Operation +3.3V 499 ohms IGLOO2 FPGA Figure 15 LEDs Interface Note: For more information, refer to page 15 of Board Level Schematics document (provided separately). Push-Button Switches The IGLOO2 Evaluation Kit comes with five push-button tactile switches that are connected to the IGLOO2 device. Table 10 lists the onboard push-button switches. Table 10 Push-Button Switches IGLOO2 Kit IGLOO2 - Pkg No IGLOO2 Pin Name SWITCH1 L20 MSIO15NB2 SWITCH2 K16 MSIO19NB2 SWITCH3 K18 MSIO20PB2 SWITCH4 J18 MSIO20NB2 SW6 R15 DEVRST_N +3.3 V 10K SWITCH1 SWITCH2 SWITCH3 IGLOO2 FPGA SWITCH4 Figure 16 Switches Interface Note: For more information, refer to page 15 of Board Level Schematics document (provided separately). Slide Switches–DPDT SW7–Power ON/OFF switch from external DC Jack, +12 V DC 22 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 3 – Key Components Description and Operation DIP Switch - SPST SW5–is a DIP switch that has four connections to the IGLOO2 device. Table 11 lists the onboard DIP switches. Table 11 DIP Switches IGLOO2 Kit IGLOO2 - Pkg No IGLOO2 Pin Name DIP1 L19 MSIO16PB2 DIP2 L18 MSIO16NB2 DIP3 K21 MSIO17PB2 DIP4 K20 MSIO17NB2 3.3V 4.7K 4.7K 4.7K 4.7K 1 SW5 DIP1 DIP2 IGLOO2 FPGA DIP3 DIP4 Figure 17 SPST Interface Note: For more information, refer to page 15 of Board Level Schematics document (provided separately). GPIO Header Pin Out The bank 4, bank 7, and bank 1 signals are routed to the GPIO header for user applications. Table 12 lists the GPIO header pin out details. Table 12 GPIO Header Pin Out IGLOO2 – U1 GPIO Header- J1 Pin No Pkg No GPIO Header- J1 Pin Name Pin No IGLOO2 – U1 Pkg No Pin Name 1 AB15 MSIO110PB4 2 3P3V 3 AA15 MSIO110NB4 4 VSS VSS 6 AA16 MSIO114PB4 AA17 MSIO114NB4 5 7 AB18 MSIO118PB4 8 9 AB19 MSIO118NB4 10 VSS 12 AB17 MSIO113PB4 AA18 MSIO113NB4 11 VSS 13 Y18 MSIO117PB4 14 15 Y19 MSIO117NB4 16 VSS 18 Y17 MSIO116PB4 MSIO115PB4 20 W17 MSIO116NB4 17 19 W16 UG0478: IGLOO2 FPGA Evaluation Kit User Guide VSS 23 3 – Key Components Description and Operation GPIO Header- J1 Pin No 21 IGLOO2 – U1 Pkg No V16 23 GPIO Header- J1 Pin Name Pin No IGLOO2 – U1 Pkg No Pin Name MSIO115NB4 22 VSS VSS 24 U14 MSIO112PB4 U15 MSIO112NB4 25 C22 MSIO27PB1 26 27 B22 MSIO27NB1 28 VSS 30 V13 MSIO108PB4 V14 MSIO108NB4 29 VSS 31 Y15 MSIO111PB4 32 33 W15 MSIO111NB4 34 VSS 36 G5 MSIO66PB7 G6 MSIO66NB7 35 VSS 37 F5 MSIO67PB7 38 39 F6 MSIO67NB7 40 VSS 42 E4 MSIO70PB7 E5 MSIO70NB7 41 VSS 43 C4 MSIO64PB7 44 45 D5 MSIO64NB7 46 VSS 48 C3 MSIO65PB7 B3 MSIO65NB7 47 VSS 49 B2 MSIO69PB7 50 51 A2 MSIO69NB7 52 VSS 54 C1 MSIO71PB7 B1 MSIO71NB7 53 VSS 55 D1 MSIO72PB7 56 57 D2 MSIO72NB7 58 59 VSS 60 D3 MSIO68PB7 61 3P3V 62 D4 MSIO68NB7 63 3P3V 64 24 VSS VSS UG0478: IGLOO2 FPGA Evaluation Kit User Guide 4 – Pin List Table 13 lists the pins for IGLOO2 M2GL010T-FG484 devices. Note: *D21- Pin cannot be used as a fabric output and it is only an input. Table 13 Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name A1 VSS A10 DDRIO51PB0/MDDR_DM_RDQS0 A11 DDRIO51NB0/MDDR_DQ4 A12 DDRIO48PB0/MDDR_DQ8 A13 DDRIO48NB0/MDDR_DQ9 A14 DDRIO44PB0/MDDR_DQ12 A15 DDRIO44NB0/MDDR_DQ13 A16 DDRIO39PB0/MDDR_CLK A17 DDRIO39NB0/MDDR_CLK_N A18 DDRIO38PB0/MDDR_BA0 A19 DDRIO38NB0/MDDR_BA1 A2 MSIO69NB7 A20 DDRIO34NB0/MDDR_ADDR6 A21 DDRIO31PB0/MDDR_ADDR10 A22 VSS A3 DDRIO63NB0 A4 DDRIO63PB0 A5 DDRIO62NB0 A6 DDRIO59NB0/GB4 A7 DDRIO56PB0/MDDR_DQ_ECC1 A8 DDRIO56NB0/MDDR_DQ_ECC0 A9 DDRIO54NB0/MDDR_DQ1 AA1 VSS AA10 NC AA11 NC AA12 NC AA13 MSIO106PB4 AA14 VSS AA15 MSIO110NB4 AA16 MSIO114PB4 AA17 MSIO114NB4 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 25 4 – Pin List PKG.PIN AA18 MSIO113NB4 AA19 VDDI4 AA2 SERDES_0_TXD0_N AA20 VDD AA21 XTLOSC_MAIN_EXTAL AA22 JTAGSEL AA3 VSS AA4 SERDES_0_TXD1_N AA5 VSS AA6 SERDES_0_TXD2_N AA7 VSS AA8 SERDES_0_TXD3_N AA9 VSS AB1 VSS AB10 NC AB11 NC AB12 VDDI4 AB13 MSIO105PB4/CCC_NE0_CLKI0 AB14 MSIO105NB4 AB15 MSIO110PB4 AB16 VSS AB17 MSIO113PB4 AB18 MSIO118PB4 AB19 MSIO118NB4 AB2 SERDES_0_TXD0_P AB20 VDD AB21 XTLOSC_MAIN_XTAL AB22 VSS AB3 VSS AB4 SERDES_0_TXD1_P AB5 VSS AB6 SERDES_0_TXD2_P AB7 VSS AB8 SERDES_0_TXD3_P AB9 VSS B1 MSIO71NB7 B10 VSS B11 DDRIO52PB0/MDDR_DQS0 B12 VDDI0 B13 DDRIO46PB0/MDDR_DQS1 26 M2GL010TS/M2GL010T-FG484 Pin Name UG0478: IGLOO2 FPGA Evaluation Kit User Guide 4 – Pin List PKG.PIN B14 VSS M2GL010TS/M2GL010T-FG484 Pin Name B15 DDRIO41PB0/MDDR_CKE B16 VDDI0 B17 DDRIO37NB0/MDDR_ADDR0 B18 VSS B19 DDRIO34PB0/MDDR_ADDR5 B2 MSIO69PB7 B20 VDDI0 B21 DDRIO31NB0/MDDR_ADDR11 B22 MSIO27NB1 B3 MSIO65NB7 B4 VSS B5 DDRIO62PB0 B6 DDRIO59PB0/GB0 B7 DDRIO58NB0/MDDR_DQS_ECC_N B8 VDDI0 B9 DDRIO54PB0/MDDR_DQ0 C1 MSIO71PB7 C10 VDDI0 C11 DDRIO52NB0/MDDR_DQS0_N C12 VSS C13 DDRIO46NB0/MDDR_DQS1_N C14 VDDI0 C15 DDRIO41NB0/MDDR_CS_N C16 DDRIO37PB0/MDDR_BA2 C17 DDRIO35PB0/MDDR_ADDR3 C18 DDRIO35NB0/MDDR_ADDR4 C19 DDRIO33NB0/MDDR_ADDR7 C2 VDDI7 C20 DDRIO33PB0/MDDR_ODT C21 VSS C22 MSIO27PB1 C3 MSIO65PB7 C4 MSIO64PB7 C5 DDRIO61PB0 C6 VDDI0 C7 DDRIO58PB0/MDDR_DQS_ECC C8 VSS C9 DDRIO55NB0 D1 MSIO72PB7 D10 DDRIO50PB0/MDDR_DQ5 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 27 4 – Pin List PKG.PIN D11 M2GL010TS/M2GL010T-FG484 Pin Name DDRIO50NB0/MDDR_DQ6 D12 DDRIO47PB0/MDDR_DQ10 D13 DDRIO47NB0/MDDR_DQ11 D14 DDRIO43PB0/MDDR_DQ14 D15 VSS D16 DDRIO36PB0/MDDR_ADDR1 D17 VDDI0 D18 DDRIO29PB0/MDDR_ADDR14 D19 VSS D2 MSIO72NB7 D20 DDRIO30NB0/MDDR_ADDR13 D21 MSI26NB1 D22 FLASH_GOLDEN_N D3 MSIO68PB7 D4 MSIO68NB7 D5 MSIO64NB7 D6 DDRIO61NB0 D7 MDDR_IMP_CALIB_ECC D8 DDRIO57NB0/MDDR_DM_RDQS_ECC D9 DDRIO55PB0/CCC_NE0_CLKI3 E1 MSIO73PB7 E10 DDRIO53NB0/MDDR_DQ3 E11 VDDI0 E12 DDRIO49PB0/MDDR_DQ7 E13 DDRIO43NB0/MDDR_DQ15 E14 VSS E15 DDRIO40PB0/MDDR_RESET_N E16 DDRIO36NB0/MDDR_ADDR2 E17 DDRIO32PB0/MDDR_ADDR8 E18 DDRIO29NB0/MDDR_ADDR15 E19 DDRIO30PB0/MDDR_ADDR12 E2 MSIO73NB7 E20 VDDI1 E21 MSIO25NB1 E22 MSIO25PB1 E3 VSS E4 MSIO70PB7 E5 MSIO70NB7 E6 VSS E7 DDRIO60PB0/MDDR_TMATCH_ECC_OUT E8 DDRIO57PB0/MDDR_TMATCH_ECC_IN 28 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 4 – Pin List PKG.PIN E9 VSS M2GL010TS/M2GL010T-FG484 Pin Name F1 VDDI7 F10 DDRIO53PB0/MDDR_DQ2 F11 VSS F12 DDRIO49NB0/MDDR_TMATCH_0_OUT F13 VDDI0 F14 DDRIO42PB0/MDDR_RAS_N F15 DDRIO40NB0/MDDR_CAS_N F16 VSS F17 DDRIO32NB0/MDDR_ADDR9 F18 MSIO24NB1 F19 MSIO24PB1 F2 NC F20 MSIO23NB1 F21 MSIO23PB1 F22 VDDI1 F3 MSIO74PB7 F4 MSIO74NB7 F5 MSIO67PB7 F6 MSIO67NB7 F7 VDDI0 F8 DDRIO60NB0/CCC_NE1_CLKI3 F9 VDDI0 G1 MSIO78NB7 G10 VREF0 G11 VREF0 G12 DDRIO45PB0/MDDR_TMATCH_0_IN G13 DDRIO45NB0/MDDR_DM_RDQS1 G14 DDRIO42NB0/MDDR_WE_N G15 VREF0 G16 MSIO28NB1 G17 MSIO28PB1 G18 MSIO22NB1 G19 MSIO22PB1/GB6 G2 NC G20 VSS G21 NC G22 NC G3 NC G4 VDDI7 G5 MSIO66PB7 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 29 4 – Pin List PKG.PIN G6 MSIO66NB7 G7 MSIO75NB7 G8 NC G9 NC H1 MSIO78PB7/GB2 H10 VDD H11 VSS H12 VDDI0 H13 VSS H14 VDDI0 H15 CCC_NE0_PLL_VDDA H16 MDDR_PLL_VDDA H17 MDDR_PLL_VSSA H18 VDDI1 H19 MSIO21NB1 H2 VSS H20 MSIO21PB1/GB5 H21 NC H22 NC H3 NC H4 MSIO77PB7 H5 MSIO77NB7 H6 MSIO76PB7 H7 MSIO75PB7 H8 NC H9 VSS J1 MSIO80PB7 J10 VSS J11 VDD J12 VSS J13 VDD J14 VSS J15 CCC_NE0_PLL_VSSA J16 CCC_NE1_PLL_VSSA J17 CCC_NE1_PLL_VDDA J18 MSIO20NB2 J19 NC J2 MSIO80NB7 J20 NC J21 VDDI1 J22 NC 30 M2GL010TS/M2GL010T-FG484 Pin Name UG0478: IGLOO2 FPGA Evaluation Kit User Guide 4 – Pin List PKG.PIN J3 MSIO79PB7/GB1 M2GL010TS/M2GL010T-FG484 Pin Name J4 MSIO79NB7 J5 VSS J6 MSIO76NB7 J7 VDDI7 J8 NC J9 VDD K1 MSIOD85PB6/CCC_NE1_CLKI1 K10 VDD K11 VSS K12 VDD K13 VSS K14 VDD K15 MSIO18NB2 K16 MSIO19NB2 K17 MSIO19PB2 K18 MSIO20PB2 K19 VSS K2 MSIOD85NB6 K20 MSIO17NB2 K21 MSIO17PB2 K22 NC K3 VDDI6 K4 MSIOD82PB6 K5 MSIOD82NB6 K6 MSIO81PB7 K7 MSIO81NB7 K8 MSIOD83PB6 K9 VSS L1 VSS L10 VSS L11 VDD L12 VSS L13 VDD L14 VSS L15 VPP L16 MSIO18PB2 L17 VDDI2 L18 MSIO16NB2 L19 MSIO16PB2 L2 MSIOD86PB6 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 31 4 – Pin List PKG.PIN L20 MSIO15NB2 L21 MSIO15PB2 L22 VSS L3 MSIOD86NB6 L4 MSIOD87PB6 L5 MSIOD87NB6 L6 VDDI6 L7 MSIOD84NB6 L8 MSIOD83NB6 L9 VDD M1 MSIOD92NB6 M10 VDD M11 VSS M12 VDD M13 VSS M14 VDD M15 VPPNVM M16 NC M17 NC M18 NC M19 NC M2 MSIOD90NB6 M20 VDDI2 M21 MSIO14PB2 M22 MSIO14NB2 M3 MSIOD90PB6 M4 VSS M5 MSIOD88PB6 M6 MSIOD88NB6 M7 MSIOD84PB6/CCC_NE1_CLKI2 M8 MSIOD95NB6 M9 VSS N1 MSIOD92PB6 N10 VSS N11 VDD N12 VSS N13 VDD N14 VSS N15 VSSNVM N16 MSIO8PB2 N17 MSIO8NB2 32 M2GL010TS/M2GL010T-FG484 Pin Name UG0478: IGLOO2 FPGA Evaluation Kit User Guide 4 – Pin List PKG.PIN N18 VSS M2GL010TS/M2GL010T-FG484 Pin Name N19 MSIO12PB2/SPI_0_CLK N2 VDDI6 N20 MSIO12NB2/SPI_0_SDI N21 MSIO13PB2/SPI_0_SDO N22 MSIO13NB2/SPI_0_SS0 N3 MSIOD91PB6 N4 MSIOD91NB6 N5 MSIOD89PB6 N6 MSIOD89NB6 N7 VSS N8 MSIOD95PB6 N9 VDD P1 MSIOD94PB6 P10 VDD P11 VSS P12 VDD P13 VSS P14 VDD P15 VPP P16 MSIO7NB2 P17 MSIO6PB2 P18 MSIO6NB2 P19 SC_SPI_SDO P2 MSIOD94NB6 P20 SC_SPI_SS P21 VSS P22 MSIO11PB2/CCC_NE0_CLKI1 P3 MSIOD93NB6 P4 MSIOD93PB6 P5 VDDI6 P6 MSIOD96PB6 P7 MSIOD96NB6 P8 SERDES_0_VDD P9 VSS R1 MSIOD97NB6 R10 VSS R11 VDD R12 VSS R13 VDD R14 VSS UG0478: IGLOO2 FPGA Evaluation Kit User Guide 33 4 – Pin List PKG.PIN R15 DEVRST_N R16 MSIO7PB2 R17 MSIO1PB2 R18 MSIO1NB2 R19 VDDI2 R2 MSIOD97PB6 R20 SC_SPI_CLK R21 SC_SPI_SDI R22 MSIO11NB2/CCC_NE0_CLKI2 R3 MSIOD98PB6 R4 MSIOD98NB6 R5 VSS R6 NC R7 NC R8 SERDES_0_L01_VDDAIO R9 VSS T1 MSIOD100NB5/SERDES_0_REFCLK0_N T10 SERDES_0_L23_VDDAIO T11 NC T12 NC T13 MSIO107NB4 T14 VDDI4 T15 VSS T16 NC T17 VSS T18 MSIO2PB2 T19 MSIO2NB2 T2 VSS T20 MSIO5PB2 T21 MSIO5NB2 T22 VDDI2 T3 MSIOD99NB6 T4 MSIOD99PB6 T5 NC T6 SERDES_0_PLL_VSSA T7 NC T8 SERDES_0_PLL_VDDA T9 SERDES_0_VDD U1 MSIOD100PB5/SERDES_0_REFCLK0_P U10 NC 34 M2GL010TS/M2GL010T-FG484 Pin Name UG0478: IGLOO2 FPGA Evaluation Kit User Guide 4 – Pin List PKG.PIN U11 NC M2GL010TS/M2GL010T-FG484 Pin Name U12 VSS U13 MSIO107PB4 U14 MSIO112PB4 U15 MSIO112NB4 U16 NC U17 NC U18 NC U19 MSIO0PB2 U2 VDDI5 U20 VSS U21 MSIO4NB2 U22 MSIO4PB2 U3 MSIOD101PB5/SERDES_0_REFCLK1_P U4 MSIOD101NB5/SERDES_0_REFCLK1_N U5 SERDES_0_L01_REXT U6 SERDES_0_L01_REFRET U7 SERDES_0_L01_VDDAPLL U8 SERDES_0_L23_VDDAPLL U9 VPP V1 VSS V10 VDDI4 V11 MSIO104PB4/GB3 V12 NC V13 MSIO108PB4 V14 MSIO108NB4 V15 VSS V16 MSIO115NB4 V17 NC V18 NC V19 MSIO0NB2 V2 VSS V20 JTAG_TMS V21 MSIO3NB2 V22 MSIO3PB2 V3 VSS V4 VSS V5 VSS V6 VSS V7 VSS V8 SERDES_0_L23_REXT UG0478: IGLOO2 FPGA Evaluation Kit User Guide 35 4 – Pin List PKG.PIN V9 SERDES_0_L23_REFRET W1 SERDES_0_RXD0_P W10 MSIO103PB4/PROBE_A W11 MSIO104NB4/GB7 W12 NC W13 VDDI4 W14 MSIO109NB4 W15 MSIO111NB4 W16 MSIO115PB4 W17 MSIO116NB4 W18 VSS W19 NC W2 VSS W20 JTAG_TCK W21 VDDI3 W22 JTAG_TDI W3 SERDES_0_RXD1_P W4 VSS W5 SERDES_0_RXD2_P W6 VSS W7 SERDES_0_RXD3_P W8 VSS W9 MSIO102PB4 Y1 SERDES_0_RXD0_N Y10 MSIO103NB4/PROBE_B Y11 VSS Y12 NC Y13 MSIO106NB4 Y14 MSIO109PB4 Y15 MSIO111PB4 Y16 VDDI4 Y17 MSIO116PB4 Y18 MSIO117PB4 Y19 MSIO117NB4 Y2 VSS Y20 NC Y21 JTAG_TDO Y22 JTAG_TRSTB Y3 SERDES_0_RXD1_N Y4 VSS 36 M2GL010TS/M2GL010T-FG484 Pin Name UG0478: IGLOO2 FPGA Evaluation Kit User Guide 4 – Pin List PKG.PIN Y5 SERDES_0_RXD2_N M2GL010TS/M2GL010T-FG484 Pin Name Y6 VSS Y7 SERDES_0_RXD3_N Y8 VSS Y9 MSIO102NB4/CCC_NE1_CLKI0 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 37 5 – Board Components Placement The IGLOO2 Evaluation Kit components placement on top and bottom sides, are shown in the following figures. Figure 18 shows the silkscreen top view. 38 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 50 G G D7 D6 TP2 20 10 C3 C2 G 10 5 G D4 D3 D2 C7 C6 C5 C4 L2 10 2 U7 H5 H6 J6 H7 G7 F3 F4 E1 U1 1 A Y2 J14 17 1 A1 DPR1 2 J9 20 J10 1 19 U5 1H1 4 1 3 Y1 2 4 I2C0_SCL 1 13 3 16 L2 X1 4 1 J21 SW1 2 U25 USB 1 3 C103 L20 U26 Y4 L6 CON1 B11 B12 J16 GND GND U21 1 A 1P2V 1 TP7 RXD2N TP11 1P2V_CUR_SENSE TP10 4 2 3 1 TP15 TP14 U23 L0 B1 TP18 TP19 1P8V_CUR_SENSE 1P8V TC18 TC19 Y5 XTAL J27 J26 1 CLK_EN J23 HZ OSC SERDES_REFCLK1 U22 SMA C79 TP16 TP9 Active L7 U20 1 J25 CR4 U19 A1 U18 J22 TP8 P1 1 CR3 SERDES_REFCLK1N J17 TP6 U15 SPI U16 Y3 5 TP17 CR1 L5 RXD2P TP5 SERDES_REFCLK1P J20 U11 SW3 U12 U14 CR2 J24 A B M2GL_M2S-EVAL-KIT DVP-102-000402-001 2 4 Rev C SW4 1 J8 19 A1 I2C0_SDA I2C1_SDA TXD2N J15 TXD2P U10 J13 K20 1 SW2 SW5 1 4 JTAG_SEL H J18 U9 9 PROG Header B1 DEVRST SW6 1 L L19 RMT K21 L18 L3 1 LED2 1 2 3 A A TC9 TC10 TC6 J7 1 ON 20 20 2 J5 L3 TC7 TC8 TP1 J4 J11 100MBPS LINK J12 LPDDR 5 FTDI-GPIO J2 B7 B6 B5 A7 A6 A5 A4 TP4 3 ETH PHY-SGMII FTDI G L1 3 4 1 G TP3 SW7 J18 G U6 J3 2 D9 D5 U8 1 SWT J6 1 30 15 G Trace DBG TC5 TC4 RMT G 40 20 G RVI/IAR TC3 12V U2 I2C1_SCL 60 GND TC2 TC1 3 U4 12V I/P 2 SF2-GPIO J1 G K16 C7 1GMBPS LINK 3.3V C10 D8 5V 1 U13 5 – Board Components Placement U24 J28 B18 Figure 18. Silkscreen Top View UG0478: IGLOO2 FPGA Evaluation Kit User Guide 39 C118 C117 C121 C122 C120 R155 R158 C125 C206 C212 C211 R162 C161 C153 R210 L8 R220 C299 C306 C309 L9 C244 C263 C284 C318 C253 C322 C252 C156 C157 C145 C158 C146 C159 C147 C31 C129 R179 R180 R230 R228 C326 C91 R244 R249 C342 R267 U31 R254 R232 R237 C336 C337 R243 C335 C341 R238 R239 C338 C339 R247 R235 C330 C331 R236 C332 J21 C329 R234 R233 C293 C308 R231 C216 C317 R246 C360 C348 R266 R245 J17 C294 C312 R226 R222 C325 C327 C321 R224 R221 C277 C278 C292 C209 C204 C295 C270 C221 C222 R212 R213 R214 C236 C251 R216 C245 R207 C323 C259 R202 C250 R209 C333 C334 R193 C215 R170 R182 C155 C162 C169 C173 C177 C180 C183 C190 C191 C192 C184 R205 C185 C188 R206 C187 C189 R200 R203 C358 U32 R271 C359 C182 C186 C195 C198 C361 R263 R264 R265 C363 R272 R172 C144 C151 C150 C154 C194 C328 C314 C316 C315 C362 C163 C167 C168 C171 C172 C175 C176 C179 C178 C181 C193 C218 C285 R225 R219 C283 C324 R166 C136 R167 C138 R169 C140 R173 C142 R188 C149 R190 C152 R194 C160 R195 C164 C272 C269 C347 R223 C205 C208 C213 C214 C219 C223 R211 C243 C232 C238 R218 R217 C271 C264 C296 C298 C297 C289 R227 C313 R229 D10 C127 C319 C320 J15 C349 R61 J16 C197 C207 R268 R269 R270 J20 C196 R204 R191 C199 R199 C200 C165 C201 C174 C166 C202 C119 U28 R201 C131 R184 R174 R185 R175 R186 R176 R187 R177 C281 C262 C242 C231 C287 C288 C254 C229 C304 C279 C255 C286 C260 C228 C280 C261 C241 C230 C303 J10 C311 C305 R240 C123 R159 R251 U27 R241 R248 C128 R161 D11 R160 C170 R208 C210 C124 C220 C217 C227 C226 R215 C240 C225 C235 C224 C248 C234 C233 C239 C237 C247 C126 C258 C249 C246 C257 C267 R163 C130 C256 C266 C276 C268 C133 C134 C273 R164 C275 C265 R165 C132 C350 C274 C282 R168 C135 C290 C301 C351 C137 C302 C300 R171 C291 R178 C139 C352 C307 R181 C141 R183 C143 C353 C310 R189 C148 R192 R198 R196 R197 R157 R156 5 – Board Components Placement CON1 Figure 19. Silkscreen Bottom View 40 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 6 – Demo Design M2GL-EVAL-KIT Board Demo Design The IGLOO2 M2GL-EVAL-KIT comes with a preloaded PCIe control plane demo design. This demo design demonstrates key features of IGLOO2 device such as - PCIe, GPIOs, and fabric interface controller of the IGLOO2 device. These features can be used for rapid prototyping and validation of user specific designs. Note: For more details on running the demo designs, refer to the Implementing PCIe Control Plane Design in IGLOO2 FPGA - Libero SoC v11.5 Tutorial. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 41 7 – Manufacturing Test M2GL-EVAL-KIT Board Testing Procedures IGLOO2 M2GL-EVAL-KIT contains a manufacturing test program that can be run to verify the functionality of the board. This program contains a list of options that can be run as diagnostics for the SERDES interface, low-power DDR (LPDDR), serial programming interface (SPI) flash, and debugging the LEDs and switches. From the list of provided menu options, either one or all of the tests can be selected to verify the functionality. Setting Up the Board for Test Before testing the IGLOO2 Evaluation Kit: • Download IGLOO2_MTD_top.stp, MTD_TESTER.exe, and PMA_SERDES_CONFIGURATOR.exe files from http://www.microsemi.com/soc/download/rsc/?f=IGLOO2_EVAL_KIT_MTD. • Download and install the drivers from: http://www.ftdichip.com/Drivers/D2XX.htm Loopback Test on SERDES Lanes Table 14 shows the list of tests performed on the four SERDES lanes in EPCS mode. Table 14 SERDES Lanes Loopback Tests Lane Tests Performed Lane 0 Internal loopback Lane 1 Internal and external loopback Lane 2 Internal loopback Lane 3 Internal loopback Internal Loopback Test on SERDES Lanes 42 1. Connect J18 to the test PC using the USB cable (mini USB to Type A USB cable). This is required for SERDES and UART communication. 2. Switch ON the SW7 power supply switch. 3. Ensure that the board is programmed with IGLOO2_MTD_top.stp file. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 – Manufacturing Test 4. Double-click the PMA_SERDES_CONFIGURATOR.exe file to open the PMA SERDES analyzer to test the Evaluation Kit board. Figure 20 shows the SERDES TEST APP window. Figure 20 SERDES TEST APP Window UG0478: IGLOO2 FPGA Evaluation Kit User Guide 43 7 – Manufacturing Test 5. Click the port settings tab on the SERDES TEST APP window. Figure 21 shows the port settings tab. Figure 21 Port Settings Tab 44 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 – Manufacturing Test 6. Select the highest COM port from the drop-down list and click Open to establish the connection with the test PC. Figure 22 Selecting the COM Port UG0478: IGLOO2 FPGA Evaluation Kit User Guide 45 7 – Manufacturing Test 7. Click the serdes analyzer tab to verify the connection. Figure 23 SERDES Analyzer Tab 46 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 – Manufacturing Test Ensure that Communication Status indicator is in green. If the UART communication is not set up properly, Communication Status indicator will be in red. Note: If the Core Reset status indicator is shown in green, click Deassert Core Reset to disable the core reset. Figure 24 Deasserting Core Reset 8. Select serdes lane0 from the Register Space drop-down list. Figure 25 Selecting Register Space UG0478: IGLOO2 FPGA Evaluation Kit User Guide 47 7 – Manufacturing Test 9. Click Enable Near (TX to RX) loopback to enable the internal near end loopback on SERDES Lane 0. Figure 26 Enabling Internal Loopback Figure 27 shows Near lpbk status indicator in green after clicking Enable Near(TX to RX) loopback. Figure 27 Enabled Internal Loopback 10. Click Enable PRBS Gen+checker to enable PRBS check. Figure 28 Enabling PRBS Generator 48 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 – Manufacturing Test Figure 29 shows PRBS gen status indicator in green after clicking Enable PRBS Gen+checker. Figure 29 Enabling PRBS Pattern Generation After the PRBS GEN+CHECKER is enabled, observe the PRBS error count for Lane0. It must be 0. 0 on PRBS error count shows that the internal loopback test is successful for SERDES lane 0. Any value other than 0 indicates that the internal loopback test is not successful and has errors. 11. Click Disable PRBS Gen +checker to stop the packet transmission and click Disable Near (TX to RX) loopback to disable the loopback. After clicking, Near lpbk status and PRBS gen status indicators change to red. Figure 30 Disabling Internal Loopback After testing internal loopback on SERDES Lane0, repeat the same test for other three SERDES lanes that is Lane 1, Lane 2, and Lane 3 by selecting the Lane from the Register Space drop-down list. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 49 7 – Manufacturing Test External Loopback on SERDES Lane1 External loopback can be performed on SERDES Lane 1 only. 1. Select serdes lane1 from the Register Space drop-down list. 2. Click Enable PRBS Gen+checker to check the error count. Figure 31 Selecting SERDES Lane 1 Figure 32 Enabling PRBS Genarator Figure 33 shows PRBS gen status indicator in green after clicking Enable PRBS Gen+checker. Figure 33 Enabling PRBS Pattern Generation After the PRBS GEN+CHECKER is enabled, observe the PRBS error count for Lane 1. It must be 0. 0 on PRBS error count shows that the internal loopback test is successful for SERDES Lane 1. Any value other than 0 indicates that the external loopback test is not successful and has errors. 3. 50 Close SERDES TEST APP window after the test is completed. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 – Manufacturing Test LPDDR and SPI Test Use the following procedure to initiate LPDDR and SPI tests on IGLOO2 Evaluation Kit: 1. Connect J18 to the test PC using the USB cable (mini USB to Type A USB cable). This is required for SERDES GUI UART communication. 2. Switch ON the SW7 power supply switch. 3. Ensure that the board is programmed with IGLOO2_MTD_top.stp file. 4. Double-click the MTD_TESTER.exe file to open the MTD TESTER to test the Evaluation Kit board. Figure 34 shows the MTD TESTER window. Figure 34 MTD TESTER Window 5. Click the port settings tab in the MTD TESTER window. Figure 35 Port Setting Tab in MTD TESTER Window UG0478: IGLOO2 FPGA Evaluation Kit User Guide 51 7 – Manufacturing Test 6. Select the highest COM port from the drop-down list and click Open to establish the connection with the test PC. Figure 36 Selecting COM Port Note: When using the USB cable for UART communication, four COM ports are shown in the drop-down list. 7. Click the register configuration tab. Figure 37 Register Configuration Tab 52 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 – Manufacturing Test Test Procedure for LPDDR In LPDDR test, you can test the board in multiple locations. 1. Enter No. Of Locations those are to be accessed on LPDDR memory. Note: By default number of locations is shown 5000. It can be modified. 2. Click DDR TEST to run the LPDDR write or read test. While the test is in progress, the DDR TEST PROGRESS shows the progress of the test in percentage. Figure 38 shows the test status as Pass after the test is completed successfully. Figure 38 LPDDR Test Note: If the LPDDR test fails, the number of locations where the test failed are displayed. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 53 7 – Manufacturing Test Test Procedure for SPI FLASH 1. Click SPI FLASH TEST to start SPI FLASH test. Figure 39 shows the status as PASS after the test is completed successfully. 2. Close the MTD TESTER window after the test is completed. 3. Click Clear Status to clear the status. Figure 39 SPI FLASH Test Switches and LED Tests Use the following switches to test the corresponding LED: • Press SW1, H5 LED must glow. • Press SW3, H6 LED must glow. • Press SW4, J6 LED must glow. • Press SW2, H7 LED must glow. Debugging the Board If the board is not programmed successfully, check if all the required power supplies, clocks, and reset signals are within the accepted range or not. Power Supply Validation 1. Check for all default jumper settings as per Table 4. 2. After power ON, power supplies with respect to the ground must be measured and the range must be as listed in Table 15. Table 15 Power Supply Range Power Rail Probing Point Accepted Voltage Range. (in Volt) 1P2V C95 Pin 2 1.15<VDD_REG<1.25 5P0V C16 pin 2 4.75<5P0V<5.25 3P3V C76 pin 2 3.15<3P3V<3.46 54 UG0478: IGLOO2 FPGA Evaluation Kit User Guide 7 – Manufacturing Test Power Rail Probing Point Accepted Voltage Range. (in Volt) 2P5V C107 pin 2 2.375<2P5V<2.625 3P3V_LDO C99 pin 1 3.135<3P3V_LDO<3.465 2P5V_LDO C100 pin 1 2.375<2P5V_LDO<2.625 DDR_VTT C22 pin 1 0.88< DDR3_VTT<.92 1P0V_PHY C36 pin 1 0.95< 1P0V_PHY<1.05 1P8V C31 pin 1 1.78<1P8V<1.82 3. LEDs (top left of board) corresponding to their respective power rails must glow. 4. Ripples on power rails must be within +/- 5% of respective voltage rail. Clock Measurement Measure clock signal at Y2 pin 3 and ensure that the stable 50 MHz signal is available. Reset Measurement Measure reset signal at resistor R14 and ensure that this is 3.3 V and held High. FPGA Programming Check whether IGLOO2 has been successfully programmed through the JTAG interface. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 55 List of Changes Revision Changes Page Revision 3 (September 2015) Updated LPDDR resolution changes. (SAR 52540, SAR 57285, SAR 61490, SAR 53271) N/A Revision 2 (January 2014) Added the recommended cable (SAR 53759). 5 Revision 1 (October 2013) Updated 7 – Manufacturing Test section (SAR 52040). 38 Note: The revision number is located in the part number after the hyphen. The part number is displayed at the bottom of the last page of the document. The digits following the slash indicate the month and year of publication. 56 UG0478: IGLOO2 FPGA Evaluation Kit User Guide Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world 408.643.6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions. Technical Support For Microsemi SoC Products Support, visit http://www.microsemi.com/products/fpga-soc/design-support/fpga-socsupport. Website You can browse a variety of technical and non-technical information on the Microsemi SoC Products Group home page, at http://www.microsemi.com/soc/. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website. Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is [email protected]. My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases. UG0478: IGLOO2 FPGA Evaluation Kit User Guide 57 Product Support Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email ([email protected]) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx. ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page. 58 UG0478: IGLOO2 FPGA Evaluation Kit User Guide Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: [email protected] © 2015 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,600 employees globally. Learn more at www.microsemi.com. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. 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