DG0471: SmartFusion2 SoC FPGA - In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6 Demo Guide

SmartFusion2 SoC FPGA In-System
Programming Using USB OTG Controller
Interface - Libero SoC v11.6
DG0471 Demo Guide
October 2015
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
Revision History
Date
Revision
Change
7
Eighth release
15 June 2015
6
Seventh release
09 March 2015
5
Sixth release
18 August 2014
4
Fifth release
3 May 2014
3
Fourth release
16 December 2013
2
Third release
27 November 2013
1
Second release
09 October 2013
0
First release
30 October 2015
Confidentiality Status
This is a non-confidential document.
DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microsemi Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
In-System Programming Using USB OTG Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Setting Up the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Authenticate Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verify Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
13
18
19
21
Checking if the Fabric is Programmed Successfully . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Checking if the eNVM is Programmed Successfully . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Programming Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Known Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 1: Board Setup Through the USB to UART (FTDI) Interface using the USB A to Mini - B Cable . . . . .
Appendix 2: Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 3: Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 4: Generating .spi Programming File using Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 5: Hardware Project Implementation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
24
25
26
27
30
Configuring the I/Os for Flash*Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Standby Clock Source Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SoftConsole Project Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Appendix 6: Implementing Workaround to Access Fabric LSRAM after IAP or ISP Program Operation . . . . . . . 34
Changes Required in Libero Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
A List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
B Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
41
41
41
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Preface
About this document
This demo is for the SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA)
devices. It provides instructions on how to use the corresponding reference design.
Intended Audience
SmartFusion2 devices are used by:
•
FPGA designers
•
Embedded designers
•
System-level designers
References
Microsemi Publications
•
UG0451: IGLOO2 and SmartFusion2 Programming User Guide
•
UG0450: SmartFusion2 SoC FPGA and IGLOO2 FPGA System Controller User Guide
•
UG0331: SmartFusion2 Microcontroller Subsystem User Guide
•
AC390: SmartFusion2 SoC FPGA Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories
Application Notes
•
Configuring Serial Terminal Emulation Programs Tutorial
See the following web page for a complete and up-to-date listing of SmartFusion2 device documentation:
http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#documents.
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In-System Programming Using USB OTG
Controller Interface
Introduction
In-system programming (ISP) allows to reprogram the design iterations and field upgrades. The
SmartFusion2 devices support ISP using universal serial bus (USB) on-the-go (OTG) controller interface.
This document describes how to program the following using ISP through the USB OTG controller
interface:
•
Embedded nonvolatile memory (eNVM)
•
FPGA fabric
•
Both the eNVM and the FPGA fabric
For information on different programming modes supported by SmartFusion2 SoC FPGAs, refer to the
UG0451: IGLOO2 and SmartFusion2 Programming User Guide. For information on USB OTG controller,
refer to the UG0331: SmartFusion2 Microcontroller Subsystem User Guide.
Design Requirements
Table 1 • Design Requirements
Design Requirements
Description
Hardware Requirements
SmartFusion2 Advanced Development Kit:
•
12 V adapter
•
FlashPro5 programmer
•
USB A to Mini-B cable
Host PC or Laptop
Rev A or later
Any 64-bit Windows Operating System
Software Requirements
Libero® System-on-Chip (SoC)
v11.6
SoftConsle
v3.4 SP1
FlashPro Programming Software
v11.6
Host PC Drivers
USB to UART
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In-System Programming Using USB OTG Controller Interface
Demo Design
Introduction
The demo design files are available for download from the following path in the Microsemi® website:
http://soc.microsemi.com/download/rsc/?f=m2s_dg0471_liberov11p6_df
The demo design files include:
•
Sample programming files
•
Libero SoC project
•
STAPL programming file
•
Source files
•
readme.txt
Figure 1 shows the top-level structure of the design files. For further details, refer to the readme.txt file.
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Figure 1 •
Demo Design Files Top-Level Structure
Figure 2 on page 7 describes the top-level demo. The SmartFusion2 device application configures the
following:
•
The MMUART_0 peripheral for serial communication with a host PC.
•
The USB OTG as mass storage class host, which can read or write files from the mass storage
device connected to the SmartFusion2 device through USB cable with Micro A end. Refer to the
"Appendix 5: Hardware Project Implementation Settings" section on page 30.
The SmartFusion2 device also initializes the system controller to run the ISP service. The SmartFusion2
device detects the connected USB mass storage device and accesses the programming files. The ARM®
Cortex®-M3 processor reads 512 byte blocks of the programming file data from the USB mass storage
device and sends the received blocks of data to the system controller ISP service.
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
The system controller ISP service executes the ISP operation in the requested mode and reports the
status to the Cortex-M3 processor. Refer to the "Description" section on page 8 for information on the
various modes of operation.
Cortex-M3
System
Controller
MSS
COMM_
BLK
COMM_
BLK
Cache
Controller
USB Mass
Storage Device
USB OTG
APB_1
SII
Master
USI
AHB SII
Master
UJTAG
AHB Bus Matrix
eNVM_0
eNVM_1
MMUART_0
Host PC
Data Transfer from
USB Mass Storage Device
FPGA Fabric
Programming eNVM and/or
Fabric using System
Controller ISP Service
SmartFusion2
Figure 2 •
APB_0
Top Level Demo Diagram
Connect the host PC to the SmartFusion2 device using the USB to UART (FTDI) interface.
Features
This demo design performs three types of programming based on the input provided by the programming
file.
•
eNVM programming: The ISP programming service programs only eNVM. In this case, the input
programming file has only eNVM content.
•
FPGA fabric programming: The ISP programming service programs only the FPGA fabric. In
this case, the input programming file has only the FPGA fabric content.
•
eNVM and FPGA fabric programming: The ISP programming service programs both the FPGA
fabric and eNVM. In this case, the input programming file has both the FPGA fabric and eNVM
content.
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In-System Programming Using USB OTG Controller Interface
Description
The ISP in SmartFusion2 devices is performed by the Cortex-M3 processor and the system controller.
The system controller manages the SmartFusion2 device programming and handles the system service
requests. The SmartFusion2 device allows the Cortex-M3 processor to directly provide a bitstream to the
system controller for programming. The Cortex-M3 processor initializes the system controller and
receives the programming bitstream from the USB mass storage device through the USB OTG controller
interface. The received bitstream is sent to the system controller to execute the ISP service in one of the
following modes of operations:
•
Authenticate: The system controller ISP service validates the integrity of the input data bitstream
and reports the status information to the Cortex-M3 processor.
–
•
Program: The system controller ISP service programs the following depending on the input data
bitstream:
–
•
For security and reliability reasons, Microsemi recommends that the bitstream is
authenticated before the program is executed using the Authenticate Operation mode. The
SmartFusion2 device application must commit only the bitstream for programming after
successful authentication and the integrity of the bitstream is validated.
eNVM
–
FPGA fabric
–
Both the eNVM and the FPGA fabric
Verify: The system controller ISP service verifies the contents of the SmartFusion2 device
against the input data bitstream and reports the status information to the Cortex-M3 processor.
The system controller ISP service utilizes the COMM_BLK interface to receive the entire programming
data bitstream as a continuous stream of bytes. Refer to the UG0331: SmartFusion2 Microcontroller
Subsystem User Guide for more information on communication block (COMM_BLK).
The Cortex-M3 processor in the SmartFusion2 device can execute an application image from embedded
SRAM (eSRAM), eNVM or DDR/SDR memories. Refer to the AC390: SmartFusion2 SoC FPGA
Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Notes for more information
on remapping techniques. In this demo design, the Cortex-M3 processor executes the ISP application
image from eSRAM while the eNVM programming taking place, that is during Program operation mode.
In order to execute the application image from eSRAM, the Cortex-M3 processor copies the ISP
application image (resides in eNVM data client) to the eSRAM and remaps the eSRAM to the Cortex-M3
processor code region. For Verify and Authenticate operation modes, the application image can be
executed from either eNVM or eSRAM since the eNVM programming is not taking place. Refer to the
"Appendix 5: Hardware Project Implementation Settings" section on page 30.
Programming Files
Sample programming files with the file extension .spi are provided to program:
•
eNVM
•
FPGA fabric
•
Both the eNVM and the FPGA fabric
The folder <download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files
contains the following sample programming files along with Libero design files.
•
envmonly.spi: Programs only eNVM. The eNVM client has a simple message display program.
•
fabriconly.spi: Programs only the FPGA fabric. The FPGA fabric has a light-emitting diode
(LED) blinking logic.
•
fabenvm.spi: Programs both the FPGA fabric and eNVM. The eNVM client has a message
display program and the FPGA fabric has an LED blinking logic. The folder
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files\fabric_an
d_envm contains the Libero design to generate this sample programming file.
•
isp_demo.spi: This is the .spi file format version of isp_demo.stp file provided in
<download_folder>\sf2_isp_using_usb_interface_demo_df\stapl_programming_file.
Note: For more information on generating .spi programming files refer to the "Appendix 4: Generating
.spi Programming File using Libero"section on page 27.
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
ISP Execution Flow
Figure 3 on page 10 describes the ISP flow. The SmartFusion2 device application initially configures the
USB OTG controller in host mode and MMUART_0 for serial communication. It also initializes the system
controller to start the ISP service in the selected operation mode.
On receiving the ISP operation mode and the programming file index, the application starts reading the
input source programming file in a 512 byte blocks. The application stores the received data in a
temporary buffer and sends the same data to the ISP service. The application requests the next block of
512 byte data until the entire file gets transferred from the USB mass storage device. The SmartFusion2
device application is notified with a status code when the ISP service completes the authentication or the
verification process. When the operation mode is Program, an internal device reset is generated for the
new design to take effect.
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In-System Programming Using USB OTG Controller Interface
Figure 3 shows the ISP execution flow.
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10
Execution Flow of ISP Operation Mode
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
Setting Up the Demo Design
The following steps describe how to setup the demo for SmartFusion2 Advanced Development Kit board:
1. Connect the host PC to the J18 Connector using the USB A to mini-B cable. The USB to UART
bridge drivers are automatically detected. Download and install the drivers from
www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip if the drivers are not
installed or detected automatically.
Verify if the detection is made in the device manager, as shown in Figure 4.
Figure 4 •
Device Manager
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In-System Programming Using USB OTG Controller Interface
2. Select one of the four COM ports with Location as on USB FP5 Serial Converter C. Figure 5
shows the Device Manager window and its properties that display the USB Serial Port
details.The COM port number is required to run the demo design.
Figure 5 •
Device Manager - FlashPro5 (COM33) Properties
3. Connect the jumpers on the SmartFusion2 Advanced Development Kit board as listed in Table 2.
CAUTION: Switch OFF the power supply switch, SW7 while connecting the jumpers.
Table 2 • SmartFusion2 Advanced Development Kit Jumper Settings
Jumper Number
Pin (from)
Pin (to)
J116, J353, J354,
J54
1
2
J123
2
3
J124, J121, J32
1
2
Comments
These are the default jumper settings of the SmartFusion2
Advanced Development Kit board. Ensure these jumpers are
set accordingly.
JTAG programming via FTDI
4. Connect the power supply to the J6 connector on the SmartFusion2 Advanced Development Kit
board.
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Running the Demo Design
1. Download the demo design from:
http://soc.microsemi.com/download/rsc/?f=m2s_dg0471_liberov11p6_df
2. Switch ON the SW7 power supply switch.
3. Start any serial terminal emulation program such as:
–
HyperTerminal
–
PuTTY
–
TeraTerm
The configuration for the program is:
–
Baud Rate: 57600
–
8 Data bits
–
1 Stop bit
–
No Parity
–
No Flow Control
For information on configuring the serial terminal emulation programs, refer to the Configuring
Serial Terminal Emulation Programs Tutorial.
4. Connect the USB cable Micro A end to the P1 connector of SmartFusion2 Advanced
Development Kit board and other end to the USB mass storage device.
Ensure to connect preformatted USB Flash drive to the SmartFusion2 device with the sample
programming files provided in
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files.
5. Launch the FlashPro software.
6. Click New Project.
7. In the New Project window, type the project name.
Figure 6 •
FlashPro New Project
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In-System Programming Using USB OTG Controller Interface
8. Click Browse and navigate to the location where you want to save the project.
9. Select Single device as the Programming mode.
10. Click OK to save the project.
11. Click Configure Device on the FlashPro GUI.
12. Click Browse and navigate to the location where the isp_demo.stp file is located and select the
file. The default location is:
<download_folder>\sf2_isp_using_usb_interface_demo_df\stapl_programming_file. The required
programming file is selected and is ready to be programmed in the device.
Figure 7 •
14
FlashPro Project Configured
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
13. Click PROGRAM to start programming the device. Wait until you get a message indicating that
the program passed. ISP requires the SmartFusion2 device to be preprogrammed with the
application code to activate the ISP service. Therefore, the SmartFusion2 device is
preprogrammed with the isp_demo.stp using the FlashPro software.
Figure 8 •
FlashPro Program Passed
–
LEDs 4 to 7 (C26, A27, F26, D26) blinking in the board indicate that the SmartFusion2 device
fabric is preprogrammed successfully.
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In-System Programming Using USB OTG Controller Interface
On programming the SmartFusion2 device successfully using FlashPro, the serial terminal
emulation program shows the initialization messages and ISP operation modes, as shown in
Figure 9.
Figure 9 •
16
ISP Operation Modes Selection
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
14. On selecting the operation mode, the files in the USB storage device are displayed, as shown in
Figure 10.
Note: Maximum of 10 files can be shown from the USB storage device.
Figure 10 • Available Files in USB Mass Storage Device
15. Select the programming file from the listed files by its index to perform the selected ISP operation
mode.
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In-System Programming Using USB OTG Controller Interface
Authenticate Operation Mode
To authenticate the data from fabenvm.spi, enter:
1. 0 to select Authenticate operation mode under Select ISP operational mode.
2. The corresponding index number to select fabenvm.spi programming file.
On selecting the programming file, the application starts reading the programming file from USB
mass storage device to execute the ISP operation mode. On completion of the ISP
authentication, the serial terminal emulation program displays an operation success message.
Figure 11 shows the operation success message.
Figure 11 • ISP Authentication Results
3.
18
Press any key to continue for other ISP operation mode. If the USB storage device files are not
displayed on serial terminal emulation program, press SW6 to reset the board.
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
Verify Operation Mode
To verify the device FPGA fabric and eNVM contents, enter:
1. 2 to select Verify operation mode under Select ISP operation mode.
2. The corresponding index number to select isp_demo.spi programming file.
On selecting the programming file, the application starts reading the programming file from USB
mass storage device to execute the ISP operation mode. On completion of the ISP verification,
the serial terminal emulation program displays an operation success message. Figure 12 shows
the operation success message.
Figure 12 • ISP Verification Results
The verification operation demonstrated is for the isp_demo.stp file that is already running in the
SmartFusion2 device. If any other .spi file is verified while the isp_demo.stp file is still running,
that verification operation fails.
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In-System Programming Using USB OTG Controller Interface
If the verification fails, the serial terminal emulation program displays an error message with an
error code. Figure 13 shows an example error message. For more information on error codes,
refer to the "Appendix 3: Error Codes"section on page 26.
The programming files are at:
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files.
All of them do not pass the verification. Only the isp_demo.spi file passes the verification
operation as it matches with the SmartFusion2 device contents (isp_demo.stp). The other
programming files fail verification.
Figure 13 • ISP Verification Failure Error Message
3. Press any key to continue for other ISP operation mode. If the USB storage device files are not
displayed on the serial terminal emulation program, press SW6 to reset the board.
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Program Operation Mode
To program the FPGA fabric and the eNVM of the SmartFusion2 device using the fabenvm.spi file,
enter:
1. 1 to select Program operation mode under Select ISP operation mode.
2. The corresponding index number to select fabenvm.spi programming file.
On selecting the programming file, the application starts reading the programming file from the
USB mass storage device to execute the ISP operation mode. The application checks the data
integrity of the selected programming file prior to perform the ISP program operation. After
completing the programming operation, an internal reset is generated for the new design to take
effect.
Figure 14 shows selection of program operation mode for the fabenvm.spi programming file.
Figure 14 • ISP Program Operation Mode
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In-System Programming Using USB OTG Controller Interface
Checking if the Fabric is Programmed Successfully
LEDs 0 to 3 (C28, B27, C27, E26) blinking in the board indicate that the fabric is programmed
successfully.
Checking if the eNVM is Programmed Successfully
The serial terminal emulation program displays the success message as shown in Figure 15 if the eNVM
is programmed successfully.
Figure 15 • ISP Program Results
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Programming Results
The result shown in Figure 15 on page 22 is for the fabenvm.spi file. Table 3 shows the possible
results for ISP Program operation mode for sample programming files provided in folder
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files.
Not all.spi files listed in the Table 3 are demonstrated.
Table 3 • ISP Programming Results
*.spi Programming
File Name
eNVM Programming Result
FPGA fabric Programming Result
envmonly.spi
The serial terminal emulation program shows successful NA
eNVM program message
fabonly.spi
NA
fabenvm.spi
The serial terminal emulation program shows successful SmartFusion2 LEDs 0 to 3 (C28, B27,
eNVM program message
C27, E26) blinking
SmartFusion2 LEDs 0 to 3 (C28, B27,
C27, E26) blinks
After successful ISP Program operation, the SmartFusion2 Advanced Development Kit board must be
reprogrammed with the original isp_demo.stp file to try the ISP operation modes again.
Known Issue
After successful completion of the two-step IAP or ISP, LSRAM read and write access fails from the
fabric path. This is a known silicon issue, which is documented in the ER0196- SmartFusion2 Device,
Errata. The workaround for this problem is to reset the system after the IAP or ISP program operation.
Microsemi recommends that this workaround can be implemented for any design, which accesses
LSRAM after IAP or ISP. For more information about how to implement this workaround, refer to the
"Appendix 6: Implementing Workaround to Access Fabric LSRAM after IAP or ISP Program
Operation"section on page 34.
The design example provided in this demonstration implements the workaround for accessing LSRAM
after implementing the IAP or ISP program operation in the Libero software. The design files are
available in the following location:
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files\LSRAM_Workar
ound
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In-System Programming Using USB OTG Controller Interface
Appendix 1: Board Setup Through the USB to UART (FTDI)
Interface using the USB A to Mini - B Cable
Figure 16 • Board Setup when Through the USB to UART (FTDI) Interface using the USB A to Mini - B Cable
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
Appendix 2: Jumper Locations
B1
3
2
1
R338
R369
DS20
R364
R253
9
J124
J121
C604
J32
J60
19
2
20
J38
1
19
R162
R330 C596
R260
U34
U23
C1
H1
R255
C600
U25
TP3
TP7 TP20
TP4
R283
R282
R155
U59
C697 C696
J123
J29
TP35
U31
H40
10
J37
20
R161
J125
DS0
DS1
DS2
D7
C40
1
J36
C610
J28
C638
R267 DS16
U24
SW1
2
C332
B
TP16
R151 R147
SW4
R304
TP12
J351
D9
C593
2
H1
DS21
SW3
R277
C698
J119
B
SW2
A
R307
R148
DS19
R279
R278
R276
B
R306
C636
R305
C637
TP21
TP9
D8
DS3
DS4
DS5
DS7
DS6
R220
R222
R224
A
A
R366
R152
1
R272
C608
R149
C328
R363 R361
TP10 TP22
U32
C647
R310
DS18
1
Y11
R318
R362
R316
Y12
B
DS17 R292
DS25
3
DS29
R354
R1216
R1217
8
7
6
5
4
R159
R158
R337
R47
R48
R308
C640
U5
R336
U7
U35
C645
C646
C644
C641
C642
A1
U3
R335
SW5
R314
C109
C150
C236
C235
C199
C159
C116
C465
C467
C460
C455
TP68
TP41
U13
A1
A1
U2
R150
C643 C648
R311
R309
A1
R346
2
1
J116
A
DS24
C630
C119
C161
C233
C197
C118
C163
R213 R209
R266
U6
TP60
R210
TP53
C476
C562
R1213
C518
C468
C519
Y4
C371
TP74
R211
C153
C156
Y3
R1214
R1212 R1208
R1210 R1207
R1215
R1209
C554
C471
C530
C528
C526
C394
C521
TP66
A1
J353
R332
R351
R352
R355
R356
TP70 TP64 R217
C517
J118
TP73
C211
C210
C213
C212
C136
C135
C138
C137
C140
C139
C142
C141
C173
C172
C175
C174
C177
C176
C179
C178
C216
C215
C92
C91
C94
C93
C96
C95
C98
C378
C625
TP29
CON1
MH2
R353
R160
R977
R973
R974
D15
C382
TP27
C257
C246
R78
TP26
C463
C422
R375
R1211
C599
Y20
U4
TP77 C374
C703
C705
U1
J13
TP62
C671
C674
R294 C699
R289
A1
C704
C359 R378
DS23
3
2
6
TP11
DS22
R344
R345
J10
C113
C129
R54
R55
R69
TP49
C220
TP67
C362
TP56 R70
C360
TP58
C361
TP72
R286
L5
L6
U60
R288
J17
C624
R343
SW7
5
C691
J11
J12
J6
U58
TP17 R281
R280
R300
U26
U27
R808
U9
U11
C702
R840
R841
R842
R134
R131
C315
J23
R125
R133
U10
R126
C672
C701 TP28
C700
R130
R373
R374
U12
A1
R74R72
J18 R73 R71
J354
R143
R137
R139
R141
R138
J16
C324
C325
U49
C606
R396
TP1
R127
CR2
CR1
R136
C323
TP2
C316
5
C164
R298
1
P1
C605
R140
R142
DS26
C673
R111
R112
R293 R303 R75
C292
C330
C331
U37
J15
J21
C283 R81
R76
Y2
R156 R372
R114 C306
C282
R113
J4
4
R313
C692
J9
J5
J7
C484
R115
R110
R109
R108
R106
R107
C314
C313
R116
R117
R118
R119
R101
R102
R103
C255
C302
R97
C307 C308 C297 C295
J19
R270
R978
R975
R976
R1518
R50
C214
TP24 R46
J14
J20
TP71 TP46
J42
R301
J350
TP30
J8
TP48
C181
C148 R64 C183
R60
TP54
TP33 TP57
TP39
TP50
TP69 R58 C144 R59 C146
R331
TP42
TP44
TP76
R216
C102
C100
R42 TP40
R41
TP38
C103
TP36
TP51 C209
R40
C294
A1
C296
C89
C90
C305
C304
TP75
U8
R218
TP78
R100 TP15
R104 J22
R105
R92
R99
R91
R94
R79
C293
R93
R95
R96
R98
R121
R120
TP32
J54
TP31 R63
C626
C303
A1
A40
R290
R291
U28
L4
C926
R5484 R5483
R334
C1579
R333
D10
D14
D13
R327
R328
R326
U36
C1575
C1574
C1573
C1572
C1566
R199
R198
R197
R194
R193
R192
R177
DS28
J30
R839
MH1
U162
R179
R178
C623
L3
U17
Y6
U62
U19
CR3
R191
R190
R189
R188
R184
R183
R182
R181
J352
R1519 R295
C628
K1
K40
R257
R986
R984
R985
R983
DS11
DS12
DS13
DS14
DS8
DS9
DS10
CR4
U16
5
C351
1
J33
C592
X1
R196
U18
R163 C358 C357
B
LED9
R164
R167
R168
R325
R169
C668
R170
C666
R166
C667
R165
R171
R329
R172
C670
TP23 TP14
R173
R174
R176
R175
B1
DS27
A
C595 R243
J34
A1
SW6
B32
Figure 17 • SmartFusion2 Advanced Development Kit Silkscreen Top View
Figure 17 shows the jumper locations in the Advanced Development Kit board:
•
Jumpers highlighted in red are set by default.
•
The location of the jumpers in Figure 17 is searchable.
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In-System Programming Using USB OTG Controller Interface
Appendix 3: Error Codes
Table 4 • Error Codes
Define
Error Code
Description
#define MSS_SYS_CHAINING_MISMATCH
1u
Device contents mismatch
#define MSS_SYS_UNEXPECTED_DATA_RECEIVED
2u
Data is not supported
#define MSS_SYS_INVALID_ENCRYPTION_KEY
3u
Invalid encryption key
#define MSS_SYS_INVALID_COMPONENT_HEADER
4u
Invalid file header
#define MSS_SYS_BACK_LEVEL_NOT_SATISFIED
5u
corrupted /invalid bitstream
#define MSS_SYS_DSN_BINDING_MISMATCH
7u
corrupted /invalid bitstream
#define MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE
8u
corrupted /invalid bitstream
#define MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES
9u
Invalid Device capabilities
#define MSS_SYS_INCORRECT_DEVICE_ID
10u
Invalid Device id
#define MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER
11u
bitstream is not supported
#define MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR
12u
Verification is not allowed for input
bitstream
#define MSS_SYS_ABORT
127u
Operation aborted
#define MSS_SYS_NVM_VERIFY_FAILED
129u
eNVM verification failed
#define MSS_SYS_DEVICE_SECURITY_PROTECTED
130u
Device is secured
#define MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED
131u
Programming mode is not enabled.
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Appendix 4: Generating .spi Programming File using Libero
The following steps describe how to generate a .spi programming file using Libero:
1. Launch the Libero SoC software to open a Libero project for fabenvm.spi programming file. The
Libero design file is provided in
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_file\fabric_and
_envm.
2. Right-click Bitstream under Handoff Design for Production in the Design Flow tab, and click
Export... from the context menu.
Figure 18 • Configuring Export Bitstream
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In-System Programming Using USB OTG Controller Interface
3. On the Export Bitstream window, select the SPI file check box.
Figure 19 • Export Programming File Options window
4. Click OK.
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5. Double-click Export Bitstream under Handoff Design for Production in the Design Flow tab to
generate the .spi file (Figure 18 on page 27). Figure 20 shows the .spi file location in
Messages tab.
Figure 20 • .SPI File Location
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In-System Programming Using USB OTG Controller Interface
Appendix 5: Hardware Project Implementation Settings
The following hardware project settings are required to build the demo design:
•
Configuring the I/Os for Flash*Freeze Mode
•
Standby Clock Source Configuration
•
SoftConsole Project Generation
Configuring the I/Os for Flash*Freeze Mode
The Libero demo design configures M3_CLK to operate at 50 MHz, one UART interface (MMUART_0)
for serial communication and USB OTG as mass storage class host. The FPGA fabric is not operational
during Program or Verify operation as the device enters into Flash*Freeze (F*F). During F*F mode, the
fabric and I/Os are not available. Therefore, the MMUART_0’s RXD and TXD ports are configured using
the I/O Editor to be available during F*F mode, as shown Figure 21. The reset of OTG controller reset is
driven by GPIO_3_OUT through fabric. This I/O is configured to hold the last value during F*F mode.The
user has to Commit and Check the settings from the File menu after configuring the ports.
Figure 21 • Configuring MMUART_0 Ports to be Available During F*F
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Standby Clock Source Configuration
The standby clock source for the microcontroller subsystem (MSS) in F*F mode is configured to On-chip
50 MHz RC Oscillator using the Flash*Freeze Hardware Settings dialog box in the Libero SoC
software, as shown in Figure 22. A higher MSS clock frequency is required in F*F mode to meet the
MMUART baud rate requirements.
Figure 22 • Flash*Freeze Hardware Settings Dialog Box
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In-System Programming Using USB OTG Controller Interface
SoftConsole Project Generation
The firmware and SoftConsole project workspace can be generated by checking the Create Project and
selecting a Software IDE option in Libero project, as shown in Figure 23.
Figure 23 • Export Firmware Options
On successful firmware generation, the firmware and SoftConsole folders are generated at
<download_folder>\sf2_isp_using_usb_interface_demo_df\libero as specified in Location field of Export
Firmware dialog box, as shown in Figure 23.
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For software modifications, open the SoftConsole Project workspace (located at
<download_folder>\sf2_isp_using_usb_interface_demo_df\libero\SoftConsole\demo_MSS_CM3) using
SoftConsole IDE v3.4 SP1. Figure 24 shows SoftConsole Project workspace.
Figure 24 • SoftConsole Project Workspace
The SoftConsole workspace consists three projects.
•
demo_MSS_CM3_app:
This project displays the available programming files from USB mass storage device. This project
receives the bitstream from the host PC through UART interface and invokes the system
controller programming services.
•
demo_MSS_CM3_boot_loader:
This project implements the remapping of the eSRAM to Cortex-M3 processor code space after
copying the ISP code to eSARM from eNVM.
•
demo_MSS_CM3_hw_platform:
This project contains all the firmware and hardware abstraction layers that correspond to the
hardware design. This project is configured as a library and is referenced by
demo_MSS_CM3_app and demo_MSS_CM3_boot_loader application projects. The contents of
this folder get over-written every time the firmware is exported as shown in Figure 23 on page 32.
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In-System Programming Using USB OTG Controller Interface
Appendix 6: Implementing Workaround to Access Fabric
LSRAM after IAP or ISP Program Operation
The LSRAM write and read accesses are denied after implementing IAP or ISP program operation. The
workaround for this problem is to apply System Reset after IAP or ISP program operation.
Changes Required in Libero Design
Option 1: Creating SmartDesign
The following steps describe how to apply System Reset:
1. Choose File > New > SmartDesign.
2. Enter Name as Dev_Restart_after_ISP_blk in the Create New SmartDesign window.
3. Navigate to Libero Catalog to open Tamper Macro.
a. Drag-and-drop the Tamper Macro available in Libero Catalog to the
Dev_Restart_after_ISP_blk SmartDesign canvas, as shown in Figure 25.
Figure 25 • Tamper Macro
b. Select the Enable RESET Function check box in the Configuring Tamper 2_0 window.
c. Click OK. The System Reset is enabled.
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
Figure 26 • Tamper Macro Configuration Window
Figure 27 shows the TAMPER2_0 macro after configuration.
Figure 27 • Tamper Macro
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In-System Programming Using USB OTG Controller Interface
4. Instantiate the FSM Module provided in the design files. This FSM Logic performs 3 consecutive
address writes to the Two-Port Large SRAM with the known data pattern and then reads back
data from those 3 consecutive address locations to compare. If the read back data pattern does
NOT match with the written data pattern, then the FSM asserts the RESET_N input to Tamper
Macro, which in turn causes a System Reset. If the read back data pattern matches with the
written data pattern, then the FSM does not do anything. Follow the steps to add the FSM logic to
the PCIe IAP design,
a. Choose File > Import > HDL Source Files.
b. Browse to the following Ram_interface.v file location in the design files folder.
<download_folder>\sf2_isp_using_usb_interface_demo_df\Sourcefiles
c. Click the Dev_Restart_after_ISP_blk tab and drag-and-drop the Ram_interface component
from the Design Hierarchy to the Dev_Restart_after_ISP_blk SmartDesign canvas.
Figure 28 shows the Ram_interface component.
Figure 28 •
Ram_interafce FSM Component
After completing the IAP programming, the System Controller asserts POWER_ON_RESET_n to
FPGA fabric. This triggers the RESETn signal and initiates the state machine in the FSM module.
5. Drag-and-drop the Two-Port Large SRAM (TPSRAM) available in the Libero Catalog to the
Dev_Restart_after_ISP_blk SmartDesign canvas. Configure the TPSRAM with the following
settings:
–
–
–
36
Write Port
•
Depth: 64
•
Width: 8
Read Port
•
Depth: 64
•
Width: 8
Select Check REN check box
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DG0471: SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface - Libero SoC v11.6
Figure 29 •
Two-Port SRAM Configurator Window
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In-System Programming Using USB OTG Controller Interface
6. Make the connections for Tamper Macro, FSM, and TPSRAM, as shown in Figure 30.
Figure 30 •
Dev_Restart_after_ISP_blk SmartDesign
7. Click the demo_top tab and drag-and-drop the Dev_Restart_after_ISP_blk component from the
Design Hierarchy to the demo_top SmartDesign canvas.
8. Make the connection as shown in Figure 31 and generate demo_top SmartDesign. This
completes the implementation of the workaround.
Figure 31 •
demo_top SmartDesign
Note: This workaround is applicable for v11.5 software release or later, and must be implemented in the
Libero design, which is used to generate the .spi programming file. Older versions of Libero might
prune Tamper Macro during Synthesis. To avoid pruning, one of the recommended options is to
promote the DETECT_ATTEMPT signal of Tamper Macro to the top-level.
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Option 2: Importing the .cxf file in Libero Project
Another option to implement this workaround is to import the .cxf file for SmartDesign
Dev_Restart_after_ISP_blk. This .cxf file is provided with the design files and it has all the component
instantiations and connections mentioned in "Option 1: Creating SmartDesign"section on page 34 from
step 1 to 6.
The following steps describe how to import .cxf file to Libero project:
1. Choose File > Import > Others.
2. Browse to the following Dev_Restart_after_ISP_blk.cxf file location in the design files folder.
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files\LSRAM_
Workaround\component\work\Dev_Restart_after_ISP_blk
3. Browse to the following Ram_interface.v file location in the design files folder.
<download_folder>\sf2_isp_using_usb_interface_demo_df\Sourcefiles
4. Repeat Step 7 and Step 8 to instantiate Dev_Restart_after_ISP_blk in demo_top
SmartDesign.
Revision 7
39
List of Changes
The following table shows the important changes made in this document for each revision.
Date
Changes
Page
Revision 7
(October 2015)
Updated the design files in the document for Libero v11.6 software release (SAR
72882).
NA
Revision 6
(June 2015)
Updated the design files in the document for Libero v11.5 software release (SAR
68427).
NA
Revision 5
(March 2015)
Updated the document for Libero v11.5 software release changes (SAR 65133).
NA
Revision 4
(August 2014)
Updated the document for Libero v11.4 software release (SAR 59740).
NA
Revision 3
(May 2014)
Updated the document for Libero v11.3 software release (SAR 56662).
NA
Revision 2
(December 2013)
Updated "Description" section (SAR 53451).
Revision 1
(November 2013)
Updated the document for Libero v11.2 software release (SAR 52963).
NA
Revision 0
(October 2013)
Initial release.
NA
Revision 7
8
40
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
For Microsemi SoC Products Support, visit
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
http://www.microsemi.com/products/fpga-soc/fpga-and-soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected]
Revision 7
41
Product Support
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Visit About Us for sales office listings and
corporate contacts.
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected] Alternatively, within My Cases, select Yes
in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web
page.
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R e visio n 7
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as
custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and
has approximately 3,600 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2015 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
50200471-7/10-15
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