CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI

SmartFusion2 SoC FPGA and
IGLOO2 FPGA Characterization
Report for XAUI
CR0025 Report
February 04, 2016
Table of Contents
I. Introduction ................................................................................................................ 3
A.
B.
Overview ...................................................................................................................................... 3
Scope ........................................................................................................................................... 3
II. XAUI 802.3 Electrical Compliance Testing .............................................................. 3
A.
B.
Transmitter Testing ...................................................................................................................... 4
Receiver Testing .......................................................................................................................... 5
III. Microsemi Test Boards............................................................................................ 6
IV. Device Testing Samples.......................................................................................... 6
V. Electrical Device Testing ......................................................................................... 7
A. Electrical Testing Equipment/Software ........................................................................................ 7
B. Electrical Testing Environment .................................................................................................... 7
C. Testing Conditions ....................................................................................................................... 8
VI. XAUI Test Results Summary .................................................................................. 9
A.
B.
XAUI Transmitter Tests .............................................................................................................. 10
XAUI Receiver Testing ............................................................................................................... 13
VII Conclusion ............................................................................................................. 18
VIII. List of Changes .................................................................................................... 18
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
I. Introduction
A. Overview
®
®
The Microsemi SmartFusion 2 SoC field programmable gate array (FPGA) and IGLOO 2 FPGA device family
provides a fully embedded 10 Gigabit Attachment Unit Interface (XAUI). The XAUI is an interface to specialized
10 Gigabit Ethernet optical modules and system backplanes. It supports four SerDes transmit and four SerDes
receive channels for 8B/10B encoding. XAUI is commonly used as backplane in networking switches to connect line
cards to switch cards. This embedded XAUI block is part of the SerDesIF module which supports four lanes of
SerDes with data rates supported up to 3.125 Gbps. The number of SerDesIF modules on the SmartFusion2 SoC
FPGA and IGLOO2 FPGA depends on the device size. The smaller devices support a single SerDesIF with one XAUI
interface. The larger devices support up to four SerDesIF modules for a total of four XAUI interfaces. XAUI
performance is available on -1 speed grade devices in all temperature grades of SmartFusion2 SoC FPGA and
IGLOO2 FPGA products. More information on the SmartFusion2 SoC FPGA and IGLOO2 FPGA device family can be
found on the SmartFusion2 SoC FPGA and IGLOO2 FPGA Product Page at www.microsemi.com.
B. Scope
Complete testing and validation of specifications required by XAUI standards were conducted on the SmartFusion2
SoC FPGA and IGLOO2 FPGA device. This report provides the user community a summary of testing completed to
demonstrate compliance to the XAUI standard, as defined by the IEEE 802.3ae 10 Gigabit Ethernet Task Force. The
testing analyzed voltage, temperature, and process variations for XAUI electrical validation. This report serves as a
reference to specific testing used to provide high confidence that the devices will perform as expected in XAUI
specific systems.
II. XAUI 802.3 Electrical Compliance Testing
XAUI electrical testing was completed based on IEEE Standard 802.3-2008 Section 4 Clause 47
http://standards.ieee.org/getieee802/download/802.3-2008_section4.pdf. This document details physical layer
specifications required to meet the 10 GBs sublayer requirements. This report highlights the procedures and
conditions tested within the Microsemi factory to validate the device’s performance against the XAUI specifications.
3
A. Transmitter Testing
All tests were performed over process, voltage, and temperature variations at the 3.125 GBs data rate to cover XAUI
speeds per XAUI Specification on M2S050-FG896 sample units. De-embedding mathematically removes the effects
of unwanted portions of the PCB routing that would impede on the measured data by subtracting their contribution.
This produces a portrayal of the devices actual performance.The S-Parameter de-embedding for Tx was applied
during the Near-End measurements to remove board trace impairments.
Table 1 XAUI 802.3 Test Specifications
Transmitter Near-End Tests
Parameter
IEEE 802.3 Definition
Specification Value
Units
XAUI Baud
Verify that the Baud rate of the device is
within the conformance limits specified in
47.3.3.
3.125 GBaud +/- 100ppm
GBaud ppm
Verify the serial bit rate per 47.3.3
320
pS
2.3
V
-400
mV
<3
dB
XAUI Unit Interval
Driver Single-ended
Output Swing Maximum
Absolute Test (Tx+ and
Tx-)
Driver Single-ended
Output Swing Minimum
Absolute Test (Tx+ and
Tx-)
Transmitter Differential
Return Loss (Output
impedance)
Verify that the single-ended output swing of
the device is within the conformance
maximum and minimum limits specified in
Clause 47.3.3.2.
Confirm the output impedance is within the
limits of Clause 47.3.3.4.
Transmitter Far-End Tests
Driver Output Amplitude
Test
Verify that the driver differential output
amplitude of the device is within the
conformance limits specified in Clause
47.3.3.2.
Driver Eye Template
Test
Verify that the devices transmitter meets
the specified eye template requirements,
Clause 47 (multiple sub-clauses).
Complies to all eye mask
parameters including rise
and fall times
Total Jitter Test
To verify that the device conforms to the
jitter requirements specified in Clause
47.3.3.5.
< 550
mUI
< 370
mUI
Deterministic Jitter Test
mVp-p
800-1600
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
B. Receiver Testing
XAUI Receiver electrical tests conform to the XAUI Specification. All receiver tests were performed over process,
voltage, and temperature variations at the 3.125 GBs data rate to cover XAUI speeds per XAUI Specification on
M2S050-FG896 units. To provide the correct amount of ISI, the receive test includes running the signal through
several inches of board trace connected through SMP connectors. This ensures the signal as measured at the DUT
is stressed enough to meet XAUI requirements.
Table 2 Receiver Tests
Parameter
Jitter Tolerance
Margin
IEEE 802.3 Definition
Specification Value
Units
Verify XAUI Compliance Interconnect
definition specified in Clause 47.4.1, for
the purposes of this test suite, by
stressing the input receiver.
0.65
Tj amplitude
UIp-p
0.37 DJ minimum
UIp-p
0.55 RJ minimum
UIp-p
Included for all tests
–
As needed to achieve Tj 650
mUIp-p
–
Receiver coupling
AC coupled as defined in Clause
47.3.4.4
Sinusoidal Jitter(Sj)
–
Receiver Input
Return Loss
Verify the receiver’s differential mode
input impedance is within the limits of
Clause 47.3.4.5.
>10
Verify the receiver’s common mode
input impedance is within the limits of
Clause 47.3.4.5.
>6
dB
5
III. Microsemi Test Boards
Testing is performed on the Microsemi Signal Integrity Board (SI) that is equipped with a test socket and provides
connections to vary power supply conditions. To ensure the integrity of the characterization measurements, special
attention is given to the signal integrity of the high-speed serial channels. Detailed analysis ensures the board
performs as designed. The transmitter (Tx) and receiver (Rx) signal paths for each SerDes are carefully routed to
high-bandwidth SMP connectors to ensure good signal integrity and performance. The PCB channel is measured and
de-embedded when performing tests.
Figure 1 SmartFusion2 SoC FPGA and IGLOO2 FPGA Signal Integrity Board
IV. Device Testing Samples
Testing was conducted on a sample of devices representing process variations across silicon fabrication. These
devices were separated from a larger group of devices representing the worse-case corners to report the results. The
results are correlated as presented in the data as worst-case.
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
V. Electrical Device Testing
Bench test equipment was used for both of the Rx jitter and the Tx jitter and amplitude measurements.
A. Electrical Testing Equipment/Software

Agilent DSA91304A, 13GHz Real Time Scope or DSO93204A 32Ghz Real Time Scope

Agilent N5431A XAUI Automation Test Application, Version 1.24 or newer

Tektronix BERTScope BSA125C with BERTScope GUI

Tektronix BERTScope DPP125B, Digital Pre-emphasis Processor

Tektronix BERTScope CR12500A, Clock Recovery Module

Agilent E3648A 100W Dual Output Power Supply

Agilent N6701A Power Supply Mainframe

Four individually controlled P/S Modules

Silicon Thermal, Temperature Control Unit

Silicon Thermal Chiller CH400

Silicon Thermal Linear Power Supply PS190-L

Silicon Thermal Temperature Controller LB190-L

Silicon Thermal 31x31(mm) Thermal Head Adapter

SMA-to-SMA cables

SMA-to-SMP cables

Microsemi Engineering. Signal Integrity Board

Agilent 11742A DC blocks

Stanford Research Systems CG635 2.05 GHz Synthesized Clock Source
B. Electrical Testing Environment
Device electrical testing was conducted by the Microsemi factory using variations on power supply voltages and
temperatures. Minimum voltage (Vmin) and maximum voltage (Vmax) were varied by +/-5% of the typical voltage
(Vtyp) supply for the supplies related to the XAUI and SerDes blocks of the device. The devices were also tested at
the industrial temperature limits (-40ºC to +125ºC).
Table 3 Temperature Specifications
Specifcation
Temperature Range
Military Temperatures
-55ºC to 125ºC
Industrial Temperatures
-40ºC to 100ºC
Commercial temperatures
0ºC to 85ºC
7
C. Testing Conditions
Table 4
Power Supply and Temperature Test Conditions
Voltage and Temperature Matrix
Voltage Dependencies
1.2V VDD range
xDDR_PLL_VDDA
3.15 V
3.3 V
3.45 V
3.15 V
3.3 V
3.45 V
CCC_xyz_PLL_VDDA
2.375 V
2.5 V
2.625 V
3.15 V
3.3 V
3.45 V
SERDES_x_PLL_VDDA
2.375 V
2.5 V
2.625 V
3.15 V
3.3 V
3.45 V
SERDES_x_L[0:3]VDDAPLL
2.375 V
2.5 V
2.625 V
2.375 V
2.5 V
2.625 V
SERDES_x_L[0:3]VDDAIO
1.14 V
1.2 V
1.26 V
1.14 V
1.2 V
1.26 V
SERDES_x_VDD
1.14 V
1.2 V
1.26 V
1.14 V
1.2 V
1.26 V
VDD (Core Supply)
1.14 V
1.2 V
1.26 V
1.14 V
1.2 V
1.26 V
-55ºC
-55ºC
-55ºC
-55ºC
-55ºC
-55ºC
-40ºC
-40ºC
-40ºC
-40ºC
-40ºC
-40ºC
0ºC
0ºC
0ºC
0ºC
0ºC
0ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
85ºC
85ºC
85ºC
85ºC
85ºC
85ºC
100ºC
100ºC
100ºC
100ºC
100ºC
100ºC
125ºC
125ºC
125ºC
125ºC
125ºC
125ºC
Temperatures
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
VI. XAUI Test Results Summary
Table 5 Summary of Test Results
IEEE 802.3 Clause 47 Specification
SmartFusion2
and IGLOO2
Device
Worst Case
Test
Parameter
Specifications
Unit
Pass/Fail
Test Results
Transmitter Testing
Baud Rate
Within
Range
-100.000 Bd ppm <= VALUE
<= 100.000 Bd ppm
-4.8
ppm
Pass
VALUE <= 2.300 V
209
mV
Pass
VALUE >= -400 mV
-230
mV
Pass
VALUE <= 2.300 V
206
mV
Pass
VALUE >= -400 mV
-231
mV
Pass
Driver Single-ended Output
Swing Maximum Absolute Test
(Tx+) (Near-end)
Maximum
Driver Single-ended Output
Swing Minimum Absolute Test
(Tx+) (Near-end)
Minimum
Driver Single-ended Output
Swing Maximum Absolute Test
(Tx-) (Near-end)
Maximum
Driver Single-ended Output
Swing Minimum Absolute Test
(Tx-) (Near-end)
Minimum
Driver Output Amplitude Test
(Far-end)
Within
Range
0.200 V <= VALUE <= 1.600 V
674
mV
Pass
Driver Eye Template Test
(Far-end)
N/A
Zero Mask Failures
N/A
N/C
Pass
Total Jitter Test (Far-end)
Maximum
VALUE <= 550 mUI
168
mUI
Pass
Deterministic Jitter Test
(Far-end)
Maximum
VALUE <= 370 mUI
135
mUI
Pass
Differential Return Loss
Maximum
VALUE <3
<3
dB
Pass
Total Jitter (Tj)
Maximum
650 mUIp-p
<650
mUI
Pass
Deterministic Jitter (Dj)
Maximum
370 mUIp-p
<370
mUI
Pass
Deterministic + Random Jitter
(Dj+Rj)
Maximum
550 mUIp-p
<550
mUI
Pass
–
As needed to achieve Tj 650
mUIp-p
–
mUI
Pass
Differential Return Loss
Minimum
>10
>10
dB
Pass
Common Mode Return Loss
Minimum
>6
>6
dB
Pass
Receiver Testing
Sinusoidal Jitter (Sj)
9
A. XAUI Transmitter Tests
XAUI Transmitter Test Setup
The characterization has been performed in accordance with XAUI Specification for Near-End and Far-End
measurements. The transmitter near-end jitter is measured at a load terminated driver output. The XAUI RefCLK is
taken from the external clock source generator. The signal is driven from a test signal source generating a CJPAT
test pattern. CJPAT is a binary pattern sequence that exposes a receiver’s CDR to large instantaneous phase jumps.
The pattern alternates repeating low- transition density patterns with repeating high- transition density patterns.
A sample of devices was tested over voltage and temperature and represents the worst case condition for the
transmitter tests. The worst test condition identified was determined to be at Temperature = -55ºC and at Voltage at
Vmax.
Figure 2 Transmitter Test Setup
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
The Total and deterministic jitter are as shown in Figure 3 and Figure 4.
40
35
30
Datapoint
25
20
15
10
5
0
Tx Total Jitter (mUI)
Figure 3 Total Jitter Histogram
35
30
25
15
10
5
0.150
0.145
0.140
0.135
0.130
0.125
0.120
0.115
0.110
0.105
0.100
0.095
0.090
0.085
0.080
0.075
0.070
0.065
0.060
0.055
0
0.050
Datapoints
20
Tx Deterministic Jitter (mUI)
Figure 4 Deterministic Jitter Histogram
Table 6 Worse Case Transmit Jitter Summary
Min
Max
Mean
Interval
Total Jitter
Jitter
97
141
117
mUI
Deterministic Jitter
67
115
90
mUI
11
Figure 5 XAUI Jitter Decomposition of Transmitter using CJPAT
Figure 6 Transmit Eye Mask
Table 7 Transmit Eye Intervals
Symbol
Near-end Value
Far-end Value
Units
X1
0.175
0.275
UI
X2
0.390
0.400
UI
A1
400
100
mV
A2
800
800
mV
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
Figure 7 Transmit Eye Diagram with Far-end Mask
B. XAUI Receiver Testing
XAUI Receiver Test Setup
A XAUI Compliance Channel setup is used for the XAUI Receiver testing per Clause 47.3.4.2. The objective of the
test is to provide a stressed input signal to the device and still have the receiver operate with a BER (bit-error rate) of
-12
better than 10 .
The BERTScope, DPP, and Clock Recovery are interconnected together to provide a necessary signal generator for
XAUI receiver testing. The XAUI receiver channel is pre-conditioned with a calibrated setup including a 55” (ISI)
backplane trace that is combined with test board trace between SMP and DUT’s package to generate required 370
mUI of Dj. This setup guarantees calibration of the XAUI Compliant Stressed Eye to the Rx package balls of the
device.
The XAUI Receiver setup uses Common RefCLK topology by having RefCLK driven by the BERTScope.
13
Figure 8 XAUI Receiver Test Setup
Note:
ISI Channel = 55 Inches
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
Figure 9 Stress Input Signal
Table 8 Stressed Input Eye Jitter Components
Jitter Measurement
Value
Unit
Data Rate
3.1249
Gb/s
TJ(1E-12)
644.7
mUI
RJ-rms
19.2
mUI
PJ-rms
51.2
mUI
DDJ-pp
246.5
mUI
ISI-pp
284.3
mUI
DCD
23.6
mUI
The stressed input signal must meet the far-end eye mask while introducing the required jitter components. Figure 7
on page 13 shows the stressed eye and the reported jitter components. The signal is driven from a test signal source
generating a CJPAT test pattern. CJPAT is a binary pattern sequence that exposes a receiver’s CDR to large
instantaneous phase jumps. The pattern alternates repeating low- transition density patterns with repeating hightransition density patterns. The purpose of the test is to feed in a jittery signal while observing the receiver's lock
status, stability, and data BER. The receiver must be AC coupled, and the input is measured at the pin of the
receiver.
Additional sinusoidal jitter is added from the BERTScope tester and swept as a function of frequency to the point
where the device starts to fail. The BER is compared to a jitter tolerance mask where jitter is applied to the stressed
input channel. Figure 8 on page 14 plots the results of the sample devices in comparison to the XAUI specified mask.
15
Figure 10 Single Tone Sinusoidal Jitter Mask
10000
Jitter (ps)
1000
100
10
1
0.1
0.001 0.002 0.005 0.01 0.022 0.05
0.1
0.2
0.5
1
1.875
5
10
20
Figure 11 Sinusoidal Jitter Tolerance Test Plot
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
Return Loss
The primary effect of return loss relates to the amount of signal being transferred to the receiver causing closure of
the eye. Multiple reflections, caused by the finite return loss of driver in conjunction with the channel, introduce
additional amplitude distortion as well as jitter. Return loss measurements of the SmartFusion2 SoC FPGA and
IGLOO2 FPGA include the contributions from the on-chip, off-chip, and package components of both the receiver and
the transmitter. The receiver tests included AC coupling capacitors. The tests used frequency domain return loss
measurements, where the loss is measured while sweeping the frequency from 100 MHz to 5 GHz.
Figure 12 Tx Return Loss Plot
Figure 13 Rx Return Loss
17
VII Conclusion
The test results demonstrate the capabilities of the SmartFusion2 SoC FPGA and the IGLOO2 FPGA XAUI solution.
XAUI systems require high reliability requiring devices to be robust. The report provides a baseline summary of the
thorough testing performed by the Microsemi factory to assure users that the device will meet the performance and
functional requirements in their customized XAUI application.
VIII. List of Changes
The following table shows important changes made in this document for each revision.
Revision
Changes
Revision 2
(February 2016)
Updated Overview Section (SAR 71993).
Revision 1
(May 2015)
Initial revision
Page
3
N/A
CR0025: SmartFusion2 SoC FPGA and IGLOO2 FPGA Characterization Report for XAUI
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
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51000025-2/02.16
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