DG0568: Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through MDDR Controller - Libero SoC v11.7 Demo Guide

Interfacing SmartFusion2 SoC FPGA with
External LPDDR Memory through MDDR
Controller - Libero SoC v11.7
DG0568 Demo Guide
Contents
1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through MDDR
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Demo Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.1
Demo Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.1.1
MDDR_Demo_top_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.1.2
UART_IF_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Running the Demo using Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.2
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.3
Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting Up the Hardware Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Programming the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7.1
Setting Up the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7.2
Programming the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7.3
Running the Hardware Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.4
Steps to Run GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7.5
Performing a Single Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7.6
Performing Burst Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Appendix: Configuring MDDR Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1
MDDR Configuration Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2.1
Memory Timing: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
30
31
4 Appendix: Finding Correct COM Port Number when Using the USB 3.0 . . . . . . . . 32
5 Appendix: Performing Write/Read Operation when Non 64-Bit Aligned Address is
Provided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1
7.2
7.3
7.4
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 5
37
37
37
37
2
7.5
7.6
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 5
37
37
37
38
38
3
Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Demo Design Files Top-Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SmartFusion2 MDDR Demo Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SF2_MDDR_Demo SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MDDR_Demo_top_0 SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
UART_IF_0 SmartDesign Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AXI_LPDDR_Simulation SmartDesign Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DO File Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Waveforms Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Invoking Organize Stimulus Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Organize Stimulus Files Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Simulation Completed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Single Write and Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16-Beat AXI Burst Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SmartFusion2 Security Evaluation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
USB Serial 2.0 Port Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FlashPro New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FlashPro Project Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FlashPro Program Passed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SF2_MDDR_Demo Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SF2_MDDR_Demo – Connection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Single Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clear Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Single Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Burst Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System Builder - Memories - MDDR Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
System Builder MDDR Configuration – General Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
System Builder MDDR Configuration – Memory Initialization Tab . . . . . . . . . . . . . . . . . . . . . . . . . 30
System Builder MDDR Configuration – Memory Timing Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB 3.0 Serial Port Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Read Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Non 64-Bit Aligned Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Converted 64-Bit Aligned Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision 5
4
Tables
Table 1.
Table 2.
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SmartFusion2 Security Evaluation Kit Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision 5
5
Preface
1
Preface
1.1
Purpose
This demo guide is for SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA)
devices. It provides instructions on how to use the corresponding reference design.
1.2
Intended Audience
This demo guide is intended for:
•
•
•
1.3
FPGA designers
System-level designers
Embedded designers
References
See the following web page for a complete and up-to-date listing of the SmartFusion2 device
documentation: http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#documentation.
•
•
•
UG0446: SmartFusion2 SoC FPGA and IGLOO2 FPGA High Speed DDR Interfaces User Guide
SmartFusion2 System Builder User Guide
UG0594: M2S090TS-EVAL-KIT SmartFusion2 Security Evaluation Kit User Guide
Revision 5
6
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2
Interfacing SmartFusion2 SoC FPGA with
External LPDDR Memory through MDDR
Controller
2.1
Introduction
This demo shows the microcontroller subsystem (MSS) double-data rate (DDR) controller accessing the
external DDR SDRAM memories in the SmartFusion2 devices. The demo has two parts:
•
•
Demo using simulation
Demo using the SmartFusion2 Security Evaluation Kit
In the demo design, the advanced eXtensible interface (AXI) Master in the FPGA fabric accesses the low
power DDR (LPDDR) memory present in the SmartFusion2 Security Evaluation Kit board using the
microcontroller subsystem DDR (MDDR) controller. A utility, SF2_MDDR_Demo is provided along with the
demo deliverables. Using the utility, you can drive the AXI Master logic. The AXI Master converts the
commands from the utility to AXI transactions for the MDDR controller to perform the read/write
operations on the LPDDR memory.
2.2
Design Requirements
Table 1 shows the hardware and software design requirements.
Table 1 • Design Requirements
Design Requirements
Description
Hardware Requirements
SmartFusion2 Security Evaluation Kit:
• FlashPro4 programmer
• 12 V adapter
• USB A to Mini-B cable
Rev D or later
Host PC or Laptop
Any 64-bit Windows Operating System
Software Requirements
Libero® System-on-Chip (SoC)
v11.7
FlashPro programming software
v11.7
SoftConsole
v3.4 SP1*
Microsoft .NET Framework 4
–
Host PC Drivers
USB to UART drivers
Note: *For this demo guide, SoftConsole v3.4 SP1 is used. For using SoftConsole v4.0, see the TU0546:
SoftConsole v4.0 and Libero SoC v11.7 Tutorial.
Revision 5
7
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.3
Demo Design
2.3.1
Introduction
The demo design files are available for download from the following path in the Microsemi website:
http://soc.microsemi.com/download/rsc/?f=m2s_dg0568_liberov11p7_df
Design files include:
•
•
•
•
•
Demo_utility
Libero_project
•
SF2_MDDR_Demo
Programming_file
Source_files
readme.txt
Figure 1 shows the top-level structure of the design files. For further details, see the readme.txt file.
Figure 1 • Demo Design Files Top-Level Structure
GRZQORDGBIROGHU!
6)B0''5B'HPRB')
'HPRBXWLOLW\
/LEHURBSURMHFW
6)B0''5B'HPR
3URJUDPPLQJBILOH
6RXUFHBILOHV
UHDGPHW[W
In the demo design, the AXI Master implemented in the FPGA Fabric accesses the LPDDR memory
present in the SmartFusion2 Security Evaluation Kit board using the MDDR controller. The AXI Master
logic communicates to the MDDR controller through Core AXI interface and the DDR_FIC interface. The
read/write operations initiated by the SF2_MDDR_Demo utility are sent to the UART_IF block using the
UART protocol. The AXI Master receives the address and the data from the UART_IF block. During a
write operation, the UART_IF block sends the address and data to the AXI Master logic.
During a read operation, the UART_IF block sends the address to the AXI Master and stores the read
data in two port static random-access memory (TPSRAM). When the read operation is complete, the
read data is sent to the host PC through UART.
Revision 5
8
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 2 shows the top-level view of demo design.
Figure 2 • SmartFusion2 MDDR Demo Block Diagram
8$57&RPPXQLFDWLRQ
008$57
'
'
5
,
2
/3''5
6'5$0
'
'
5
3
+
<
0''5
''5
&RQWUROOHU
$;,
7UDQVDFWLRQ
&RQWUROOHU
$3%
&RUWH[0
8VHU*8,
,QWHUIDFH
H190
+RVW3&
''5B),&
$3%&RQILJ
5HJ
$+%%XV0DWUL[
),&B
),&B
066
&RUH&RQILJ3
&RUH$;,
$;,B0DVWHU
'$7$+$1'/(B)60
8$57B,)
8$57B,)B)60
7365$0
)3*$)DEULF
6PDUW)XVLRQ
In this demo design, different blocks are configured as shown below:
•
•
•
•
MDDR controller is configured for LPDDR memory available in the SmartFusion2 Security
Evaluation Kit board. The LPDDR memory is a Micron DRAM (Part Number: MT46H32M16LF)
DDR_FIC is configured for AXI bus interface.
Both AXI clock and LPDDR clock are configured for 160 MHz.
TPSRAM IP has the following configuration:
•
Write port depth: 256
•
Write port width: 64
•
Read port depth: 2048
•
Read port width: 8
See "Appendix: Configuring MDDR Controller" on page 28 for information on how to configure the DDR
controller.
2.4
Demo Design Features
The SmartFusion2 MDDR demo design has the following features:
•
•
•
•
•
Single AXI read or write transactions
16-beat burst AXI read or write transactions
LPDDR memory model simulation using SmartDesign testbench
Design validation using the SmartFusion2 Security Evaluation Kit board that has the LPDDR
memory
Initiation of the read or write transactions using SF2_MDDR_Demo utility
Revision 5
9
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.4.1
Demo Design Description
The demo design consists of the following SmartDesign components:
•
•
MDDR_Demo_top_0: This SmartDesign handles the data transactions between the MDDR
controller and LPDDR SDRAM.
UART_IF_0: This SmartDesign handles the communication between the host PC and the
SmartFusion2 Security Evaluation Kit board.
Figure 3 shows the MDDR_Demo_top_0 and UART_IF_0 connections.
Figure 3 • SF2_MDDR_Demo SmartDesign
2.4.1.1 MDDR_Demo_top_0
This consists of the MDDR_Demo_0 subsystem generated using the System Builder and the AXI_IF_0
master logic. The AXI_IF_0 master logic is an RTL code that implements the AXI read and write
transactions. It receives the read or write operations, burst length (RLEN and WLEN), address and data
as inputs. Based on inputs received, it communicates with the LPDDR memory through the MDDR
controller.
Revision 5
10
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 4 shows the MDDR_Demo_top_0 SmartDesign component.
Figure 4 • MDDR_Demo_top_0 SmartDesign Component
2.4.1.2 UART_IF_0
The UART_IF_0 SmartDesign component handles the communication between the host PC demo utility
and the AXI Master logic. The MMUART_1 block present in the MSS receives the UART signals from the
host PC user interface, the ARM® Cortex®-M3 processor sends this user data to the
DATAHANDLE_FSM block present in the FPGA fabric using the FIC_0 advanced peripheral bus (APB)
slave interface. DATAHANDLE_FSM is an APB slave wrapper, which sends the received data to the
UART_IF_FSM_0 block.
For a single write operation, the UART_IF_FSM_0 wrapper receives the address and data from the
demo utility. For a burst write operation, the address and data are received from the demo utility and the
subsequent incremental data are provided by the UART_IF_FSM_0 wrapper.
For a burst read operation, UART_IF_FSM_0 collects the address from the demo utility and sends that to
the AXI_IF_0 master logic. It then receives the read data from the AXI_IF_0 master logic and stores it in
the TPSRAM_0. After completion of the read burst transactions, the Cortex-M3 processor reads the
TPSRAM_0 buffer through DATAHANDLE_FSM (APB wrapper) block. The received data is sent to the
host PC using the MMUART_1 block.
Revision 5
11
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 5 shows the UART_IF_0 SmartDesign component.
Figure 5 • UART_IF_0 SmartDesign Component
2.5
Running the Demo using Simulation
2.5.1
Introduction
The demo design can be simulated using SmartDesign testbench and the LPDDR memory model
(MT46H32M16LF with 512 Mb density).
The simulation is set to run the following:
•
•
Single AXI write and read operation
16-beat AXI burst write and read operation
Revision 5
12
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 6 shows the AXI_LPDDR_Simulation SmartDesign testbench. The AXI_testbench provides the
read or write operations, burst length, address, and data to the MDDR_Demo_top_0 SmartDesign
component.
Figure 6 • AXI_LPDDR_Simulation SmartDesign Testbench
To run simulation, ensure that the following files are present in the Libero SoC project:
•
•
•
dram.v
dram_parameters.vh
AXI_testbench.v
The default location of the files is:
<Download folder>\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\stimulus
Revision 5
13
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.5.2
Simulation
Simulation setup configuration can be set properly using the following steps:
1.
2.
3.
4.
Launch the Libero SoC software.
Browse the SF2_MDDR_Demo project provided in the design file.
Go to Project > Project Settings > Simulation Options.
Ensure that the DO File tab has the configuration as shown in Figure 7.
Figure 7 • DO File Settings
5.
Ensure that the Waveforms tab has the configuration as shown in Figure 8.
Figure 8 • Waveforms Settings
Revision 5
14
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
6.
7.
Go to Design Flow tab.
Right-click Simulate under Verify Pre-Synthesized Design and then select, Organize Input Files
> Organize Stimulus Files as shown in Figure 9.
Figure 9 • Invoking Organize Stimulus Files Window
8.
Ensure that the Organize Stimulus files window has the configuration as shown in Figure 10.
Figure 10 • Organize Stimulus Files Window
Revision 5
15
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.5.3
Running the Simulation
The following steps describe how to run the simulation:
1.
2.
3.
Right-click Simulate under Verify Pre-Synthesized Design.
Click Open Interactively.
Simulation requires 900 µs to complete as mentioned in the 3rd point under "Simulation" section on
page 14.
Figure 11 shows the transcript window of the simulation.
Figure 11 • Simulation Completed
Revision 5
16
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 12 shows the single AXI write and AXI read operation.
Figure 12 • Single Write and Read Operation
Figure 13 shows the 16-beat AXI burst write and read operation.
Figure 13 • 16-Beat AXI Burst Write and Read
Revision 5
17
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.6
Setting Up the Hardware Demo
The following steps describe how to setup the hardware demo:
1.
Connect the jumpers on the SmartFusion2 Security Evaluation Kit as listed in Table 2.
Table 2 • SmartFusion2 Security Evaluation Kit Jumper Settings
Jumper
Pin (From)
Pin (To)
Comments
J22
1
2
Default
J23
1
2
Default
J24
1
2
Default
J8
1
2
Default
J3
1
2
Default
CAUTION: Ensure that the power supply switch SW7 is switched off while connecting the jumpers.
2.
3.
4.
Connect the Power supply to the J6 connector, switch on the power supply switch, SW7.
Connect the FlashPro4 programmer to the J5 connector of the SmartFusion2 Security Evaluation
Kit.
Connect the host PC USB port to the SmartFusion2 Security Evaluation Kit board’s J18 USB
connector using the USB mini-B cable.
Figure 14 shows the board setup for running the SmartFusion2 MDDR demo on the SmartFusion2
Security Evaluation Kit.
Figure 14 • SmartFusion2 Security Evaluation Kit
Revision 5
18
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
5.
Ensure that the USB to UART bridge drivers are automatically detected. This can be verified in the
Device Manager of the host PC. The FTDI USB to UART converter enumerates four COM ports.
For USB 2.0, note down the USB Serial Converter D COM port number to use it in the GUI.
Figure 15 shows the USB 2.0 Serial port properties. As shown in Figure 15, COM7 is connected to
USB Serial Converter D. See "Appendix: Finding Correct COM Port Number when Using the USB
3.0" on page 32 for finding the correct COM port in USB 3.0.
Figure 15 • USB Serial 2.0 Port Properties
6.
If the USB to UART bridge drivers are not installed, download and install the drivers from
www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip.
Revision 5
19
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.7
Programming the Demo Design
The following steps describe how to program the demo design:
1.
2.
3.
4.
5.
6.
7.
8.
Download the demo design from the following link:
http://soc.microsemi.com/download/rsc/?f=m2s_dg0568_liberov11p7_df
Switch ON the power supply switch SW7.
Launch the FlashPro software.
Click New Project.
In the New Project window, type the project name as SF2_MDDR_Demo.
Click Browse and navigate to the location where you want to save the project.
Select Single device as the Programming mode.
Click OK to save the project.
Figure 16 • FlashPro New Project
Revision 5
20
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.7.1
Setting Up the Device
The following steps describe how to configure the device:
1.
2.
3.
Click Configure Device on the FlashPro GUI.
Click Browse and navigate to the location where the SF2_MDDR_Demo.stp file is located and select
the file. The default location is:
<download_folder>\SF2_MDDR_Demo_DF\Programming_file\.
Click Open. The required programming file is selected and is ready to be programmed in the device.
Figure 17 • FlashPro Project Configuration
Revision 5
21
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.7.2
Programming the Device
Click PROGRAM to start programming the device. Wait until Programmer Status is changed to RUN
PASSED.
Figure 18 • FlashPro Program Passed
Revision 5
22
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.7.3
Running the Hardware Demo
The SmartFusion2 MDDR demo comes with utility, SF2_MDDR_Demo that runs on the host PC to
communicate with the SmartFusion2 Security Evaluation Kit board. The UART protocol is used as the
underlying communication protocol between the host PC and the SmartFusion2 Security Evaluation Kit
board. Figure 19 shows the initial screen of the SF2_MDDR_Demo utility.
Figure 19 • SF2_MDDR_Demo Utility
The SF2_MDDR_Demo utility has the following sections:
•
•
•
•
•
Serial Port Configuration: Displays the serial port. Baud rate is fixed at 115200.
Data Transfer Type: Single or Burst.
LPDDR SDRAM: Provides Address and Data.
LPDDR Burst Read: Displays the Burst Read Values for the corresponding address.
C: Clears the existing data.
Revision 5
23
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
2.7.4
Steps to Run GUI
The following steps describe how to run the GUI:
1.
2.
3.
Launch the utility. The default location is:
<download_folder>\\SF2_MDDR_Demo_DF\Demo_Utility\SF2_MDDR_Demo.exe.
Select the appropriate COM port from drop down menu. In this case, it is COM 7.
Click Connect. The connection status along with the COM Port and Baud rate is shown in the left
bottom corner of the screen. Figure 20 shows the connection status of the utility.
Figure 20 • SF2_MDDR_Demo – Connection Status
2.7.5
Performing a Single Data Transfer
For a single write or read operation, the AXI Master logic is configured to transfer a burst length of 1 (that
is, 8 bytes). For a write operation, the utility sends a 32-bit address and 64-bit (8 bytes) data. The data is
then written to the LPDDR SDRAM. For a read operation, the utility sends a 32-bit address and receives
64-bit data from LPDDR and is displayed in the utility.
The following steps describe how to perform a single data transfer:
1.
2.
3.
4.
Select the Data Transfer Type as Single (8 bytes).
A 64-bit aligned address is required in the address field. Enter a 32-bit HEX Address in the range
0x00000000 - 0x03FFFFF8. When a non 64-bit aligned address is provided, the GUI converts it to
64-bit aligned address and performs the write or read. See "Appendix: Performing Write/Read
Operation when Non 64-Bit Aligned Address is Provided" on page 34 to perform write or read when
non 64-bit aligned address is provided.
In the Data field, enter a 64-bit data in HEX format.
Click Write. The entered data is written to the LPDDR memory.
Revision 5
24
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 21 shows the Address and Data values entered for a Single Write operation.
Figure 21 • Single Write Operation
5.
6.
To verify the write operation, perform a read operation to the same address where the data was
written.
Press C to clear the data present in the Data field. Figure 22 highlights the Clear button, C.
Figure 22 • Clear Data Field
7.
Click Read to read the data from the LPDDR SDRAM.
Revision 5
25
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 23 shows the data read from the LPDDR SDRAM.
Figure 23 • Single Read Operation
8.
2.7.6
Compare the read and write data. The write and read data being same establishes that the write and
read operations to the LPDDR SDRAM were successful.
Performing Burst Data Transfer
For a burst write or read operation, the AXI Master logic is configured to transfer a burst length of 16 (that
is, 128 bytes). In this demo, 16 transfers of 16-beat burst operations is implemented, that is, 16
(transfers) x 16-beat burst data = 2048 bytes data). For a write operation, the utility sends a 32-bit initial
address and 64-bit (8 bytes) initial data. After the initial write operation, incremental data is written. For a
read operation, the utility sends a 32-bit address and receives 2048 bytes of data from the LPDDR
SDRAM and the data is displayed in the utility.
The following steps describe how to perform a burst data transfer:
1.
2.
3.
4.
Select the Data Transfer Type as Burst (2048 bytes).
A 64-bit aligned address is required in the address field. Enter a 32-bit HEX Address in the range
0x00000000 - 0x03FFF7F8. When a non 64-bit aligned address is provided, the GUI converts it into
64-bit aligned address and performs the write or read operation. See "Appendix: Performing
Write/Read Operation when Non 64-Bit Aligned Address is Provided" on page 34 to perform write or
read when non 64-bit aligned address is provided.
In the Data field, enter a 64-bit data in HEX format.
Click Write. The entered data is written to the Address location specified in the Address filed and
then the data is incremented by 1 and written to the next address location. This is repeated 256
times to write all the 2048 bytes of data.
Revision 5
26
Interfacing SmartFusion2 SoC FPGA with External LPDDR Memory through
MDDR Controller
Figure 24 shows the Address and Data values entered for a Burst Write operation.
Figure 24 • Burst Write Operation
5.
6.
To verify the write operation, perform a read operation to the same address where the data was
written.
Click Read. All the 2048 bytes of data that was written to the LPDDR was read and the read data
was displayed in the LPDDR Burst Read panel. Figure 25 shows the burst read data.
Figure 25 • Burst Read Operation
7.
2.8
Click Exit to exit the utility.
Conclusion
This demo shows how to perform Read or Write operations to LPDDR SDRAM using the SmartFusion2
MDDR controller. Options are provided to simulate the design using a SmartDesign testbench and
validate the design on the SmartFusion2 Security Evaluation Kit using a GUI interface.
Revision 5
27
Appendix: Configuring MDDR Controller
3
Appendix: Configuring MDDR Controller
This section describes how to configure the MDDR controller registers using Libero SoC. The
configuration options for MDDR are available at the MDDR tab of the Memories tab in System Builder.
The SmartFusion2 Security Evaluation Kit has the LPDDR memory from Micron. All values provided here
are from the Micron datasheet; part number, MT46H32M16LF.
Note: The Automotive Mobile Low-Power DDR SDRAM Datasheet is available for download from Micron
website.
Figure 26 shows the MDDR tab.
Figure 26 • System Builder - Memories - MDDR Tab
3.1
MDDR Configuration Tab
When using an external memory, the memory controller must wait for the memory to initialize (settling
time) before accessing it. The SmartFusion2 Security Evaluation Kit uses the LPDDR memory.
Therefore, the DDR controller has to wait at least 200 µs. Provide 200 as the value for the field, DDR
memory settling time (us).
Note: All the values provided here are from the Micron datasheet. The parameters can be configured according
to the user requirements.
Revision 5
28
Appendix: Configuring MDDR Controller
3.1.1
General
This section shows the configurations of the General tab.
•
•
•
Memory Type: LPDDR
Data Width: 16
Address Width (bits)
•
Row: 16
•
Bank: 2
•
Column: 10
Figure 27 shows the General tab after configuration parameters are set.
Figure 27 • System Builder MDDR Configuration – General Tab
Revision 5
29
Appendix: Configuring MDDR Controller
3.1.2
Memory Initialization
This section shows the configurations of the Memory Initialization tab.
•
•
•
•
•
•
•
•
•
•
Burst length: 8
Burst Order: Sequential
Timing Mode: 1T
CAS Latency: 3
Self Refresh Enabled: NO
Auto Refresh Burst Count: 8
Power Down Enabled: YES
Stop the clock: NO
Deep Power Down enabled: NO
No Activity clocks for Entry: 320
Figure 28 shows the Memory Initialization tab after configuration parameters are set.
Figure 28 • System Builder MDDR Configuration – Memory Initialization Tab
Revision 5
30
Appendix: Configuring MDDR Controller
3.1.2.1 Memory Timing:
This section shows the configurations of the Memory Timing tab.
•
•
•
•
•
•
•
•
•
•
•
•
Time To Hold Reset Before INIT – 0
MRD: 4
RAS (Min): 8
RAS (Max): 8192
RCD: 6
RP: 7
REFI: 3104
RC: 12
XP: 3
CKE: 3
RFC: 79
FAW: 0
Figure 29 shows the Memory Timing tab after configuration parameters are set.
Figure 29 • System Builder MDDR Configuration – Memory Timing Tab
Revision 5
31
Appendix: Finding Correct COM Port Number when Using the USB 3.0
4
Appendix: Finding Correct COM Port Number
when Using the USB 3.0
FTDI USB to UART converter enumerates the four COM ports. In USB 3.0, the four available COM ports
are in Location 0. Figure 30 shows the USB 3.0 Serial port properties.
Figure 30 • USB 3.0 Serial Port Properties
Revision 5
32
Appendix: Finding Correct COM Port Number when Using the USB 3.0
To find out the correct COM port, program the SmartFusion2 Security Evaluation Kit board with provided
programming file. Connect each available COM port and click Write. If wrong COM port is selected, the
GUI displays the read error. Try with all four available COM ports until this message disappears.
Figure 31 shows the read error message.
Figure 31 • Read Error
Revision 5
33
Appendix: Performing Write/Read Operation when Non 64-Bit Aligned
Address is Provided
5
Appendix: Performing Write/Read Operation
when Non 64-Bit Aligned Address is
Provided
When a non 64-bit aligned address is provided in the GUI, the GUI converts it into the 64-bit aligned
address (0, 8, 10, 18, 20, 28, 30, 38…) and performs the write/read operation.
1.
2.
Enter the non 64-bit aligned 32-bit address in HEX format.
Enter the 64-bit data in HEX format.
Figure 32 shows the non 64-bit aligned address entered in the GUI.
Figure 32 • Non 64-Bit Aligned Address
3.
Click Write to perform write operation. GUI converts the address into 64-bit aligned address and
performs the write operation.
Revision 5
34
Appendix: Performing Write/Read Operation when Non 64-Bit Aligned
Address is Provided
Figure 33 shows the GUI pop-up information message and converted 64-bit aligned address.
Figure 33 • Converted 64-Bit Aligned Address
Revision 5
35
Revision History
6
Revision History
The following table shows important changes made in this document for each revision.
Revision
Changes
Revision 5
(April 2016)
Updated the document for Libero v11.7 software release (SAR 78195).
Revision 4
(November 2015)
Changed AXI: MDDR ratio as 1:1 and updated Figure 3 on page 10, Figure 4 on
page 11, Figure 5 on page 12, and Figure 6 on page 13 (SAR 73230).
Revision 3
(October 2015)
Updated the document for Libero v11.6 software release (SAR 71692).
Revision 2
(February 2015)
Updated the document for Libero v11.5 software release (SAR 64895).
Revision 1
(August 2014)
Initial release
Revision 5
36
Product Support
7
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
7.1
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
7.2
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
7.3
Technical Support
For Microsemi SoC Products Support, visit
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.
7.4
Website
You can browse a variety of technical and non-technical information on the Microsemi SoC Products
Group home page, at http://www.microsemi.com/products/fpga-soc/fpga-and-soc.
7.5
Contacting the Customer Technical Support
Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
7.5.1
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected]
7.5.2
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Revision 5
37
Product Support
7.5.3
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Visit About Us for sales office listings and
corporate contacts.
7.6
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected] Alternatively, within My Cases, select Yes
in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web
page.
Revision 5
38
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice
processing devices; RF solutions; discrete components; enterprise storage and communication
solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Powerover-Ethernet ICs and midspans; as well as custom design capabilities and services.
Microsemi is headquartered in Aliso Viejo, Calif, and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
Microsemi Corporate
Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2016 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
50200568-5/4.16
Similar pages