DG0565: SmartFusion2 Low Standby Power - Libero SoC v11.7 Demo Guide

SmartFusion2 SoC FPGA Low Standby Power
- Libero SoC v11.7
DG0565 Demo Guide
Contents
1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7 . . . . . . . . . . . . . 6
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.2
Extracting the Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Creating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1
Launching Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.2
Connecting Components in the Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Importing Physical Constraint files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Synthesis and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Running the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.8.1
Power Measurement (Normal Operation and Standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.8.2
Precise Standby Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.8.3
Total Power (Dynamic and Static) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.8.4
Standby Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Appendix: Power Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1
Power Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1
5.2
5.3
5.4
5.5
5.6
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Design Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Libero SoC Project Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
New Project - Project Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
New Project - Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
New Project - Device Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
New Project Information Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Creating SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Entering SmartDesign Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock & Management Category of Libero SoC IP Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Configuring Fabric CCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuring PLL Feedback Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Configuring PLL Power-down Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Configuring Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Importing HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Design Hierarchy Tab with Imported Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SmartDesign Canvas after Adding Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SmartDesign Canvas after Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Importing I/O PDC Constraint File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Information Dialog Box after Importing PDC Constraint File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I/O PDC Constraint File in Libero SoC Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Selecting I/O PDC Constraint File in Design Flow Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Place and Route Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Successful Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Generating Post Layout Power Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reports Tab after Implementing Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SmartFusion2 Security Evaluation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Launching Programming Software from Design Flow Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming Messages in Libero SoC Log Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Design Flow Tab after Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Settings Section in the Device Settings and Summary Worksheet . . . . . . . . . . . . . . . . . . . . . . . . . 31
Initialize Power Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Initialize Power Estimator Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FAB_CCC and Oscillator Work Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Modes and Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
LEDs Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connections in Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Promote to Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Preface
1
Preface
1.1
Purpose
This demo is for the SmartFusion®2 system-on-chip (SoC) FPGAs. It provides instructions on how to use
the reference design.
1.2
Intended Audience
This demo guide is intended for:
•
•
1.3
FPGA designers
System-level designers
References
•
•
•
SmartFusion2 and IGLOO2 Power Estimator User Guide
UG0444: SmartFusion2 SoC and IGLOO2 FPGA Low Power Design User Guide
UG0445: SmartFusion2 Soc and IGLOO2 FPGA Fabric User Guide
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SmartFusion2 SoC FPGA Low Standby
Power - Libero SoC v11.7
2.1
Introduction
Microsemi® SmartFusion2 SoC FPGAs are designed to meet the demand of low power FPGAs. The
SmartFusion2 devices exhibit lower power consumption in static and dynamic modes. This demo guide
demonstrates how to implement the standby power mode on the SmartFusion2 devices using
SmartDesign and measure the standby power. The design drives the light emitting diodes (LEDs) on the
SmartFusion2 Security Evaluation Kit with a pattern based on the state of the switches SW1 and SW3,
as shown in Table 1.
Table 1 • LEDs Pattern
LED E1, F4, F3, G7 Behavior
Standby Entry (SW1)
Standby Exit (SW3)
LEDs toggle
Released
Released
LEDs on
Depressed and Released
Released
LEDs toggle
Depressed and Released
Depressed
This demo guide describes the following:
•
•
•
•
2.2
Creating a Libero® System-on-Chip (SoC) project
Implementing the standby power mode on the SmartFusion2 devices using SmartDesign
Importing a PDC file, running layout, and programming the SmartFusion2 silicon
Measuring the standby power using a standard digital voltmeter (DVM) / multimeter
Design Requirements
Table 2 lists the design requirements.
Table 2 • Design Requirements
Design Requirements
Description
Hardware Requirements
SmartFusion2 Security Evaluation Kit:
12 V adapter
FlashPro4 programmer
Rev D or later
Desktop or Laptop
Any Windows 64-bit Operating System
Software Requirements
Libero SoC
v11.7
FlashPro Programming Software
v11.7
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
2.3
Demo Design
2.3.1
Introduction
The demo design files are available for download from the following path in the Microsemi website:
http://soc.microsemi.com/download/rsc/?f=m2s_dg0565_liberov11p7_df
The demo design files include:
•
•
•
•
•
Libero SoC project
Constraint file
Programming file
Source files
Readme file
Refer to the Readme.txt file provided in the design files for the complete directory structure.
The design consists of a 32 kHz external main crystal oscillator, fabric CCC (FCCC), standby power
control logic, and fabric logic block. Figure 1 shows the block diagram of the design.
The FCCC is configured to provide a 100 MHz clock to the fabric logic. It is also configured with
phase-locked loop (PLL) power-down enabled. The 32 kHz external main crystal oscillator is the
reference clock source for FCCC. The lock signal is used as the reset signal to the fabric logic. The
standby power control logic consists of a clocked S-R latch, which powers down the PLL of FCCC. The
fabric logic consists 4202 stages of 8-bit loadable up-counters, 252 stages of 16-bit shift registers,
55 LSRAM blocks,56 µSRAM blocks, and 42 math blocks. It also consists an LED driver block, which is
connected to a set of light-emitting diodes (LEDs) to monitor the state of the fabric while entering and
exiting the standby power mode.
Figure 1 • Design Block Diagram
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Extracting the Source Files
Extract the required files to the <C:\ or D:\>Microsemi_prj folder on PC. Confirm that a folder named
SF2_Standby_tutorial containing sub-folders named Source_files and Constraints are extracted.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
2.4
Creating the Design
This section describes how to create the standby power mode enabled design using SmartDesign. Some
source files are provided in the Source_files folder.
2.4.1
Launching Libero SoC
The following steps describe how to launch Libero SoC:
1.
Go to Start > Programs > Microsemi > Libero SoC v11.7 > Libero SoC v11.7, or
double-click the shortcut icon on the PC. This opens the Libero SoC Project Manager window, as
shown in Figure 2.
Figure 2 • Libero SoC Project Manager
2.
Create a new project using one of the following options:
•
Select New on the Start Page tab, as shown in Figure 2.
•
In the Libero SoC menu, go to Project > New Project.
This opens the New Project window, as shown in Figure 3 on page 9.
3.
Enter the following information in the New Project - Project Details window, as shown in Figure 3
on page 9:
•
Project Name: SF2_Standby
•
Project Location: <C:\ or D:\>Microsemi_prj\SF2_Standby_tutorial
•
Preferred HDL type: VHDL
•
Enable Block Creation: Not selected
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Figure 3 • New Project - Project Details
4.
5.
6.
Click Next. This opens New Project - Device Selection window, as shown in Figure 4.
Select the following values from the drop-down list, highlighted in Figure 4:
•
Family: SmartFusion2
•
Die: M2S090TS
•
Package: 484 FBGA
•
Speed: -1
•
Core Voltage: 1.2
•
Range: COM
Select the filtered device M2S090TS-1FG484, as shown in Figure 4.
Figure 4 • New Project - Device Selection
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7.
8.
Click Next. This opens New Project - Device Settings window, as shown in Figure 5.
Select the following values in the Power supplies section from the drop-down list, highlighted in
Figure 5:
•
PLL Supply Voltage (V): 3.3 V
•
Power on Reset Delay: 100 ms
The PLL analog supply voltage can be either 2.5 V or 3.3 V. The voltage setting in the New Project Device Settings window must match the PLL analog supply voltage on the board to ensure that the PLL
works properly. The PLL analog supply voltage is connected to 3.3 V on the SmartFusion2 Security
Evaluation Kit.
9.
Do not change the default selections. Click Finish.
Figure 5 • New Project - Device Settings
New Project Information window opens as shown in Figure 6 on page 11.
10. Click Use Classic Constraint Flow.
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Figure 6 • New Project Information Window
11. In the Design Flow window, expand Create Design, as shown in Figure 7.
12. Right-click Create SmartDesign and click Run.
Figure 7 • Creating SmartDesign
13. In the Create New SmartDesign dialog box enter the Name as SF2_Standby and click OK. A new
SmartDesign canvas opens.
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Figure 8 • Entering SmartDesign Name
This design uses a fabric CCC to generate a 100 MHz internal clock. The CCC reference clock is the
32 kHz external main crystal oscillator.
14. In the IP catalog, expand Clock & Management.
Figure 9 • Clock & Management Category of Libero SoC IP Catalog
15. Drag an instance of the clock conditioning circuitry (CCC) v2.0.200 component into the SmartDesign
canvas.
16. Double-click the FCCC_0 component in the SmartDesign canvas and open the FAB CCC
Configurator window, as shown in Figure 10 on page 13.
17. Click the Basic tab in the FAB CCC Configurator window, as shown in Figure 10 on page 13 and
enter the following information:
•
Reference Clock Frequency: 0.032 MHz
•
Reference Clock: Select Oscillators > Crystal Oscillator from the drop-down list
•
GL0: Checked; Frequency: 100 MHz
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Figure 10 • Configuring Fabric CCC
18. Click the Advanced tab in the FAB CCC Configurator window and select Internal > PLL Internal
from the drop-down list as PLL feedback source, as shown in Figure 11 on page 14.
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Figure 11 • Configuring PLL Feedback Source
19. Click the PLL Options tab in the FAB CCC Configurator window and select the Expose
PLL_ARST_N and PLL_POWERDOWN_N signals checkbox, as shown in Figure 12 on page 15.
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Figure 12 • Configuring PLL Power-down Signal
20. Click OK.
21. Drag an instance of the Chip Oscillators v2.0.101 component from the IP catalog into the
SmartDesign canvas.
22. Double-click the OSC_0 component in the SmartDesign canvas and open the Chip Oscillators
Configurator window, as shown in Figure 13 on page 16.
23. Configure the external main crystal oscillator to drive the FCCC and the fabric logic by entering the
following information, as shown in Figure 13 on page 16:
•
External Main Crystal Oscillator: Selected
•
Source: Select Crystal (32 KHz - 20 MHz) from the drop-down list
•
Frequency: 0.032 MHz
•
Drives Fabric CCC(s): Selected
•
Drives Fabric Logic: Selected
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Figure 13 • Configuring Chip Oscillators
24. Click OK.
25. Import the VHDL source files into the project by selecting Create HDL under Create Design in the
Design Flow tab. Right-click and select Import Files…, as shown in Figure 14.
Figure 14 • Importing HDL Source Files
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26. Browse to <C:\ or D:\>Microsemi_prj\SF2_Standby_tutorial\Source_files select all .vhd, .v, and .h
files, and click Open.
The files are visible in the Design Hierarchy tab.
Figure 15 • Design Hierarchy Tab with Imported Files
27. Drag the Standby_Control and Fabric_Logic components into the SmartDesign canvas. The
SmartDesign resembles Figure 16 on page 18.
28. Align the components to improve the appearance of the canvas.
Expand the canvas area by selecting View > Maximize Work Area, or click the
icon on the tool
bar.
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Figure 16 • SmartDesign Canvas after Adding Components
2.4.2
Connecting Components in the Canvas
SmartDesign in Libero SoC has a connection mode that supports click, drag, and release to connect the
components.
Connect the components in the SmartDesign canvas using the following procedure:
1.
2.
Select SmartDesign > Connection Mode from the Libero SoC menu.
Connect the XTLOSC_CCC_OUT port of OSC_0 component to the XTLOSC_CCC_IN port of the
FCCC_0 component as follows:
a. Click and hold the XTLOSC_CCC_OUT port of the OSC_0 component.
b. Drag the XTLOSC_CCC_IN port of the FCCC_0 component and release the mouse button to
connect.
Note: You can also connect the ports by selecting them using CTRL (Ctrl + Click to select a port), right-clicking
any of the selected ports, and selecting Connect.
3.
Connect the other components in the SmartDesign canvas as per Table 3 on page 18.
Table 3 • Connections in Canvas
From
To
OSC_0: XTLOSC_O2F
Standby_Control_0: CLK
Standby_Control_0: PLL_PowerDown FCCC_0: PLL_ARST_N
FCCC_0: PLL_POWERDOWN_N
4.
FCCC_0: GL0
Fabric_Logic_0: CLK
FCCC_0: LOCK
Fabric_Logic_0: RST
Select SmartDesign > Connection Mode from the Libero SoC menu to exit the connection mode.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
5.
Promote the ports shown in Table 4 on page 19 to the top level. Right-click the port and select
Promote to Top Level.
Table 4 • Promote to Top Level
Ports
Standby_Control_0: Standby_Entry
Standby_Control_0: Standby_Exit
Fabric_Logic_0: LD
Fabric_Logic_0: DIN[15:0]
Fabric_Logic_0: DOUT[15:0]
Fabric_Logic_0: LED_1
Fabric_Logic_0: LED_2
Fabric_Logic_0: LED_3
Fabric_Logic_0: LED_4
The SmartDesign canvas appears, as shown in Figure 17 on page 19. Arrange the components by
dragging or use the SmartDesign Auto Arrange feature to improve the appearance of the canvas.
Figure 17 • SmartDesign Canvas after Connections
6.
7.
Go to File > Save SF2_Standby to save the design.
Generate the design by selecting SmartDesign > Generate Component, or by clicking the
Generate Component icon on the SmartDesign toolbar (highlighted in Figure 17 on page 19).
8. Go to View > Restore Work Area to restore the work area, if you expanded the work area earlier.
9. Confirm that the message SF2_Standby was generated appears in the Libero Log window.
10. Go to File > Close SF2_Standby to close the design.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
2.5
Importing Physical Constraint files
This section describes how to import a physical design constraint (PDC) file to make I/O attribute and pin
assignments for the layout.
The following steps describe how to make I/O assignments:
1.
2.
Expand Create Constraints in the Design Flow tab.
Right-click I/O Constraints and select Import Files....
Figure 18 • Importing I/O PDC Constraint File
3.
4.
Browse to <C:\ or D:\>Microsemi_prj\SF2_Standby_tutorial\Constraints, select the
SF2_Standby.pdc file, and click Open.
Click No in the Information dialog box.
Figure 19 • Information Dialog Box after Importing PDC Constraint File
The file is visible in the Libero SoC Files tab under constraint > io.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
Figure 20 • I/O PDC Constraint File in Libero SoC Project
A description of the designer PDC constraints is available in the Libero Help (Go to Help > Help Topics
> Implement Design > Constrain Place and Route > Assigning Design Constraints > Design
Constraints Guide > Reference > Constraints by File Format > PDC Command Reference).
2.6
Synthesis and Layout
Use the push-button flow to synthesize the design with Synplify Pro, run layout and generate the
programming file as mentioned below:
1.
2.
Expand Create Constraints > I/O Constraints in the Libero SoC Design Flow tab. Right-click
SF2_Standby.pdc under Constraints.
Right-click and select Use for Compile, as shown in Figure 21 on page 22. A green tick mark
appears on the constraint file indicating that the file will be used.
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Figure 21 • Selecting I/O PDC Constraint File in Design Flow Tab
3.
On the Design Flow tab click Place and Route (see Figure 22) or select Design > Place and
Route to synthesize the design, and run the layout using the I/O constraints that are created.
Figure 22 • Place and Route Button
Note: It may take 30 minutes to complete the flow.
The design implementation tools run in batch mode. Successful completion of a design step is indicated
by a green tick mark next to Implement Design in the Design Flow tab, as shown in Figure 23 on
page 23.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
Figure 23 • Successful Design Implementation
4.
Generate a power report by right-clicking Verify Power under Verify Post Layout Implementation
in the Design Flow tab and selecting Run.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
Figure 24 • Generating Post Layout Power Report
5.
The Reports tab displays reports for the tools used to implement the design. Select
SF2_Standby_power_report.xml under Verify Power in the Reports tab to view the power
consumption.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
Figure 25 • Reports Tab after Implementing Design
The Reports tab displays the power report, as shown in Figure 26 on page 26.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
Figure 26 • Power Report
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
2.7
Programming
The following steps describe how to run FlashPro in batch mode and program SmartFusion2 M2S090TS
on the SmartFusion2 Security Evaluation Kit board:
1.
Prior to programming and powering up the SmartFusion2 Security Evaluation Kit board, ensure that
the jumpers are positioned as shown in Table 5.
Table 5 • Jumper Settings
Jumper
Location
Setting
J3
Above the ON/OFF switch in Figure 27
1-2 installed
J8
Below the JTAG programming header (J5) in Figure 27
1-2 installed
Figure 27 • SmartFusion2 Security Evaluation Kit
2.
3.
4.
5.
6.
Plug the FlashPro4 ribbon cable into connector J5 (JTAG programming header) on the
SmartFusion2 Security Evaluation Kit board.
Connect FlashPro4 to the USB port of the PC using the mini USB cable.
Install the FlashPro4 drivers if prompted. The drivers are located at: <FlashPro Installation
Directory>\Drivers.
Power on the board by plugging in the power cable and switching on the power switch. Three green
LEDs on the top left of the board are powered on.
In the Design Flow tab, expand Program and Debug Design > Program Design. Right-click Run
PROGRAM Action and select Run to begin programming.
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Figure 28 • Launching Programming Software from Design Flow Tab
FlashPro runs in the batch mode and programs the device. Programming messages are visible in the
Libero SoC log window. Programmer number differs.
Note: Do not interrupt the programming sequence. It may damage the device or programmer.
The following message is visible in the Reports view under Program Device when the device is
programmed successfully, as shown in Figure 29 on page 29. Programmer number differs:
programmer '92327' : device 'M2S090TS' : Executing action PROGRAM PASSED.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
Figure 29 • Programming Messages in Libero SoC Log Window
A green tick mark appears next to Program Design in the Design Flow tab indicating that programming is completed successfully.
Figure 30 • Design Flow Tab after Programming
7.
Go to Project > Exit to close Libero SoC. Select Yes, if prompted for saving the changes.
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SmartFusion2 SoC FPGA Low Standby Power - Libero SoC v11.7
2.8
Running the Demo Design
2.8.1
Power Measurement (Normal Operation and Standby)
The SmartFusion2 Security Evaluation Kit board has a voltage measuring circuit that measures the
voltage across the VDD (1.2 V) current sense resistor.
The core power can be calculated using following equations:
Core Current  mA  = Measured Voltage  mV   5  Scaling Factor 
EQ 1
Core Power  mW  = 1.2  Core Current
EQ 2
Connect the positive terminal of a standard digital voltmeter (DVM)/Multimeter to TP14 and negative
terminal to TP7.
Note the digital voltmeter/Multimeter reading and calculate the power using above equations.
2.8.2
Precise Standby Power Measurement
Precise and accurate power measurements can be obtained by measuring voltage across the 1.2 V,
0.05  sense resistor. Test points TP16 and TP17 can be used to directly measure voltage across the
1.2 V sense resistor. Since the current drawn by the device in standby mode is expected to be around or
less than 10 mA, the voltage measured across the 0.05  sense resistor is expected to be less than
0.5 mV. A precise digital voltmeter such as Fluke-287 that can measure sub-millivolt readings must be
used to read voltage measured across the sense resistor.
Convert the voltage measured across sense resistor to power using the following equation:
Power  mW  =  Voltage  mV   0.05   1.2
EQ 3
2.8.3
Total Power (Dynamic and Static)
The following steps describe how to calculate total power:
1. Reset the board by pressing and releasing the Reset button (SW6 DEVRST).
2. Observe the pattern of the LEDs E1, F4, F3, and G7 after resetting the board.
3. Measure the power
Note: If the LEDs are not toggling after reset, the device is in the Standby mode. Press and release the standby
exit push button (SW3) and observe the LEDs lighting pattern. When the LEDs start toggling, measure
the power.
2.8.4
Standby Power
The following steps describe how to calculate standby power:
1.
2.
3.
4.
Press and release the standby entry push button (SW1) and observe the LEDs lighting pattern. The
LEDs stop toggling.
Measure the power.
Press and release the standby exit push button (SW3).
When finished, remove power from the board.
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Appendix: Power Estimator
3
Appendix: Power Estimator
3.1
Power Estimator
The following steps describe how to use Power Estimator and calculate the total power:
1.
2.
3.
4.
Download the Power Estimator, SmartFusion2 and IGLOO2 Power Calculator.
Double-click and invoke the power estimator spreadsheet.
Click on the Summary worksheet. The Summary worksheet provides the device settings and the
power summary.
Change the device settings by selecting the following from the drop-down list:
•
Family: Select SmartFusion2
•
Device: Select M2S090TS
•
Package: Select 484 FBGA
Figure 31 • Settings Section in the Device Settings and Summary Worksheet
The summary worksheet has an integrated initialize power estimator wizard. This wizard provides an
option to select design specific information. Upon running the wizard, it populates the power estimator
spreadsheet with information about the design and performs power estimation for the design.
5.
Click Initialize Power Estimator as shown in Figure 32. The Initialize power estimator dialog box
opens as shown in Figure 33.
Figure 32 • Initialize Power Estimator
6.
Enter the following information in the Initialize Power Estimator dialog box:
•
Set all FPGA fabric resources to: 50%
•
IO:
•
Technology: LVCMOS25
•
#Inputs: 19
•
#Outputs: 20
•
Default RAM Enable Rate: 100%
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Appendix: Power Estimator
Figure 33 • Initialize Power Estimator Wizard
7.
8.
9.
Click OK. Click Yes in the Reset and set to the values specified dialog box.
Click on the CCC & Oscillator worksheet.
Enter the following information in the Oscillator Power table for the external main crystal oscillator:
•
Used: Select Yes from the drop-down list
•
Frequency (MHz): 0.032
10. Scroll down to the FAB_CCC Power section and enter the following information in the FAB_CCC
Power table:
•
Name: FCCC_0
•
Reference clock frequency (MHz): 0.032
•
PLL output frequency (MHz): 500 MHz
•
Output1 frequency (MHz):100 MHz
Figure 34 • FAB_CCC and Oscillator Work Sheet
11. Click the Summary worksheet to get the total power. The Power Summary section is populated with
the Total Active mode power.
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Appendix: Power Estimator
Figure 35 • Power Summary
The Modes and Scenarios section is populated with the total power in the Active, Standby, and
Flash*Freeze modes.
Figure 36 • Modes and Scenarios
12. Close the Power Estimator.
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Revision History
4
Revision History
The following table shows important changes made in this document for each revision.
Revision
Changes
Revision 4
(March 2016)
Updated the document for Libero SoC v11.7 (SAR 76538).
Revision 3
(October 2015)
Updated the document for Libero SoC v11.6 (SAR 71490).
Revision 2
(February 2015)
Updated the document for Libero SoC v11.5 (SAR 64705).
Revision 1
(September 2014)
Initial release.
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Product Support
5
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
5.1
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
5.2
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
5.3
Technical Support
For Microsemi SoC Products Support, visit
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.
5.4
Website
You can browse a variety of technical and non-technical information on the Microsemi SoC Products
Group home page, at http://www.microsemi.com/products/fpga-soc/fpga-and-soc.
5.5
Contacting the Customer Technical Support
Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
5.5.1
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected]
5.5.2
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
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Product Support
5.5.3
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Visit About Us for sales office listings and
corporate contacts.
5.6
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected] Alternatively, within My Cases, select Yes
in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web
page.
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Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
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processing devices; RF solutions; discrete components; Enterprise Storage and
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services. Microsemi is headquartered in Aliso Viejo, Calif, and has approximately 4,800
employees globally. Learn more at www.microsemi.com.
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CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
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Fax: +1 (949) 215-4996
E-mail: [email protected]
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Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
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liability whatsoever arising out of the application or use of any product or circuit. The products sold
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on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
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