DS0120: Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet

Military Grade IGLOO2 FPGA and
SmartFusion2 SoC FPGA
DS0120 Datasheet
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table of Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Product Briefs and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
11
4.1. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Overshoot/Undershoot Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.1
4.3.2
4.3.3
4.3.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Theta-JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Theta-JB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Theta-JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
16
16
16
5. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1. Quiescent Supply Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2. Programming Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Average Fabric Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . 19
7. Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1. Input Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2. Output Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3. Tristate Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4. I/O Speeds
................................................................
8.5. Detailed I/O Characteristics
.................................................
8.6. Single-Ended I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) . . . . . . . . . . . . . . . . . . . . . . .
3.3 V LVCMOS/LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 V PCI/PCIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
23
24
25
27
27
27
28
30
33
36
39
42
8.7. Memory Interface and Voltage Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
High-Speed Transceiver Logic (HSTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic 2.5 V (SSTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic 1.8 V (SSTL18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic 1.5 V (SSTL15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Double Data Rate (LPDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
45
45
48
50
52
8.8. Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mini-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RSDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.9. I/O Register Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.9.1 Input Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.9.2 Output/Enable Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.10. DDR Module Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
Input DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
71
72
73
75
9. Logic Element Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.1. 4-input LUT (LUT-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.2. Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.2.1 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10. Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11. FPGA Fabric SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.1. FPGA Fabric Large SRAM (LSRAM)
11.2. FPGA Fabric Micro SRAM (uSRAM)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12. Embedded NVM (eNVM) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
15. Clock Conditioning Circuits (CCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
16. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
17. DEVRST_N Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
18. System Controller SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19. Mathblock Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
20. Flash*Freeze Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21. DDR Memory Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
22. SFP Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
23. PCIe Electrical and Timing AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 109
24. SmartFusion2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
24.1. MSS Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
24.2. SmartFusion2 Inter-Integrated Circuit (I2C) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
24.3. Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
25. CAN Controller Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
26. USB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
27. IGLOO2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
27.1. HPMS Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
27.2. IGLOO2 Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
28. List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
29. Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
29.1. Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.2. Product Brief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.3. Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4. Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5. Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
30. Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . 123
31. Microsemi Corporate Headquarters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
List of Figures
Figure 1. Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 2. Input Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. Output Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Tristate Buffer for Enable Path Test Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. Timing Model for Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 6. I/O Register Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 7. Timing Model for Output/Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 8. I/O Register Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 9. Input DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 10. Input DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 11. Output DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 12. Output DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 13. LUT-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 14. Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 15. Sequential Module Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 16. I2C Timing Parameter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 17. SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) . . . . . . . . . . . . . . . . . 115
Figure 18. SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) . . . . . . . . . . . . . . . . . 120
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
List of Tables
Table 1. IGLOO2 FPGA and SmartFusion2 SoC FPGA Device Status ...............................................10
Table 2. Absolute Maximum Ratings ....................................................................................................11
Table 3. Recommended Operating Conditions ....................................................................................12
Table 4. FPGA Operating Limits ...........................................................................................................14
Table 5. Embedded Flash Limits ..........................................................................................................14
Table 6. Device Storage Temperature and Retention ..........................................................................14
Table 7. Package Thermal Resistance .................................................................................................15
Table 8. Quiescent Supply Current Characteristics ..............................................................................17
Table 9. SmartFusion2 and IGLOO2 Quiescent Supply Current – Typical Process ............................17
Table 10. Currents During Program Cycle, 0°C < = TJ <= 85°C, Typical Process ...............................18
Table 11. Currents During Verify Cycle, 0°C <= TJ <= 85°C, Typical Process .....................................18
Table 12. Inrush Currents at Power up, –55°C <= TJ <=125°C, Typical Process ................................18
Table 13. SmartFusion2 and IGLOO2 Quiescent Supply Current – Worst-Case Process ...................18
Table 14. Average Temperature and Voltage Derating Factors for Fabric Timing Delays ...................19
Table 15. Timing Model Parameters ....................................................................................................21
Table 16. Maximum Data Rate Summary for Worst-Case Military Conditions .....................................25
Table 17. Maximum Frequency Summary for Worst-Case Military Conditions ....................................26
Table 18. Input Capacitance .................................................................................................................27
Table 19. I/O Weak Pull-Up/Pull-Down Resistance Values for DDRIO, MSIO, and MSIOD Banks .....27
Table 20. Schmitt Trigger Input Hysteresis ..........................................................................................27
Table 21. LVTTL/LVCMOS 3.3 V DC Voltage Specification (Applicable to MSIO I/O Bank Only) .......28
Table 22. LVTTL/LVCMOS 3.3 V Maximum Switching Speeds (Applicable to MSIO I/O Bank Only) .28
Table 23. LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO Bank Only) 28
Table 24. LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Banks (Input Buffers) .........29
Table 25. LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) ......................................................................................................................................................29
Table 26. LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications
(Applicable to MSIO Bank* Only) .........................................................................................................29
Table 27. LVCMOS 2.5 V DC Voltage Specification ............................................................................30
Table 28. LVCMOS 2.5 V Maximum AC Switching Speeds .................................................................30
Table 29. LVCMOS 2.5 V AC Test Parameters and Driver Impedance Specifications ........................30
Table 30. LVCMOS 2.5 V AC Switching Characteristics for Receiver (Input Buffers) ..........................31
Table 31. LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 31
Table 32. LVCMOS 2.5 V Transmitter Drive Strength Specifications ...................................................31
Table 33. LVCMOS 1.8 V DC Voltage Specification ............................................................................33
Table 34. LVCMOS 1.8 V Maximum AC Switching Speeds .................................................................33
Table 35. LVCMOS 1.8 V Transmitter Drive Strength Specifications ...................................................33
Table 36. LVCMOS 1.8 V Transmitter Drive Strength Specifications ...................................................34
Table 37. LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications ........................34
Table 38. LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers) ..........................35
Table 39. LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 35
Table 40. LVCMOS 1.5 V Minimum and Maximum DC Input and Output Levels ................................36
Table 41. LVCMOS 1.5 V Maximum AC Switching Speeds .................................................................37
Table 42. LVCMOS 1.5 V AC Test Parameters and Driver Impedance Specifications ........................37
Table 43. LVCMOS 1.5 V Transmitter Drive Strength Specifications ...................................................37
Table 44. LVCMOS 1.5 V AC Switching Characteristics for Receiver (Input Buffers) ..........................38
Table 45. LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 38
Table 46. LVCMOS 1.2 V Minimum and Maximum DC Input and Output Levels ................................39
Revision 4
6
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 47. LVCMOS 1.2 V Maximum AC Switching Speeds .................................................................40
Table 48. LVCMOS 1.2 V AC Calibrated Impedance and Test Parameters Specifications .................40
Table 49. LVCMOS 1.2 V Transmitter Drive Strength Specifications ...................................................40
Table 50. LVCMOS 1.2 V AC Switching Characteristics for Receiver (Input Buffers) ..........................41
Table 51. LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 41
Table 52. PCI/PCI-X DC Voltage Specification (Applicable to MSIO Bank Only ..................................42
Table 53. PCI/PCI-X AC Specifications (Applicable to MSIO Bank Only) ............................................42
Table 54. PCI/PCIX AC Switching Characteristics for Receiver (Input Buffers) ...................................43
Table 55. PCI/PCIX AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ........43
Table 56. HSTL DC Voltage Specification (Applicable to DDRIO I/O Bank Only) ................................43
Table 57. HSTL15 AC Switching Characteristics for Receiver (Input Buffers) .....................................44
Table 58. HSTL AC Specifications (Applicable to DDRIO Bank Only) .................................................44
Table 59. HSTL 15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) .........45
Table 60. DDR1/SSTL2 Minimum and Maximum DC Input and Output Levels ...................................45
Table 61. DDR1/SSTL2 AC Specifications ...........................................................................................46
Table 62. DDR1/SSTL2 AC Switching Characteristics for Receiver (Input Buffers) ............................47
Table 63. DDR1/SSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ..47
Table 64. DDR2/SSTL18 AC/DC Minimum and Maximum Input and Output Levels Specification ......48
Table 65. DDR2/SSTL18 AC Specifications (Applicable to DDRIO Bank Only) ..................................49
Table 66. DDR2/SSTL18 AC Switching Characteristics for Receiver (Input Buffers) ..........................50
Table 67. DDR2/SSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 50
Table 68. DDR3 SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) .................................50
Table 69. DDR3/SSTL15 AC Specifications .........................................................................................51
Table 70. DDR3/STTL15 AC Switching Characteristics for Receiver (Input Buffers) ...........................52
Table 71. DDR3/SSTL15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 52
Table 72. LPDDR AC/DC Specifications (for DDRIO IO Bank Only) ...................................................52
Table 73. LPDDR Maximum AC Switching Speeds (for DDRIO I/O Bank Only) ..................................53
Table 74. LPDDR AC Specifications (for DDRIO IO Bank Only) ..........................................................53
Table 75. LPDDR AC Switching Characteristics for Receiver (Input Buffers) ......................................54
Table 76. LPDDR AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...........54
Table 77. LPDDR-LVCMOS 1.8 V Mode, Minimum and Maximum DC Input and Output Levels
(Applicable to DDRIO I/O Bank Only) ...................................................................................................54
Table 78. LPPDR - LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers) ..........55
Table 79. LPDDR-LVCMOS 1.8 V Maximum AC Switching Speeds (Applicable to DDRIO I/O Bank Only)
...............................................................................................................................................................55
Table 80. LPDDR-LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications (Applicable to
DDRIO I/O Bank Only) .........................................................................................................................55
Table 81. LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification (Applicable to DDRIO I/O
Bank Only) ............................................................................................................................................55
Table 82. LPDDR - LVCMOS 1.8 V AC Switching Characteristics for Transmitter DDRIO I/O Bank (Output
and Tristate Buffers) .............................................................................................................................56
Table 83. LVDS DC Voltage Specification ...........................................................................................57
Table 84. LVDS AC Specifications .......................................................................................................57
Table 85. LVDS25 Receiver Characteristics ........................................................................................58
Table 86. LVDS25 Transmitter Characteristics ....................................................................................58
Table 87. LVDS33 Receiver Characteristics ........................................................................................58
Table 88. LVDS33 Transmitter Characteristics ....................................................................................58
Table 89. B-LVDS DC Voltage Specification ........................................................................................59
Table 90. B-LVDS AC Specifications ...................................................................................................59
Table 91. B-LVDS AC Switching Characteristics for Receiver (Input Buffers) .....................................60
Table 92. B-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ..........60
Table 93. M-LVDS DC Voltage Specification .......................................................................................60
Table 94. M-LVDS AC Switching Characteristics for Receiver (Input Buffers) .....................................61
Revision 4
7
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 95. M-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ..........61
Table 96. M-LVDS AC Specifications ...................................................................................................61
Table 97. Mini-LVDS DC Voltage Specification ....................................................................................62
Table 98. Mini-LVDS AC Specifications ...............................................................................................62
Table 99. Mini-LVDS AC Switching Characteristics for Receiver (Input Buffers) .................................63
Table 100. Mini-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ....63
Table 101. RSDS DC Voltage Specification .........................................................................................64
Table 102. RSDS AC Specifications ....................................................................................................64
Table 103. RSDS AC Switching Characteristics for Receiver (Input Buffers) ......................................65
Table 104. RSDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ...........65
Table 105. LVPECL DC Voltage Specification (Applicable to MSIO I/O Banks Only) ..........................65
Table 106. LVPECL Receiver Characteristics ......................................................................................66
Table 107. LVPECL Maximum AC Switching Speeds (Applicable to MSIO I/O Banks Only) ..............66
Table 108. Input Data Register Propagation Delays ............................................................................67
Table 109. Output/Enable Data Register Propagation Delays .............................................................69
Table 110. Input DDR Propagation Delays ..........................................................................................72
Table 111. Output DDR Propagation Delays ........................................................................................75
Table 112. Combinatorial Cell Propagation Delays ..............................................................................76
Table 113. Register Delays ..................................................................................................................78
Table 114. M2S150T Device Global Resource ....................................................................................78
Table 115. M2S090T Device Global Resource ..................................................................................78
Table 116. M2S025T Device Global Resource ....................................................................................79
Table 117. M2S010T Device Global Resource ....................................................................................79
Table 118. M2S050T Device Global Resource ....................................................................................79
Table 119. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18 ...............................80
Table 120. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2Kx9 .................................81
Table 121. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4Kx4 .................................82
Table 122. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8Kx2 .................................83
Table 123. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16Kx1 ...............................84
Table 124. RAM1K18 – Two-Port Mode for Depth × Width Configuration 512x36 ..............................86
Table 125. uSRAM (RAM64x18) in 64x18 Mode .................................................................................87
Table 126. uSRAM (RAM64x16) in 64x16 Mode .................................................................................88
Table 127. uSRAM (RAM128x9) in 128x9 Mode .................................................................................89
Table 128. uSRAM (RAM128x8) in 128x8 Mode .................................................................................91
Table 129. uSRAM (RAM256x4) in 256x4 Mode .................................................................................92
Table 130. uSRAM (RAM512x2) in 512x2 Mode .................................................................................93
Table 131. uSRAM (RAM1024x1) in 1024x1 Mode .............................................................................95
Table 132. eNVM Read Performance ..................................................................................................97
Table 133. eNVM Page Programming ..................................................................................................97
Table 134. Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz) ................98
Table 135. Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz) .............98
Table 136. Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz) ..................98
Table 137. Electrical Characteristics of the 50 MHz RC Oscillator .......................................................99
Table 138. Electrical Characteristics of the 1 MHz RC Oscillator .........................................................99
Table 139. IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Specification ....................................100
Table 140. JTAG 1532 .......................................................................................................................101
Table 141. IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Jitter Specifications .........................101
Table 142. DEVRST_N Characteristics ..............................................................................................102
Table 143. System Controller SPI Characteristics .............................................................................103
Table 144. Supported I/O Configurations for System Controller SPI (for MSIO Bank Only) ..............103
Table 145. Mathblocks With All Registers Used .................................................................................104
Table 146. Mathblock With Input Bypassed and Output Registers Used ...........................................104
Table 147. Flash*Freeze Entry and Exit Times ..................................................................................105
Revision 4
8
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 148. Mathblock With Input Register Used and Output in Bypass Mode ...................................105
Table 149. Mathblock With Input and Output in Bypass Mode ...........................................................105
Table 150. DDR Memory Interface Characteristics ............................................................................107
Table 151. SFP Transceiver Electrical Characteristics ......................................................................108
Table 152. Transmitter Parameters ....................................................................................................109
Table 153. Receiver Parameters ........................................................................................................109
Table 154. SERDES Reference Clock AC Specifications ..................................................................109
Table 155. Maximum Frequency for MSS Main Clock .......................................................................110
Table 156. I2C Characteristics ...........................................................................................................110
Table 157. HCSL Minimum and Maximum DC Input Levels (Applicable to SERDES REFCLK Only) 110
Table 158. HCSL Maximum AC Switching Speeds (Applicable to SERDES REFCLK Only) ............110
Table 159. I2C Switching Characteristics ...........................................................................................112
Table 160. SPI Characteristics ...........................................................................................................113
Table 161. CAN Controller Characteristics .........................................................................................116
Table 162. USB Characteristics .........................................................................................................117
Table 163. Maximum Frequency for HPMS Main Clock .....................................................................118
Table 164. SPI Characteristics ...........................................................................................................118
Revision 4
9
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
IGLOO2 and SmartFusion2 SoC FPGA Military Grade
AC/DC Electrical Characteristics
1. Introduction
Microsemi®’s military grade SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) and
IGLOO®2 FPGA families integrate an industry standard 4-input lookup table-based (LUT) FPGA fabric with integrated
mathblocks, multiple embedded memory blocks, and high-performance SERDES communications interfaces on a
single chip. Both families benefit from low power flash technology and are the most secure and reliable FPGAs in the
industry. These next generation devices offer up to 150K Logic Elements, up to five MB of embedded RAM, up to 16
SERDES lanes, and up to four PCI Express Gen 1 endpoints, as well as integrated hard DDR3 memory controllers
with error correction.
SmartFusion2 military grade devices integrate an entire low power real time Microcontroller Subsystem with a rich set
of Industry standard peripherals including Ethernet, USB, and CAN, while the IGLOO2 military devices integrate a
high-performance memory subsystem with on-chip flash, 32 Kbyte embedded SRAM, and multiple DMA controllers.
2. Device Status
For more information on device status, refer to the "Datasheet Categories".
Table 1 •
IGLOO2 FPGA and SmartFusion2 SoC FPGA Device Status
Design Security Device Densities
Status
010T
Production
025T
Production
050T
Production
060T
Preliminary
090T
Production
150T
Production
Data Security Device Densities
Status
010TS
Production
025TS
Production
050TS
Production
060TS
Preliminary
090TS
Production
150TS
Production
Revision 4
10
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
3. Product Briefs and Pin Descriptions
The product brief and pin descriptions are published separately:
•
PB0121: IGLOO2 Product Brief
•
DS0124: IGLOO2 Pin Descriptions
•
PB0115: SmartFusion2 SoC FPGA Product Brief
•
DS0115: SmartFusion2 Pin Descriptions
4. General Specifications
4.1 Operating Conditions
Stresses beyond those listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions
beyond those listed under the recommended operating conditions specified in Table 2 is not implied.
Table 2 •
Absolute Maximum Ratings
Limits
Symbol
Parameter
Min
Max Units Notes
VDD
DC core supply voltage. Must always power this
–0.3
pin.
1.32
V
–
VPP
Power supply for charge pumps (for normal
operation and programming). Must always power –0.3
this pin.
3.63
V
–
MSS_MDDR_PLL_VDDA
Analog power pad for MDDR PLL
–0.3
3.63
V
–
HPMS_MDDR_PLL_VDDA
Analog power pad for MDDR PLL
–0.3
3.63
V
–
FDDR_PLL_VDDA
Analog power pad for FDDR PLL
–0.3
3.63
V
–
PLL0_PLL1_MSS_MDDR_VDDA
Analog power pad for MDDR PLL
–0.3
3.63
V
–
PLL0_PLL1_HPMS_MDDR_VDDA Analog power pad for MDDR PLL
–0.3
3.63
V
–
CCC_XX[01]_PLL_VDDA
Analog power pad for PLL0–5
–0.3
3.63
V
–
SERDES_[01]_PLL_VDDA
High supply voltage for PLL SERDES[01]
–0.3
3.63
V
–
SERDES_[01]_L[0123]_VDDAPLL
Analog power for SERDES[01] PLL lane0 to lane3.
–0.3
This is a +2.5 V SERDES internal PLL supply.
2.75
V
–
SERDES_[01]_L[0123]_VDDAIO
TX/RX analog I/O voltage. Low voltage power for
the lanes of SERDESIF0. This is a +1.2 V SERDES –0.3
PMA supply.
1.32
V
–
SERDES_[01]_VDD
PCIe®/PCS power supply
–0.3
1.32
V
–
DC FPGA I/O buffer supply voltage for MSIO I/O
–0.3
Bank
3.63
V
–
DC FPGA I/O buffer
MSIOD/DDRIO I/O Banks
–0.3
2.75
V
–
I/O Input voltage for MSIO I/O Bank
–0.3
3.63
V
–
I/O Input voltage for MSIOD/DDRIO I/O Bank
–0.3
2.75
V
–
Analog sense circuit supply of embedded
nonvolatile memory (eNVM). Must be shorted to –0.3
VPP.
3.63
V
–
VDDIx
VI
VPPNVM
supply
Revision 4
voltage
for
11
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 2 •
Absolute Maximum Ratings (continued)
Limits
Symbol
Parameter
Min
Max Units Notes
TSTG
Storage temperature
–65
150
°C
*
TJ
Junction temperature
–
135
°C
–
Note: * For flash programming and retention maximum limits, refer to Table 4 on page 14. For recommended operating
conditions, refer to Table 3.
Table 3 •
Recommended Operating Conditions
Symbol
Tj
VDD
VPP
MSS_MDDR_PLL_VDDA
HPMS_MDDR_PLL_VDDA
FDDR_PLL_VDDA
PLL0_PLL1_MSS_MDDR_VDDA
Parameter
Operating
Temperature
Junction
Programming
Temperature
Junction
Conditions
Min
Typ
Max
Military
-55
25
125
°C
–
–
0
25
85
°C
–
–
-40
25
100
°C
1
–
1.14
1.2
1.26
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
DC core supply voltage.
Must always power this
pin.
Power
Supply
for
Charge
Pumps
(for
Normal Operation and
Programming) for 010,
025, 050 Devices
Power
Supply
for
Charge
Pumps
(for
Normal Operation and
Programming) for 090,
and 150 devices
Analog power pad for
MDDR PLL
Analog power pad for
MDDR PLL
Analog power pad for
FDDR PLL
Analog power pad for
MDDR PLL
Revision 4
Units Notes
12
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 3 •
Recommended Operating Conditions (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
2.5 V
Range
2.375
2.5
2.625
V
2
3.3 V
Range
3.15
3.3
3.45
V
2
SERDES_[01]_L[0123]_VDDAPLL
Analog
power
for
SERDES[01] PLL lanes
0-3. It is a +2.5 V
SERDES internal PLL
supply.
–
2.375
2.5
2.625
V
–
SERDES_[01]_L[0123]_VDDAIO
TX/RX
analog
I/O
voltage. Low voltage
power for the lanes of
SERDESIF0. It is a
+1.2 V SERDES PMA
supply.
–
1.14
1.2
1.26
V
–
SERDES_[01]_VDD
PCIe/PCS Power supply
–
1.14
1.2
1.26
V
–
1.2 V DC supply voltage
–
1.14
1.2
1.26
V
–
1.5 V DC supply voltage
–
1.425
1.5
1.575
V
–
1.8 V DC supply voltage
–
1.71
1.8
1.89
V
–
2.5 V DC supply voltage
–
2.375
2.5
2.625
V
–
3.3 V DC supply voltage
–
3.15
3.3
3.45
V
–
LVDS differential I/O
–
2.375
2.5
3.45
V
–
BLVDS, MLVDS, MiniLVDS, RSDS differential
I/O
–
2.375
2.5
2.625
V
–
LVPECL differential I/O
–
3.15
3.3
3.45
V
–
Reference
Supply
for
(Bank0)
MDDR(Bank5)
–
V
–
Analog power pad for
PLL0_PLL1_HPMS_MDDR_VDDA
MDDR PLL
CCC_XX[01]_PLL_VDDA
SERDES_[01]_PLL_VDDA
VDDIx
VREFx
Analog power pad for
PLL0-5
High supply voltage for
PLL SERDES[01]
Voltage
FDDR
and
Revision 4
0.49 × 0.5 × 0.51 ×
VDDIx VDDIx VDDIx
Units Notes
13
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 3 •
Recommended Operating Conditions (continued)
Symbol
VPPNVM
Parameter
Conditions
Min
Typ
Max
Units Notes
Analog sense circuit
supply of embedded
nonvolatile
memory
(eNVM).
Must
be
shorted to VPP
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
Notes:
1. Programming at this temperature range is available only with VPP in 3.3 V Range
2. Power supply ramps must all be strictly monotonic, without plateaus.
Table 4 •
FPGA Operating Limits
Product Grade
Military
Element
FPGA
Programming
Temperature
Operating
Temperature
Programming
Retention
Cycles
(Biased/Unbiased) Note
Min TJ = 0°C
Max TJ = 85°C
Min TJ = -55°C
Max TJ = 125°C
500
10 Years
–
Min TJ = -40°C
Max TJ = 100°C
Min TJ = -55°C
Max TJ = 125°C
500
10 Years
*
Note: *: Programming at this temperature range is available only with VPP in 3.3 V Range
Table 5 •
Embedded Flash Limits
Product Grade
Military
Table 6 •
Embedded flash
Maximum
Operating
Temperature
Min TJ = -55°C
Max TJ = 125°C
Min TJ = -55°C
Max TJ = 125°C
Programming
Cycles
Retention
(Biased/Unbiased)
< 10,000 cycles
per pages, up to
one million cycles
per eNVM array
10 Years
Device Storage Temperature and Retention
Product Grade
Military
Element
Programming
Temperature
Storage Temperature (Tstg)
Retention
Min TJ = -55°C
Max TJ = 125°C
10 Years
4.2 Overshoot/Undershoot Limits
For AC signals, the input signal may undershoot during transitions to -1.0 V for no longer than 10% or the period. The
current during the transition must not exceed 100mA.
For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the period.
The current during the transition must not exceed 100mA.
Note: The above specification does not apply to the PCI standard. The IGLOO2 and SmartFusion2 PCI I/Os are
compliant to the PCI standard including the PCI overshoot/undershoot specifications.
Revision 4
14
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
4.3. Thermal Characteristics
4.3.1 Introduction
The temperature variable in the Microsemi SoC Products Group Designer software refers to the junction temperature,
not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power
consumption will cause the chip's junction temperature to be higher than the ambient, case, or board temperatures.
EQ 1 through EQ 3 give the relationship between thermal resistance, temperature gradient, and power.
TJ – TA
 JA = -----------------P
EQ 1
 JB
TJ – TB
= -----------------P
 JC
TJ – TC
= -----------------P
EQ 2
EQ 3
where
JA = Junction-to-air thermal resistance
JB = Junction-to-board thermal resistance
JC = Junction-to-case thermal resistance
TJ
= Junction temperature
TA
= Ambient temperature
TB
= Board temperature (measured 1.0 mm away from the package edge)
TC
= Case temperature
P
= Total power dissipated by the device
Table 7 •
Package Thermal Resistance
Product
M2GL/M2S
JA
Still Air
1.0 m/s
2.5 m/s
JB
JC
Units
FG484
18.22
14.83
13.62
8.83
4.92
°C/W
FG484
17.03
13.66
12.45
7.66
4.18
°C/W
FG484
15.29
12.19
10.99
6.27
3.24
°C/W
15.40
12.06
10.85
6.14
3.15
°C/W
FG484
14.64
11.37
10.16
5.43
2.77
°C/W
FC1152
9.08
6.81
5.87
2.56
0.38
°C/W
010
025
050
060
FG484
090
150
Revision 4
15
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
4.3.2 Theta-JA
Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by JEDEC (JESD-51),
but it has little relevance in actual performance of the product. It must be used with caution, but it is useful for
comparing the thermal performance of one package to another.
The maximum power dissipation allowed is calculated using EQ 4.
T J(MAX) – T A(MAX)
Maximum Power Allowed = ------------------------------------------- JA
EQ 4
The absolute maximum junction temperature is 100°C. EQ 5 shows a sample calculation of the absolute maximum
power dissipation allowed for the M2GL050-FG484 package at Military temperature and in still air, where:
JA
= 15.29°C/W (taken from Table 7 on page 15)
TA
= 85°C
– 85°C = 0.981 W
Maximum Power Allowed = 100°C
-----------------------------------15.29°C/W
EQ 5
The power consumption of a device can be calculated using the Microsemi SoC Products Group power calculator. The
device's power consumption must be lower than the calculated maximum power dissipation by the package.
If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be
attached on top of the case, or the airflow inside the system must be increased.
4.3.3 Theta-JB
Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the surface of the
chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from junction to board uses an
isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary
condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm
away from the package edge.
4.3.4 Theta-JC
Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the surface of the chip
to the top or bottom surface of the package. It is applicable for packages used with external heat sinks. Constant
temperature is applied to the surface in consideration and acts as a boundary condition.
This only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration.
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
5. Power Consumption
5.1 Quiescent Supply Current
Table 8 •
Quiescent Supply Current Characteristics
Modes and Configurations
Power Supplies/Blocks
Non-Flash*Freeze Mode Flash*Freeze Mode Notes
FPGA Core
On
Off
–
VDD / SERDES_[01]_VDD
On
On
1
VPP / VPPNVM
On
On
–
MDDR_PLL_VDDA
CCC_XX[01]_PLL_VDDA
PLL0_PLL1_MDDR_VDDA
FDDR_PLL_VDDA
0V
0V
–
SERDES_[01]_PLL_VDDA
0V
0V
3
SERDES_[01]_L[0123]_VDDAPLL / VDD_2V5
On
On
3
SERDES_[01]_L[0123]_VDDAIIO
On
On
3
VDDIx
On
On
2, 4
VREFx
On
On
–
32 kHz
32 kHz
–
On
Sleep state
–
HPMS Controller
50 MHz
50 MHz
–
50 MHz Oscillator (enable/disable)
Enabled
Disabled
–
1 MHz Oscillator (enable/disable)
Disabled
Disabled
–
Crystal Oscillator (enable/disable)
Disabled
Disabled
–
MSSDDR CLK
RAM
Notes:
1. SERDES_[01]_VDD Power Supply is shorted to VDD.
2. VDDIx has been set to ON for test conditions as described. Banks on the east side should always be powered with the
appropriate VDDI Bank supplies. For details on bank power supplies, refer to the “Recommendation for Unused Bank
Supplies” table in the AC393: SmartFusion2 and IGLOO2 Board Design Guidelines Application Note.
3. SERDES and DDR blocks to be unused.
4. No Differential (that is to say, LVDS) I/O’s or ODT attributes to be used.
Table 9 •
SmartFusion2 and IGLOO2 Quiescent Supply Current – Typical Process
010
Parameter
IDC1
IDC2
Modes
NonFlash*Freeze
Flash*Freeze
Conditions
025
050
090
150
VDD=1.2 V VDD=1.2 V VDD=1.2 V VDD=1.2 V VDD=1.2 V Units
Typical
(TJ = 25°C)
6.9
8.9
13.1
15.4
27.5
mA
Military
(TJ = 125°C)
73.0
106.4
180.9
217.5
390.5
mA
Typical
(TJ = 25°C)
2.6
3.7
5.1
5.1
8.9
mA
Military
(TJ = 125°C)
55.6
74.2
98.5
99.5
161.0
mA
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 10 • SmartFusion2 and IGLOO2 Quiescent Supply Current – Worst-Case Process
010
Parameter
Modes
025
050
090
150
Conditions VDD=1.26 V VDD=1.26 V VDD=1.26 V VDD=1.26 V VDD=1.26 V Units
IDC1
NonMilitary
Flash*Freeze (TJ = 125°C)
151.5
227.4
358.9
443.1
660.4
mA
IDC2
Flash*Freeze
Military
(TJ = 125°C)
127.2
144.2
174.6
195.0
236.3
mA
5.2 Programming Currents
The tables below represent programming, verify and Inrush currents for SmartFusion2 SoC and IGLOO2 FPGA
devices.
Table 11 • Currents During Program Cycle, 0°C < = TJ <= 85°C, Typical Process
Power Supplies
Voltage (V)
010
025
050
090
150
Units
Notes
VDD
1.26
53
55
58
42
52
mA
–
VPP
3.46
11
6
10
12
12
mA
–
VPPNVM
3.46
2
2
3
3
–
mA
*
2.62
16
17
1
12
81
mA
**
3.46
31
36
1
17
84
mA
**
8
8
10
9
19
–
–
VDDI
Number of banks
Notes:
* VPP and VPPNVM are internally shorted.
** The current for 050 represents JTAG I/O Bank only.
Table 12 • Currents During Verify Cycle, 0°C <= TJ <= 85°C, Typical Process
Power Supplies
Voltage (V)
010
025
050
090
150
Units
Notes
VDD
1.26
53
55
58
41
51
mA
–
VPP
3.46
5
3
15
11
12
mA
–
VPPNVM
3.46
0
0
1
1
–
mA
*
VDDI
2.62
16
17
1
11
81
mA
**
3.46
32
36
1
17
84
mA
**
8
8
10
9
19
–
–
Number of banks
Notes:
* VPP and VPPNVM are internally shorted.
** The current for 050 represents JTAG I/O Bank only.
Table 13 • Inrush Currents at Power up, –55°C <= TJ <=125°C, Typical Process
Power Supplies
Voltage (V)
010
025
050
090
150
Units
VDD
1.26
53
78
57
98
140
mA
VPP
3.46
57
50
180
36
51
mA
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 13 • Inrush Currents at Power up, –55°C <= TJ <=125°C, Typical Process
VDDI
2.62
141
161
187
283
404
mA
8
8
10
9
19
–
Number of banks
6. Average Fabric Temperature and Voltage Derating Factors
Table 14 • Average Temperature and Voltage Derating Factors for Fabric Timing Delays
(Normalized to TJ = 125°C, Worst-Case VDD = 1.14 V)
Core Voltage VDD (V)
Junction Temperature (°C)
–55°C
–40°C
0°C
25°C
70°C
85°C
100°C
125°C
1.14
0.91
0.91
0.93
0.94
0.96
0.97
0.98
1.00
1.2
0.82
0.83
0.84
0.85
0.87
0.87
0.88
0.90
1.26
0.75
0.75
0.77
0.77
0.79
0.80
0.81
0.75
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
7. Timing Model
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Figure 1 • Timing Model
Revision 4
20
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 15 • Timing Model Parameters
Index Parameter
A
Description
Speed
Grade
–1
Units
Notes
tPY
Propagation Delay of DDR3 Receiver
1.672
ns
Refer to page 52 for more
information
tICLKQ
Clock-to-Q of the Input Data Register
0.165
ns
Refer to page 67 for more
information
tISUD
Setup Time of the Input Data Register
0.369
ns
Refer to page 67 for more
information
tRCKH
Input High Delay for Global Clock
1.55
ns
Refer to page 78 for more
information
tRCKL
Input Low Delay for Global Clock
0.861
ns
Refer to page 78 for more
information
3.061
ns
Refer to page 58 for more
information
B
C
D
tPY
Input Propagation
Receiver
Delay
of
LVDS
E
tDP
Propagation Delay of a three input AND
Gate
0.217
ns
Refer to page 76 for more
information
F
tDP
Propagation Delay of a OR Gate
0.17
ns
Refer to page 76 for more
information
G
tDP
Propagation Delay of a LVDS Transmitter
2.299
ns
Refer to page 58 for more
information
H
tDP
Propagation Delay of a three input XOR
Gate
0.236
ns
Refer to page 76 for more
information
I
tDP
Propagation Delay of LVCMOS 2.5 V
Transmitter, Drive strength of 16mA on
the MSIO Bank
2.717
ns
Refer to page 31 for more
information
J
tDP
Propagation Delay of a two input NAND
Gate
0.17
ns
Refer to page 76 for more
information
K
tDP
Propagation Delay of LVCMOS 2.5 V
Transmitter, Drive strength of 8mA on the
MSIO Bank
2.594
ns
Refer to page 31 for more
information
tCLKQ
Clock-to-Q of the Data Register
0.112
ns
Refer to page 67 for more
information
tSUD
Setup Time of the Data Register
0.262
ns
Refer to page 67 for more
information
tDP
Propagation Delay of a two input AND
gate
0.17
ns
Refer to page 76 for more
information
tOCLKQ
Clock-to-Q of the Output Data Register
0.272
ns
Refer to page 69 for more
information
tOSUD
Setup Time of the Output Data Register
0.196
ns
Refer to page 69 for more
information
L
M
N
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 15 • Timing Model Parameters (continued)
Index Parameter
Description
Speed
Grade
–1
Units
Notes
O
tDP
Propagation Delay of SSTL2, Class I
Transmitter on the MSIO Bank
2.283
ns
Refer to page 47 for more
information
P
tDP
Propagation Delay of LVCMOS 1.5 V
Transmitter, Drive strength of 12mA, fast
slew on the DDRIO Bank
3.703
ns
Refer to page 38 for more
information
8. User I/O Characteristics
There are three types of I/Os supported in the IGLOO2 FPGA and SmartFusion2 SoC FPGA families: MSIO, MSIOD,
and DDRIO I/O banks. The I/O standards supported by the different I/O banks is described in the “I/Os” section of the
UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide.
8.1 Input Buffer and AC Loading
tPY
tPYS
PAD
Y
IN
tPY = MAX(tPY(R), tPY(F))
tPYS = MAX(tPYS(R), tPYS(F))
VIH
Vtrip
IN
Vtrip
VIL
VDD
50%
50%
Y
GND
tPY
tPY
(R)
(F)
tPYS
(R)
tPYS
(F)
Figure 2 • Input Buffer AC Loading
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.2. Output Buffer and AC Loading
Single-Ended I/O Test Setup
HSTL/PCI Test Setup
tDP
tDP
PAD
OUT
D
VTT/VDDI
PAD
OUT
D
Rtt_test
Cload
Cload
tDP = MAX(tDP(R), tDP(F))
tDP = MAX(tDP(R), tDP(F))
Voltage-Referenced, Singled-Ended I/O Test Setup
tDP
D
VTT
OUT
PAD
Rtt_test
Cload
tDP = MAX(tDP(R), tDP(F))
Differential I/O Test Setup
tDP
OUT
tPY
PAD_P
PAD_P
D
IN
PAD_N
PAD_N
tPY = MAX(tPY(R), tPY(F))
tDP = MAX(tDP(R), tDP(F))
tPYS = MAX(tPYS(R), tPYS(F))
Figure 3 • Output Buffer AC Loading
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.3. Tristate Buffer and AC Loading
The tristate path for enable path loadings is described in the respective specifications. The methodology of
characterization is illustrated by the enable path test point shown in Figure 4.
tZL, tZH, tHZ, tLZ
E
OUT
D
Rent to VDDI for tZL, tLZ
PAD
Cent tZL, tLZ, tZH, tHZ
Rent to GND for tZH, tHZ
Data
(D)
Enable
(E)
50%
tZL
PAD
50%
50%
tHZ
tZH
50%
tLZ
90% VDDI
90% VDDI
10% VDDI
10% VDDI
Figure 4 • Tristate Buffer for Enable Path Test Point
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.4 I/O Speeds
Table 16 • Maximum Data Rate Summary for Worst-Case Military Conditions
Single-Ended I/O
MSIO
MSIOD
DDRIO
Units
PCI 3.3 V
560
–
–
Mbps
LVTTL 3.3 V
540
–
–
Mbps
LVCMOS 3.3 V
540
–
–
Mbps
LVCMOS 2.5 V
360
370
360
Mbps
LVCMOS 1.8 V
260
360
360
Mbps
LVCMOS 1.5 V
140
190
210
Mbps
LVCMOS 1.2 V
100
140
180
Mbps
–
–
360
Mbps
MSIO
MSIOD
DDRIO
Units
LPDDR
–
–
360
Mbps
HSTL1.5 V
–
–
360
Mbps
SSTL 2.5 V
450
480
360
Mbps
SSTL 1.8 V
–
–
600
Mbps
MSIO
MSIOD
DDRIO
Units
–
–
600
Mbps
MSIO
MSIOD
DDRIO
Units
LVPECL (input only)
810
–
–
Mbps
LVDS 3.3 V
480
480
–
Mbps
LVDS 2.5 V
480
480
–
Mbps
RSDS
460
480
–
Mbps
BLVDS
450
–
–
Mbps
MLVDS
450
–
–
Mbps
Mini-LVDS
460
480
–
Mbps
LPDDR – LVCMOS 1.8 V Mode
Voltage-Referenced I/O
Voltage-Referenced I/O
SSTL 1.5 V
Differential I/O
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 17 • Maximum Frequency Summary for Worst-Case Military Conditions
Single-Ended I/O
MSIO
MSIOD
DDRIO
Units
PCI 3.3 V
280
–
–
MHz
LVTTL 3.3 V
270
–
–
MHz
LVCMOS 3.3 V
270
–
–
MHz
LVCMOS 2.5 V
180
185
180
MHz
LVCMOS 1.8 V
130
180
180
MHz
LVCMOS 1.5 V
70
95
105
MHz
LVCMOS 1.2 V
50
70
90
MHz
LPDDR - LVCMOS 1.8 V mode
–
–
180
MHz
Voltage-Referenced I/O
MSIO
MSIOD
DDRIO
Units
LPDDR
–
–
180
MHz
HSTL1.5 V
–
–
180
MHz
SSTL 2.5 V
225
240
180
MHz
SSTL 1.8 V
–
–
300
MHz
SSTL 1.5 V
–
–
300
MHz
MSIO
MSIOD
DDRIO
Units
LVPECL (input only)
405
–
–
MHz
LVDS 3.3 V
240
240
–
MHz
LVDS 2.5 V
240
240
–
MHz
RSDS
230
240
–
MHz
BLVDS
225
–
–
MHz
MLVDS
225
–
–
MHz
Mini-LVDS
230
240
–
MHz
Differential I/O
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.5 Detailed I/O Characteristics
Table 18 • Input Capacitance
Symbol
CIN
Definition
Min
Max
Units
Input Capacitance
–
10
pF
Table 19 • I/O Weak Pull-Up/Pull-Down Resistance Values for DDRIO, MSIO, and MSIOD Banks
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values at VOH/VOL Level
VDDI Domain
DDRIO I/O Bank
MSIO I/O Bank
MSIOD I/O Bank
R(WEAK
R(WEAK
R(WEAK
R(WEAK
R(WEAK
R(WEAK
PULL-UP)
PULL-DOWN)
PULL-UP)
PULL-DOWN)
PULL-UP)
PULL-DOWN)
at VOH ()
at VOL ()
at VOH ()
at VOL ()
at VOH ()
at VOL ()
Min
Max
Min
Max
Min
3.3 V
N/A
N/A
N/A
N/A
9.9K
2.5 V
10K
15.1K 9.98K 15.3K
10K
Max
Min
Max
14.5K 9.98K 14.9K
15K
Min
Max
Min
Max
N/A
N/A
N/A
N/A
Notes
10.1K 15.6K
9.6K
14.1K 9.5K 13.9K
1,2
1.8 V
10.3K 16.2K 10.3K 16.6K 10.4K 16.2K 10.4K 17.3K
9.7K
14.7K 9.7K 14.5K
1,2
1.5 V
10.6K 17.2K 10.6K 17.9K 10.7K 17.3K 10.8K 18.9K
9.9K
15.3K 9.8K
1,2
1.2 V
11.1K 19.3K 11.2K 20.9K 11.3K 19.7K 11.5K 22.7K 10.3K 16.7K 10K 16.2K
15K
1,2
Notes:
1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX)
2. R(WEAK PULL-UP) = (VDDImax - VOHspec)/I(WEAK PULL-UP MIN)
Table 20 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value for Schmitt Trigger Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (Typical, unless otherwise noted)
3.3 V LVTTL / LVCMOS / PCI / PCI-X
0.05 × VDDI (Worst-case)
2.5 V LVCMOS
0.05 × VDDI (Worst-case)
1.8 V LVCMOS
0.1 × VDDI (Worst-case)
1.5 V LVCMOS
60 mV
1.2 V LVCMOS
20 mV
8.6 Single-Ended I/O Standards
8.6.1 Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined by JEDEC
(JESD 8-5). The LVCMOS standards supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs are: LVCMOS12,
LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33.
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.6.2 3.3 V LVCMOS/LVTTL
LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V applications.
8.6.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 21 • LVTTL/LVCMOS 3.3 V DC Voltage Specification (Applicable to MSIO I/O Bank Only)
Symbol
Parameters
Conditions
Min
Typ
Max
Units
Notes
3.15
3.3
3.45
V
–
VIH (DC) DC input logic High
2.0
–
3.45
V
–
VIL (DC)
DC input logic Low
–0.3
–
0.8
V
–
IIH (DC)
Input current High
–
–
10
µA
–
IIL (DC)
Input current Low
–
–
10
µA
–
LVTTL/LVCMOS 3.3 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVTTL/LVCMOS 3.3 V DC Input Voltage Specification
LVCMOS 3.3 V DC Output Voltage Specification
VOH
DC output logic High
2.4
–
–
V
*
VOL
DC output logic Low
–
–
0.4
V
*
LVTTL 3.3 V DC Output Voltage Specification
VOH
DC output logic High
2.4
–
–
V
–
VOL
DC output logic Low
–
–
0.4
V
–
Note: * The VOH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B requirements.
Table 22 • LVTTL/LVCMOS 3.3 V Maximum Switching Speeds (Applicable to MSIO I/O Bank Only)
Symbol
Parameters
Conditions
Min
Typ
Max
Units
–
–
540
Mbps
LVTTL/LVCMOS 3.3 V Maximum Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load, maximum
drive/slew
Table 23 • LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO Bank Only)
LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications
Symbol
Parameters
Conditions
Min
Typ
Max
Units
Vtrip
Measuring/trip point for data path
–
1.4
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Revision 4
28
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 24 • LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications
(Applicable to MSIO Bank* Only)
Output Drive Selection
VOH (V)
VOL (V)
IOH (at VOH) mA
IOL (at VOL) mA
2 mA
2.4
0.4
2
2
4 mA
2.4
0.4
4
4
8 mA
2.4
0.4
8
8
12 mA
2.4
0.4
12
12
16 mA
2.4
0.4
16
16
20 mA
2.4
0.4
18
18
Note: * Software Configurator GUI displays the Commercial/Industrial numeric values. The actual drive capability at
temperature is defined in Table 24.
8.6.2.2 AC Switching Characteristics
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
AC Switching Characteristics for Receiver (Input Buffers)
Table 25 • LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Banks (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
LVTTL/LVCMOS 3.3 V (for MSIO I/O Bank)
Speed Grade
–1
On-Die Termination
(ODT)
tPY
tPYS
Units
None
2.416
2.443
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 26 • LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
Output Drive Selection
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
2mA
slow
3.515
3.826
3.242
2.024
3.636
ns
4mA
slow
2.565
2.948
2.774
3.339
4.896
ns
8mA
slow
2.349
2.568
2.528
5.013
5.329
ns
12mA
slow
2.261
2.324
2.386
6.389
6.05
ns
16mA
slow
2.274
2.287
2.369
6.671
6.256
ns
20mA
slow
2.372
2.206
2.306
6.976
6.541
ns
Revision 4
29
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.6.3 2.5 V LVCMOS
LVCMOS 2.5 V is a general standard for 2.5 V applications and is supported in IGLOO2 FPGA and SmartFusion2 SoC
FPGAs in compliance to the JEDEC specification JESD8-5A.
8.6.3.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 27 • LVCMOS 2.5 V DC Voltage Specification
Symbol
Parameters
Conditions
Min
Typ
Max
Units
Notes
2.375
2.5
2.625
V
–
LVCMOS 2.5 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVCMOS 2.5 V DC Input Voltage Specification
VIH (DC)
DC input logic High (for MSIOD and DDRIO I/O Bank)
1.7
–
2.625
V
–
VIH (DC)
DC input logic High (for MSIO I/O Bank)
1.7
–
2.75
V
–
VIL (DC)
DC input logic Low
–0.3
–
0.7
V
–
IIH (DC)
Input current High
–
–
10
µA
–
IIL (DC)
Input current Low
–
–
10
µA
–
LVCMOS 2.5 V DC Output Voltage Specification
VOH
DC output logic High
1.7
–
–
V
*
VOL
DC output logic Low
–
–
0.7
V
*
Note: * The VOH/VOL test points selected ensure compliance with LVCMOS 2.5 V JEDEC8-5A requirements.
Table 28 • LVCMOS 2.5 V Maximum AC Switching Speeds
Symbol
Parameters
Conditions
Min
Typ
Max
Units
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
370
Mbps
Table 29 • LVCMOS 2.5 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
75, 60,
50, 33,
25, 20
–

LVCMOS 2.5 V Calibrated Impedance Option
Rodt_cal
Supported output driver
calibrated impedance
(for DDRIO I/O Bank)
LVCMOS 2.5 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data
path
–
–
1.2
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable
path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Cload
Capacitive loading for data
path (tDP)
–
–
5
–
pF
Revision 4
30
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 30 • LVCMOS 2.5 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIOD
I/O Bank
DDRIO I/O Bank
(With Software Default
Fixed Code)
VOH (V)
Min
VOL (V)
Max
IOH (at VOH)
mA
IOL (at VOL)
mA
2 mA
2 mA
2 mA
1.7
0.7
2
2
4 mA
4 mA
4 mA
1.7
0.7
4
4
6 mA
6 mA
6 mA
1.7
0.7
6
6
8 mA
8 mA
8 mA
1.7
0.7
8
8
12 mA
12 mA
12 mA
1.7
0.7
12
12
16 mA
N/A
16 mA
1.7
0.7
16
16
MSIO
I/O Bank
Note: For board design considerations, output slew rates extraction, detailed output buffer resistances and I/V Curve
use the corresponding IBIS models located at:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
8.6.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 31 • LVCMOS 2.5 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
On-Die Termination
(ODT)
tPY
tPYS
Units
LVCMOS 2.5 V (for DDRIO I/O Bank)
None
1.903
2.021
ns
LVCMOS 2.5 V (for MSIO I/O Bank)
None
2.689
2.698
ns
LVCMOS 2.5 V (for MSIOD I/O Bank)
None
2.447
2.46
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 32 • LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Output Drive
Selection
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
slow
3.967
3.664
3.986
4.172
3.811
ns
medium
3.625
3.38
3.647
3.882
3.458
ns
medium_fast
3.485
3.259
3.507
3.747
3.327
ns
fast
3.458
3.253
3.48
3.74
3.31
ns
slow
3.371
2.942
3.362
5.148
4.71
ns
medium
3.063
2.701
3.059
4.874
4.381
ns
medium_fast
2.925
2.566
2.92
4.686
4.248
ns
fast
2.91
2.559
2.905
4.683
4.238
ns
LVCMOS 2.5 V (for DDRIO I/O Bank with Fixed Code)
2 mA
4 mA
Revision 4
31
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 32 • LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V (continued)
Output Drive
Selection
6 mA
8 mA
12 mA
16 mA
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
slow
3.189
2.716
3.169
5.56
5.092
ns
medium
2.886
2.473
2.876
5.273
4.752
ns
medium_fast
2.749
2.355
2.738
5.127
4.167
ns
fast
2.731
2.345
2.72
5.115
4.6
ns
slow
3.132
2.646
3.109
5.686
5.207
ns
medium
2.832
2.407
2.82
5.402
4.864
ns
medium_fast
2.698
2.292
2.685
5.262
4.732
ns
fast
2.684
2.282
2.671
5.252
4.724
ns
slow
3.013
2.504
2.984
5.918
5.416
ns
medium
2.72
2.284
2.707
5.657
5.074
ns
medium_fast
2.592
2.176
2.578
5.537
4.949
ns
fast
2.58
2.166
2.566
5.529
4.946
ns
slow
2.936
2.415
2.902
6.136
5.577
ns
medium
2.66
2.206
2.645
5.901
5.261
ns
medium_fast
2.536
2.102
2.519
5.815
5.142
ns
fast
2.523
2.093
2.506
5.81
5.137
ns
LVCMOS 2.5 V (for MSIO I/O Bank)
2 mA
slow
3.933
4.352
4.22
2.358
3.838
ns
4 mA
slow
2.905
3.423
3.508
4.681
5.262
ns
6 mA
slow
2.687
2.995
3.155
5.561
5.73
ns
8 mA
slow
2.594
2.877
3.07
6.602
6.248
ns
12 mA
slow
2.623
2.732
2.944
6.974
6.478
ns
16 mA
slow
2.717
2.617
2.84
7.455
6.824
ns
LVCMOS 2.5 V (for MSIOD I/O Bank)
2 mA
slow
2.403
2.922
2.89
5.397
5.202
ns
4 mA
slow
1.998
2.446
2.468
5.936
5.665
ns
6 mA
slow
1.861
2.329
2.375
6.391
6.068
ns
8 mA
slow
1.781
2.145
2.208
6.884
6.44
ns
12 mA
slow
1.804
2.039
2.108
7.23
6.685
ns
Revision 4
32
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.6.4 1.8 V LVCMOS
LVCMOS 1.8 is a general standard for 1.8 V applications and is supported in IGLOO2 FPGAs and SmartFusion2 SoC
FPGAs in compliance to the JEDEC specification JESD8-7A.
8.6.4.1 Minimum and Maximum AC/DC Input and Output Levels
Table 33 • LVCMOS 1.8 V DC Voltage Specification
Symbols
Parameters
Min
Typ
Max
Units
1.710
1.8
1.89
V
Recommended DC Operating Conditions
VDDI
Supply Voltage
LVCMOS 1.8 V DC Input Voltage Specification
VIH(DC)
DC input Logic HIGH (for MSIOD and
0.65 x VDDI
DDRIO I/O Banks)
–
1.89
V
VIH(DC)
DC input Logic HIGH (for MSIO I/O
0.65 x VDDI
Bank)
–
2.75
V
VIL(DC)
DC input Logic LOW
-0.3
–
0.35 × VDDI
V
IIH(DC)
Input Current HIGH
–
–
10
uA
IIL(DC)
Input Current LOW
–
–
10
uA
LVCMOS 1.8 V DC Output Voltage Specification
VOH
DC output Logic HIGH
VDDI - 0.45
–
–
V
VOL
DC output Logic LOW
–
–
0.45
V
Table 34 • LVCMOS 1.8 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVCMOS 1.8 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
260
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Note: * Maximum data rate applies for drive strength 8mA and above, all slews
Table 35 • LVCMOS 1.8 V Transmitter Drive Strength Specifications
Output Drive Selection
VOH (V)
VOL (V)
MSIOD I/O Bank
Min
Max
IOH (at VOH)
mA
IOL (at VOL)
mA
2 mA
2 mA
VDDI – 0.45
0.45
2
2
4 mA
4 mA
VDDI – 0.45
0.45
4
4
6 mA
6 mA
VDDI – 0.45
0.45
6
6
8 mA
8 mA
VDDI – 0.45
0.45
8
8
10 mA
10 mA
VDDI – 0.45
0.45
10
10
12 mA
N/A
VDDI – 0.45
0.45
12
12
MSIO I/O Bank
Revision 4
33
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 36 • LVCMOS 1.8 V Transmitter Drive Strength Specifications
Output Drive
Selection
VOH (V)
VOL (V)
DDRIO Bank*
Min
Max
2 mA
VDDI – 0.45
0.45
2
2
–
4 mA
VDDI – 0.45
0.45
4
4
–
6 mA
VDDI – 0.45
0.45
6
6
**
8 mA
VDDI – 0.45
0.45
6
6
**
10 mA
VDDI – 0.45
0.45
8
8
–
12 mA
VDDI – 0.45
0.45
10
10
–
16 mA
VDDI – 0.45
0.45
12
12
–
IOH (at VOH) mA IOL (at VOL) mA
Notes
Notes:
* Software Configurator GUI will display the Commercial/Industrial numeric values. The actual drive capability at
temperature is defined by Table 36.
** DDRIO has two 6mA drive strength settings. The setting that corresponds to Output Drive Selection value of 8mA
has a shorter propagation delay.
Table 37 • LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications
LVCMOS 1.8 V AC Calibrated Impedance Option
Symbols
Rodt_cal
Parameters
Supported output driver calibrated impedance
(for DDRIO I/O Bank)
Min
Typ
Max
Units
–
75, 60, 50,
33, 25, 20
–

LVCMOS 1.8 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.9
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Revision 4
34
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.6.4.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 38 • LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
Speed Grade
–1
tPYS
tPY
ODT
(On Die Termination)
LVCMOS 1.8 V
(for DDRIO I/O Bank with Fixed Codes)
LVCMOS 1.8 V (for MSIO I/O Bank)
LVCMOS 1.8 V (for MSIOD I/O Bank)
Units
None
2.071
2.213
ns
None
3.185
3.171
ns
50
3.394
3.397
ns
75
3.322
3.316
ns
150
3.252
3.239
ns
None
2.827
2.813
ns
50
3.043
3.053
ns
75
2.968
2.963
ns
150
2.898
2.886
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 39 • LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
Output Drive Selection
Slew Control
4 mA
6 mA
8 mA
10 mA
tHZ
tLZ
Units
4.017
4.69
5.388
4.852
ns
tDP
LVCMOS 1.8 V (for DDRIO I/O Bank with Fixed Codes)
slow
4.681
2 mA
tZL
Speed Grade
–1
tZH
medium
4.211
3.599
4.219
5.058
4.488
ns
medium_fast
3.978
3.392
3.986
4.874
4.327
ns
fast
3.953
3.373
3.961
4.858
4.316
ns
slow
4.355
3.657
4.346
5.967
5.399
ns
medium
3.886
3.246
3.879
5.628
5.01
ns
medium_fast
3.656
3.05
3.647
5.461
4.845
ns
fast
3.635
3.033
3.626
5.447
4.838
ns
slow
4.105
3.422
4.092
6.221
5.599
ns
medium
3.68
3.05
3.668
5.9
5.257
ns
medium_fast
3.477
2.867
3.463
5.739
5.118
ns
fast
3.451
2.849
3.437
5.72
5.104
ns
slow
4.015
3.32
3.998
6.458
5.808
ns
medium
3.59
2.947
3.574
6.129
5.449
ns
medium_fast
3.383
2.761
3.366
5.963
5.304
ns
fast
3.357
2.746
3.34
5.954
5.289
ns
slow
3.888
3.18
3.864
6.739
6.045
ns
medium
3.485
2.822
3.467
6.422
5.7
ns
medium_fast
3.281
2.642
3.26
6.277
5.553
ns
fast
3.258
2.627
3.238
6.27
5.546
ns
Revision 4
35
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 39 • LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V (continued)
Output Drive Selection
12 mA
Slew Control
slow
tDP
3.795
Speed Grade
–1
tZL
tZH
tHZ
3.096
3.773
6.773
medium
3.408
2.764
3.389
6.47
tLZ
6.067
Units
ns
5.743
ns
medium_fast
3.215
2.599
3.194
6.346
5.61
ns
fast
3.196
2.584
3.175
6.335
5.604
ns
slow
3.744
3.035
3.719
6.944
6.207
ns
medium
3.358
2.712
3.339
6.657
5.868
ns
medium_fast
3.175
2.546
3.153
6.547
5.751
ns
fast
3.156
2.531
3.133
6.541
5.747
ns
LVCMOS 1.8 V (for MSIO I/O Bank)
2 mA
slow
3.957
4.784
5.023
5.643
5.866
ns
4 mA
slow
3.668
4.162
4.485
6.543
6.382
ns
6 mA
slow
3.586
3.994
4.358
7.622
6.941
ns
8 mA
slow
3.616
3.782
4.162
7.988
7.161
ns
10 mA
slow
3.662
3.732
4.121
8.396
7.423
ns
12 mA
slow
3.75
3.615
4.006
8.576
7.543
ns
LVCMOS 1.8 V (for MSIOD I/O Bank)
2 mA
slow
3.048
3.692
3.898
5.818
5.609
ns
3.288
6.421
6.121
ns
16 mA
4 mA
slow
2.5
3.088
6 mA
slow
2.225
2.747
2.937
7.18
6.753
ns
8 mA
slow
2.233
2.72
2.904
7.49
6.992
ns
10 mA
slow
2.263
2.577
2.759
7.851
7.253
ns
8.6.5 1.5 V LVCMOS
LVCMOS 1.5 is a general standard for 1.5 V applications and is supported in IGLOO2 FPGAs and SmartFusion2 SoC
FPGAs in compliance to the JEDEC specification JESD8-11A.
8.6.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 40 • LVCMOS 1.5 V Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Min
Typ
Max
Units
1.425
1.5
1.575
V
LVCMOS 1.5 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVCMOS 1.5 V DC Input Voltage Specification
VIH (DC)
DC input logic High for (MSIOD and DDRIO I/O banks)
0.65 × VDDI
–
1.575
V
VIH (DC)
DC input logic High (for MSIO I/O Bank)
0.65 × VDDI
–
2.75
V
VIL (DC)
DC input logic Low
–0.3
–
0.35 × VDDI
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC
Input current Low
–
–
10
µA
LVCMOS 1.5 V DC Output Voltage Specification
VOH
DC output logic High
VDDI × 0.75
–
–
V
VOL
DC output logic Low
–
–
VDDI × 0.25
V
Revision 4
36
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 41 • LVCMOS 1.5 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVCMOS 1.5 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
210
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
140
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
190
Mbps
Min
Typ
Max
Units
–
75, 60,
50, 40
–

Table 42 • LVCMOS 1.5 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Conditions
LVCMOS 1.5 V AC Calibrated Impedance Option
Rodt_cal
Supported output driver calibrated impedance
(for DDRIO I/O Bank)
LVCMOS 1.5 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.75
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 43 • LVCMOS 1.5 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIO I/O Bank
DDRIO I/O Bank
MSIOD I/O Bank (with Fixed Code)
VOH (V)
VOL (V)
Min
Max
IOH (at VOH) IOL (at VOL)
mA
mA
2 mA
2 mA
2 mA
VDDI × 0.75
VDDI × 0.25
2
2
4 mA
4 mA
4 mA
VDDI × 0.75
VDDI × 0.25
4
4
6 mA
6 mA
6 mA
VDDI × 0.75
VDDI × 0.25
6
6
8 mA
N/A
8 mA
VDDI × 0.75
VDDI × 0.25
8
8
N/A
N/A
10 mA
VDDI × 0.75
VDDI × 0.25
10
10
N/A
N/A
12 mA
VDDI × 0.75
VDDI × 0.25
12
12
Revision 4
37
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.6.5.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 44 • LVCMOS 1.5 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.425 V
Speed Grade
–1
ODT (On Die Termination)
tPY
tPYS
Units
none
2.19
2.216
ns
none
3.679
3.652
ns
50
4.151
4.126
ns
75
3.984
3.953
ns
150
3.823
3.791
ns
none
3.262
3.229
ns
50
3.76
3.739
ns
75
3.555
3.52
ns
150
3.395
3.359
ns
LVCMOS 1.5 V (for DDRIO I/O Bank
with Fixed Codes)
LVCMOS 1.5 V (for MSIO I/O Bank)
LVCMOS 1.5 V (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 45 • LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI=1.425 V
Output Drive
Selection
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
LVCMOS 1.5 V (for DDRIO I/O Bank with Fixed Codes)
2 mA
4 mA
6 mA
slow
5.712
4.796
5.735
5.814
5.138
ns
medium
5.094
4.274
5.114
5.484
4.779
ns
medium_fast
4.793
4.013
4.81
5.288
4.625
ns
fast
4.762
3.98
4.78
5.261
4.615
ns
slow
4.966
4.133
4.956
6.763
6.05
ns
medium
4.412
3.62
4.401
6.433
5.664
ns
medium_fast
4.145
3.358
4.131
6.249
5.507
ns
fast
4.116
3.338
4.103
6.238
5.498
ns
slow
4.744
3.869
4.728
7.173
6.383
ns
medium
4.212
3.382
4.195
6.837
6.004
ns
medium_fast
3.951
3.135
3.93
6.668
5.861
ns
fast
3.919
3.11
3.899
6.644
5.845
ns
Revision 4
38
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 45 • LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI=1.425 V (continued)
Speed Grade
–1
Output Drive
Selection
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
slow
4.603
3.691
4.585
7.397
6.553
ns
medium
4.081
3.242
4.062
7.064
6.189
ns
medium_fast
3.827
3.015
3.804
6.912
6.051
ns
fast
3.804
2.994
3.781
6.903
6.051
ns
slow
4.519
3.612
4.499
7.578
6.676
ns
medium
4.026
3.177
4.005
7.264
6.335
ns
medium_fast
3.775
2.948
3.75
7.11
6.198
ns
fast
3.747
2.929
3.721
7.103
6.19
ns
slow
4.456
3.562
4.433
7.704
6.795
ns
medium
3.965
3.13
3.943
7.388
6.425
ns
medium_fast
3.731
2.912
3.704
7.278
6.303
ns
fast
3.703
2.893
3.676
7.275
6.294
ns
8 mA
10 mA
12 mA
LVCMOS 1.5 V (for MSIO I/O Bank)
2 mA
slow
5.118
6.263
6.53
6.524
6.388
ns
4 mA
slow
4.657
5.178
5.65
8.57
7.55
ns
6 mA
slow
4.693
4.89
5.389
8.928
7.766
ns
8 mA
slow
4.876
4.663
5.183
9.59
8.173
ns
LVCMOS 1.5 V (for MSIOD I/O Bank)
2 mA
slow
3.085
3.795
4.086
6.838
6.477
ns
4 mA
slow
2.731
3.365
3.631
7.663
7.165
ns
6 mA
slow
2.742
3.162
3.417
8.126
7.52
ns
8.6.6 1.2 V LVCMOS
LVCMOS 1.2 is a general standard for 1.2 V applications and is supported in IGLOO2 FPGAs and SmartFusion2 SoC
FPGAs in compliance to the JEDEC specification JESD8-12A.
8.6.6.1 Minimum and Maximum Input and Output Levels Specification
Table 46 • LVCMOS 1.2 V Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Conditions
Min
Typ
Max
Units
1.140
1.2
1.26
V
VIH (DC) DC input logic High (for MSIOD and DDRIO I/O Banks)
0.65 × VDDI
–
1.26
V
VIH (DC) DC input logic High (for MSIO I/O Bank)
0.65 × VDDI
–
2.75
V
LVCMOS 1.2 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVCMOS 1.2 V DC Input Voltage Specification
VIL (DC)
DC input logic Low
–0.3
–
0.35 × VDDI
V
IIH (DC)
Input current High
–
–
10
µA
Revision 4
39
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 46 • LVCMOS 1.2 V Minimum and Maximum DC Input and Output Levels
IIL (DC)
Input current Low
–
–
10
µA
LVCMOS 1.2 V DC Output Voltage Specification
VOH
DC output logic High
–
VDDI × 0.75
–
–
V
VOL
DC output logic Low
–
–
–
VDDI × 0.25
V
Min
Typ
Max
Units
Table 47 • LVCMOS 1.2 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
LVCMOS 1.2 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
180
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
100
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
140
Mbps
Table 48 • LVCMOS 1.2 V AC Calibrated Impedance and Test Parameters Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
75, 60,
50, 40
–

LVCMOS 1.2 V AC Calibrated Impedance Option
Rodt_cal
Supported output driver calibrated impedance
(for DDRIO I/O Bank)
LVCMOS 1.2 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.6
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 49 • LVCMOS 1.2 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIO I/O Bank
DDRIO I/O Bank
MSIOD I/O Bank (with Fixed Code)
VOH (V)
VOL (V)
Min
Max
IOH (at VOH)
mA
IOL (at VOL)
mA
2 mA
2 mA
2 mA
VDDI × 0.75 VDDI × 0.25
2
2
4 mA
4 mA
4 mA
VDDI × 0.75 VDDI × 0.25
4
4
N/A
6 mA
VDDI × 0.75 VDDI × 0.25
6
6
N/A
Revision 4
40
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.6.6.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 50 • LVCMOS 1.2 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.14 V
Speed Grade
–1
ODT (On Die Termination)
tPY
tPYS
Units
none
2.539
2.556
ns
none
4.888
4.845
ns
50
6.683
6.605
ns
75
5.923
5.847
ns
150
5.29
5.235
ns
none
4.281
4.235
ns
50
6.806
6.721
ns
75
5.643
5.564
ns
150
4.813
4.753
ns
LVCMOS 1.2 V (for DDRIO I/O Bank
with Fixed Codes)
LVCMOS 1.2 V (for MSIO I/O Bank)
LVCMOS 1.2 V (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 51 • LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.14 V
Output Drive
Selection
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
slow
6.938
5.599
6.948
7.568
6.612
ns
medium
6.11
4.814
6.114
7.201
6.234
ns
medium_fast
5.675
4.409
5.676
6.971
6.048
ns
fast
5.633
4.379
5.634
6.958
6.037
ns
slow
6.328
4.892
6.316
8.339
7.306
ns
medium
5.538
4.192
5.521
7.961
6.923
ns
medium_fast
5.119
3.832
5.097
7.76
6.741
ns
fast
5.072
3.085
5.051
7.752
6.725
ns
slow
6.092
4.681
6.075
8.685
7.589
ns
medium
5.342
4.016
5.32
8.33
7.19
ns
medium_fast
4.949
3.66
4.922
8.139
7.022
ns
fast
4.903
3.622
4.876
8.107
7.006
ns
LVCMOS 1.2 V (for DDRIO I/O Bank with Fixed Code)
2 mA
4 mA
6 mA
LVCMOS 1.2 V (for MSIO I/O Bank)
2 mA
slow
7.051
7.856
8.541
10.387
8.768
ns
4 mA
slow
7.385
7.027
7.815
11.547
9.444
ns
Revision 4
41
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 51 • LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.14 V (continued)
Speed Grade
–1
Output Drive
Selection
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
LVCMOS 1.2 V (for MSIOD I/O Bank)
2 mA
slow
4.048
5.123
5.552
8.401
7.824
ns
4 mA
slow
3.941
4.406
4.814
9.422
8.656
ns
8.6.7 3.3 V PCI/PCIX
Peripheral Component Interface (PCI) for 3.3 V standards specify support for 33 MHz and 66 MHz PCI bus
applications.
8.6.7.1 Minimum and Maximum Input and Output Levels Specification
Table 52 • PCI/PCI-X DC Voltage Specification (Applicable to MSIO Bank Only
Symbols
Parameters
Conditions
Min
Typ
Max
Units
3.15
3.3
3.45
V
PCI/PCIX Recommended DC Operating Conditions
VDDI
Supply voltage
PCI/PCIX DC Input Voltage Specification
VI
DC input voltage
0
–
3.45
V
IIH(DC)
Input current High
–
–
10
µA
IIL(DC)
Input current Low
–
–
10
µA
PCI/PCIX DC Output Voltage Specification
VOH
DC output logic High
Per PCI Specification
V
VOL
DC output logic Low
Per PCI Specification
V
Min
Typ
Max
Units
–
–
560
Mbps
Table 53 • PCI/PCI-X AC Specifications (Applicable to MSIO Bank Only)
Symbols
Parameters
Conditions
PCI/PCI-X AC Specifications
Dmax
Maximum data rate (MSIO I/O AC Loading: per JEDEC
Bank)
specifications
PCI/PCI-X AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path (falling edge)
–
0.615 × VDDI
–
V
Vtrip
Measuring/trip point for data path (rising edge)
–
0.285 × VDDI
–
V
Rtt_test
Resistance for data test path
–
25
–

Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
10
–
pF
Revision 4
42
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.6.7.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 54 • PCI/PCIX AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
ODT
(On Die Termination)
tPY
tPYS
Units
None
2.379
2.387
ns
PCI/PCIX
(for MSIO I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 55 • PCI/PCIX AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 3.15 V
Speed Grade
–1
PCI/PCIX (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.394
2.274
2.316
6.876
6.242
ns
8.7 Memory Interface and Voltage Referenced I/O Standards
8.7.1 High-Speed Transceiver Logic (HSTL)
The High-Speed Transceiver Logic (HSTL) standard is a general purpose high-speed bus standard sponsored by IBM
(EIA/JESD8-6). IGLOO2 FPGA and SmartFusion2 SoC FPGA devices support two classes of the 1.5 V HSTL. These
differential versions of the standard require a differential amplifier input buffer and a push-pull output buffer.
8.7.1.1 Minimum and Maximum Input and Output Levels Specification
Table 56 • HSTL DC Voltage Specification (Applicable to DDRIO I/O Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
HSTL Recommended DC Operating Conditions
VDDI
Supply voltage
1.425
1.5
1.575
V
VTT
Termination voltage
0.698
0.750
0.803
V
VREF
Input reference voltage
0.698
0.750
0.803
V
HSTL DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.1
–
1.575
V
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.1
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
HSTL DC Output Voltage Specification
HSTL Class I
VOH
DC output logic High
VDDI – 0.4
–
–
V
VOL
DC output logic Low
–
–
0.4
V
IOH at VOH Output minimum source DC current
–7.0
–
–
mA
IOL at VOL
7.0
–
–
mA
VDDI – 0.4
–
–
V
Output minimum sink current
HSTL Class II
VOH
DC output logic High
Revision 4
43
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 56 • HSTL DC Voltage Specification (Applicable to DDRIO I/O Bank Only) (continued)
Symbols
Parameters
Min
Typ
Max
Units
–
–
0.4
V
IOH at VOH Output minimum source DC current
–15.0
–
–
mA
IOL at VOL
15.0
–
–
mA
0.2
–
–
V
Min
Typ
Max
Units
VOL
Conditions
DC output logic Low
Output minimum sink current
HSTL DC Differential Voltage Specifications
VID (DC)
DC input differential voltage
Table 57 • HSTL AC Specifications (Applicable to DDRIO Bank Only)
Symbols
Parameters
Conditions
HSTL AC Differential Voltage Specifications
VDIFF
AC input differential voltage
0.4
–
–
V
Vx
AC differential cross point voltage
0.68
–
0.9
V
–
–
360
Mbps
HSTL Maximum AC Switching Speed
Dmax
AC loading:
specifications
Maximum data rate
per
JEDEC
HSTL Impedance Specification
Rref
Supported output driver calibrated
Reference resistance = 191 
impedance (for DDRIO I/O Bank)
–
25.5,
47.8
–

RTT
Effective impedance value (ODT for
Reference resistance = 191 
DDRIO I/O Bank only)
–
47.8
–

HSTL AC Test Parameters Specification
Vtrip
Measuring/trip point for data path
–
0.75
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for HSTL15 Class I (tDP)
–
50
–

Rtt_test
Reference resistance for data test path for HSTL15 Class II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
8.7.1.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 58 • HSTL15 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
tPY
ODT (On Die Termination)
Speed Grade
–1
Units
HSTL (for DDRIO I/O Bank with Fixed Code)
Pseudo-Differential
None
1.673
ns
True-Differential
None
1.693
ns
Revision 4
44
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 59 • HSTL 15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.922
2.91
2.904
3.225
3.218
ns
Differential
2.907
2.757
2.755
2.662
2.66
ns
HSTL Class I (for DDRIO I/O Bank)
HSTL Class II (for DDRIO I/O Bank)
Single Ended
2.817
2.735
2.735
2.644
2.644
ns
Differential
2.827
2.81
2.803
3.205
3.197
ns
8.7.2 Stub-Series Terminated Logic
Stub-Series Terminated Logic (SSTL) for 2.5 V (SSTL2), 1.8 V (SSTL18), and 1.5 V (SSTL15) is supported in IGLOO2
and SmartFusion2 SoC FPGAs. SSTL2 is defined by JEDEC standard JESD8-9B and SSTL18 is defined by JEDEC
standard JESD8-15. IGLOO2 SSTL I/O configurations are designed to meet double data rate standards DDR/2/3 for
general purpose memory buses. Double data rate standards are designed to meet their JEDEC specifications as
defined by JEDEC standard JESD79F for DDR, JEDEC standard JESD79-2F for DDR, JEDEC standard JESD79-3D
for DDR3, and JEDEC standard JESD209A for LPDDR.
8.7.3 Stub-Series Terminated Logic 2.5 V (SSTL2)
SSTL2 Class I and Class II are supported in IGLOO2 and SmartFusion2 SoC FPGAs and also comply with reduced
and full drive of double data rate (DDR) standards. IGLOO2 and SmartFusion2 SoC FPGA I/Os supports both
standards for single-ended signaling and differential signaling for SSTL2. This standard requires a differential amplifier
input buffer and a push-pull output buffer.
8.7.3.1 Minimum and Maximum DC Input and Output Levels Specification
Table 60 • DDR1/SSTL2 Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Recommended DC Operating Conditions
VDDI
Supply voltage
2.375
2.5
2.625
V
VTT
Termination voltage
1.164
1.250
1.339
V
VREF
Input reference voltage
1.164
1.250
1.339
V
SSTL2 DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.15
–
2.625
V
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.15
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
SSTL2 DC Output Voltage Specification
SSTL2 Class I (DDR Reduced Drive)
VOH
DC output logic High
VTT + 0.608
–
–
V
VOL
DC output logic Low
–
–
VTT – 0.608
V
IOH at VOH
Output minimum source DC current
8.1
–
–
mA
Revision 4
45
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 60 • DDR1/SSTL2 Minimum and Maximum DC Input and Output Levels (continued)
Symbols
IOL at VOL
Parameters
Conditions
Output minimum sink current
Min
Typ
Max
Units
–8.1
–
–
mA
SSTL2 Class II (DDR Full Drive) – Applicable to MSIO and DDRIO I/O Banks Only
VOH
DC output logic High
VTT + 0.81
–
–
V
VOL
DC output logic Low
–
–
VTT – 0.81
V
IOH at VOH
Output minimum source DC current
16.2
–
–
mA
IOL at VOL
Output minimum sink current
–16.2
–
–
mA
0.3
–
–
V
SSTL2 DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Table 61 • DDR1/SSTL2 AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
SSTL2 Maximum AC Switching Speeds
Dmax
Maximum data rate (for AC loading: per JEDEC
DDRIO I/O Bank)
specifications
–
–
360
Mbps
Dmax
Maximum data rate (for
AC loading: 17pF load
MSIO I/O Bank)
–
–
450
Mbps
Dmax
Maximum data rate (for
AC loading: 17pF load
MSIOD I/O Bank)
–
–
480
Mbps
0.7
–
–
V
0.5 × VDDI - 0.2
–
0.5 × VDDI + 0.2
V
–
20, 42
–

SSTL2 AC Differential Voltage Specifications
VDIFF
AC Input
Voltage
Differential
Vx
AC Differential
Point Voltage
Cross
SSTL2 Impedance Specifications
Supported output driver
Reference resistor
calibrated impedance (for
= 150 
DDRIO I/O Bank)
SSTL2 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
1.25
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for SSTL2
Class I (tDP)
–
50
–

Rtt_test
Reference resistance for data test path for SSTL2
Class II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Revision 4
46
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.7.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 62 • DDR1/SSTL2 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
ODT (On Die Termination)
tPY
Units
Pseudo-Differential
None
1.613
ns
True-Differential
None
1.647
ns
Pseudo-Differential
None
3.083
ns
True-Differential
None
3.028
ns
Pseudo-Differential
None
2.721
ns
True-Differential
None
2.71
ns
SSTL2 (DDRIO I/O Bank)
SSTL2 (MSIO I/O Bank)
SSTL2 (MSIOD I/O Bank)
Table 63 • DDR1/SSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.457
2.145
2.137
2.302
2.293
ns
Differential
2.454
2.38
2.375
2.589
2.584
ns
Single Ended
2.283
2.255
2.243
2.286
2.273
ns
Differential
2.434
2.702
2.691
2.39
2.381
ns
Single Ended
1.646
1.59
1.589
1.82
1.818
ns
Differential
1.774
1.93
1.926
2.012
2.007
ns
Single Ended
2.317
2.06
2.053
2.229
2.221
ns
Differential
2.32
2.213
2.21
2.57
2.565
ns
SSTL2 Class I
DDRIO I/O Bank
MSIO I/O Bank
MSIOD I/O Bank
SSTL2 Class II
DDRIO I/O Bank
Revision 4
47
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 63 • DDR1/SSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V (continued)
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.563
2.208
2.19
2.205
2.187
ns
Differential
2.703
2.566
2.555
2.363
2.353
ns
MSIO I/O Bank
8.7.4 Stub-Series Terminated Logic 1.8 V (SSTL18)
SSTL18 Class I and Class II are supported in IGLOO2 and SmartFusion2 SoC FPGAs, and also comply with the
reduced and full drive double date rate (DDR2) standard. IGLOO2 and SmartFusion2 SoC FPGA I/Os support both
standards for single-ended signaling and differential signaling for SSTL18. This standard requires a differential
amplifier input buffer and a push-pull output buffer.
8.7.4.1 Minimum and Maximum Input and Output Levels Specification
Table 64 • DDR2/SSTL18 AC/DC Minimum and Maximum Input and Output Levels Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units Notes
Recommended DC Operating Conditions
VDDI
Supply voltage
1.71
1.8
1.89
V
–
VTT
Termination voltage
0.838
0.900
0.964
V
–
VREF
Input reference voltage
0.838
0.900
0.964
V
–
SSTL18 DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.125
–
1.89
V
–
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.125
V
–
IIH (DC)
Input current High
–
–
10
µA
–
IIL (DC)
Input current Low
–
–
10
µA
–
SSTL18 DC Output Voltage Specification
SSTL18 Class I (DDR2 Reduced Drive)
VOH
DC output logic High
VTT + 0.603
–
–
V
–
VOL
DC output logic Low
–
–
VTT– 0.603
V
–
IOH at VOH
Output minimum source DC current (DDRIO I/O
Bank only)
6.0
–
–
mA
–
IOL at VOL
Output minimum sink current (DDRIO I/O Bank
only)
–6.0
–
–
mA
–
*
SSTL18 Class II (DDR2 Full Drive)
VOH
DC output logic High
VTT + 0.603
–
–
V
–
VOL
DC output logic Low
–
–
VTT– 0.603
V
–
IOH at VOH
Output minimum source DC current (DDRIO I/O
Bank only)
12.0
–
–
mA
–
Note: *To meet JEDEC Electrical Compliance, use DDR2 Full Drive Transmitter.
Revision 4
48
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 64 • DDR2/SSTL18 AC/DC Minimum and Maximum Input and Output Levels Specification (continued)
Symbols
IOL at VOL
Parameters
Conditions
Output minimum sink current (DDRIO I/O Bank
only)
Min
Typ
Max
Units Notes
–12.0
–
–
mA
–
0.3
–
–
V
–
SSTL18 DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Note: *To meet JEDEC Electrical Compliance, use DDR2 Full Drive Transmitter.
Table 65 • DDR2/SSTL18 AC Specifications (Applicable to DDRIO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
0.5
–
–
V
0.5 × VDDI – 0.175
–
0.5 × VDDI + 0.175
V
–
–
600
Mbps
SSTL18 AC Differential Voltage Specification
VDIFF (AC) AC input differential voltage
Vx (AC)
AC differential cross point voltage
SSTL18 Maximum AC Switching Speed
Dmax
Maximum data rate (for AC
loading:
per
DDRIO I/O Bank)
JEDEC specification
SSTL18 Impedance Specifications
Rref
Supported output driver
Reference resistor
calibrated impedance
= 150 
(for DDRIO I/O Bank)
–
20, 42
–

RTT
Effective
impedance Reference resistor
value (ODT)
= 150 
–
50, 75,
150
–

SSTL18 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.9
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL,
tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for
SSTL18 Class I (tDP)
–
50
–

Rtt_test
Reference resistance for data test path for
SSTL18 Class II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Revision 4
49
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.7.4.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 66 • DDR2/SSTL18 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
Speed Grade
–1
On-Die Termination (ODT)
tPY
Units
SSTL18 (for DDRIO I/O Bank with Fixed Codes)
Pseudo differential
None
1.633
ns
True differential
None
1.65
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 67 • DDR2/SSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.67
3.078
3.072
2.489
2.484
ns
Differential
2.645
2.431
2.434
2.396
2.398
ns
Single Ended
2.564
2.973
2.965
2.45
2.444
ns
Differential
2.532
2.401
2.398
2.368
2.365
ns
SSTL18 Class I (for DDRIO I/O Bank)
SSTL18 Class II (for DDRIO I/O Bank
8.7.5 Stub-Series Terminated Logic 1.5 V (SSTL15)
SSTL15 Class I and Class II are supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs, and also comply with
the reduced and full drive double data rate (DDR3) standard. IGLOO2 FPGA and SmartFusion2 SoC FPGA I/Os
supports both standards for single-ended signaling and differential signaling for SSTL18. This standard requires a
differential amplifier input buffer and a push-pull output buffer.
8.7.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 68 • DDR3 SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Recommended DC Operating Conditions
VDDI
Supply voltage
1.425
1.5
1.575
V
VTT
Termination voltage
0.698
0.750
0.803
V
VREF
Input reference voltage
0.698
0.750
0.803
V
SSTL15 DC Input Voltage Specification
VIH(DC)
DC input logic High
VREF + 0.1
–
1.575
V
VIL(DC)
DC input logic Low
–0.3
–
VREF – 0.1
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
Revision 4
50
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 68 • DDR3 SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
SSTL15 DC Output Voltage Specification
DDR3/SSTL15 Class I (DDR3 Reduced Drive)
VOH
DC output logic High
0.8 x VDDI
–
–
V
VOL
DC output logic Low
–
–
0.2 x VDDI
V
IOH at VOH
Output minimum source DC current
6.5
–
–
mA
IOL at VOL
Output minimum sink current
–6.5
–
–
mA
SSTL15 Class II (DDR3 Full Drive)
VOH
DC output logic High
0.8 × VDDI
–
–
V
VOL
DC output logic Low
–
–
0.2 x VDDI
V
IOH at VOH
Output minimum source DC current
7.6
–
–
mA
IOL at VOL
Output minimum sink current
–7.6
–
–
mA
0.2
–
–
V
SSTL15 Differential Voltage Specification
VID
DC input differential voltage
Note: *To meet JEDEC Electrical Compliance, use DDR3 Full Drive Transmitter.
Table 69 • DDR3/SSTL15 AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
0.3
–
–
V
0.5 × VDDI
– 0.150
–
0.5 × VDDI +
0.150
V
–
–
600
Mbps
SSTL15 AC Differential Voltage Specification
VDIFF
AC input differential voltage
Vx
AC differential cross point voltage
SSTL15 Maximum AC Switching Speed (for DDRIO I/O Banks Only)
Dmax
Maximum data rate
AC
loading:
per
JEDEC specifications
SSTL15 AC Calibrated Impedance Option
Rref
Supported output driver Reference resistor
calibrated impedance
= 240 
–
34, 40
–

RTT
Effective impedance value Reference resistor
(ODT)
= 240 
–
20, 30, 40,
60, 120
–

SSTL15 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.75
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Rtt_test
Reference resistance for data test path for SSTL15
Class I (tDP)
–
50
–

Rtt_test
Reference resistance for data test path for SSTL15
Class II (tDP)
–
25
–

Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Revision 4
51
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.7.5.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 70 • DDR3/STTL15 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
Speed Grade
–1
ODT (On Die Termination)
tPY
Units
DDR3/SSTL15 (for DDRIO I/O Bank) – Calibration Mode Only
Pseudo-Differential
None
1.672
ns
True-Differential
None
1.694
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 71 • DDR3/SSTL15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.425 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
DDR3 Reduced Drive/SSTL15 Class I (for DDRIO I/O Bank)
Single Ended
2.832
2.766
2.767
2.658
2.659
ns
Differential
2.848
3.401
3.393
3.173
3.166
ns
DDR3 Full Drive/SSTL15 Class II (for DDRIO I/O Bank)
Single Ended
2.832
2.76
2.759
2.655
2.655
ns
Differential
2.845
3.397
3.387
3.179
3.171
ns
8.7.6 Low Power Double Data Rate (LPDDR)
LPDDR reduced and full drive low power double data rate standards are supported in IGLOO2 FPGA and
SmartFusion2 SoC FPGA I/Os. This standard requires a differential amplifier input buffer and a push-pull output buffer.
This I/O standard is supported in DDRIO I/O Bank only.
8.7.6.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 72 • LPDDR AC/DC Specifications (for DDRIO IO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
Notes
Recommended DC Operating Conditions
VDDI
Supply voltage
1.71
1.8
1.89
V
–
VTT
Termination voltage
0.838
0.900
0.964
V
–
VREF
Input reference voltage
0.838
0.900
0.964
V
–
LPDDR DC Input Voltage Specification
VIH (DC)
DC input logic High
0.7 × VDDI
–
1.89
V
–
VIL (DC)
DC input logic Low
–0.3
–
0.3 × VDDI
V
–
IIH (DC)
Input current High
–
–
10
µA
–
IIL (DC)
Input current Low
–
–
10
µA
–
LPDDR DC Output Voltage Specification
Revision 4
52
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 72 • LPDDR AC/DC Specifications (for DDRIO IO Bank Only)
LPDDR Reduced Drive
VOH
DC output logic High
0.9 × VDDI
–
–
V
–
VOL
DC output logic Low
–
–
0.1 × VDDI
V
–
IOH at VOH
Output minimum source DC current
0.1
–
–
mA
–
IOL at VOL
Output minimum sink current
–0.1
–
–
mA
–
*
LPDDR Full Drive
VOH
DC output logic High
0.9 × VDDI
–
–
V
–
VOL
DC output logic Low
–
–
0.1 × VDDI
V
–
IOH at VOH
Output minimum source DC current
0.1
–
–
mA
–
IOL at VOL
Output minimum sink current
–0.1
–
–
mA
–
0.4 × VDDI
–
–
V
–
LPDDR DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Note: *To meet JEDEC Electrical Compliance, use LPDDR Full Drive Transmitter.
Table 73 • LPDDR Maximum AC Switching Speeds (for DDRIO I/O Bank Only)
Symbols
Dmax
Parameters
Maximum data rate
Conditions
AC
loading:
specifications
per
Min
Typ
Max
Units
–
–
360
Mbps
JEDEC
Table 74 • LPDDR AC Specifications (for DDRIO IO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
VDIFF (AC) AC Input differential voltage
–
0.6 × VDDI
–
–
V
Vx (AC)
–
0.4 × VDDI
–
0.6 × VDDI
V
LPDDR AC Differential Voltage Specification
AC Differential Cross Point Voltage
LPDDR Impedance Specifications
Rref
Supported Output Driver Calibrated
Impedance
Reference Resistor
= 150 
–
20,42
–

RTT
Effective impedance Value - ODT
Reference Resistor
= 150 
–
50, 75,
150
–

LPDDR AC Test Parameters Specifications
Vtrip
Measuring/Trip Point for Data Path
–
–
0.9
–
V
Rent
Resistance for Enable Path (tZH, tZL,
tHZ, tLZ)
–
–
2k
–

Cent
Capacitive Loading for Enable Path
(tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Rtt_test
Reference resistance for Data Test
Path for LPDDR (tDP)
–
–
50
–

Cload
Capacitive Loading for Data Path
(tDP)
–
–
5
–
pF
Revision 4
53
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.7.6.2 AC Switching Characteristics
Table 75 • LPDDR AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.71 V
Speed Grade
–1
ODT (On Die Termination)
tPY
Units
LPDDR (for DDRIO I/O Bank with Fixed Codes)
Pseudo-Differential
None
1.633
ns
True-Differential
None
1.65
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 76 • LPDDR AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ=125°C, VDD=1.14 V, VDDI= 1.71 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.645
2.431
2.434
2.396
2.398
ns
Differential
2.652
3.044
3.038
2.46
2.455
ns
Single Ended
2.532
2.401
2.398
2.368
2.365
ns
Differential
2.546
2.509
2.503
2.852
2.845
ns
LPDDR Reduced Drive (for DDRIO I/O Bank)
LPDDR Full Drive (for DDRIO I/O Bank)
8.7.6.3 Minimum and Maximum AC/DC Input and Output Levels Specification using LPDDRLVCMOS 1.8 V Mode
Table 77 • LPDDR-LVCMOS 1.8 V Mode, Minimum and Maximum DC Input and Output Levels
(Applicable to DDRIO I/O Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
1.710
1.8
1.89
V
LPDDR-LVCMOS 1.8 V Recommended DC Operating Conditions
VDDI
Supply Voltage
–
LPDDR-LVCMOS 1.8 V Mode DC Input Voltage Specification
VIH(DC)
DC input Logic HIGH for (MSIOD
and DDRIO I/O Banks)
–
0.65 x VDDI
–
1.89
V
VIH(DC)
DC input Logic HIGH (for MSIO
I/O Bank)
–
0.65 x VDDI
–
3.45
V
VIL(DC)
DC input Logic LOW
–
-0.3
–
0.35 x VDDI
V
IIH(DC)
Input current HIGH
–
–
–
10
uA
IIL(DC)
Input current LOW
–
–
–
10
uA
LPDDR-LVCMOS 1.8 V Mode DC Output Voltage Specification
VOH
DC output Logic HIGH
–
VDDI - 0.45
–
–
V
VOL
DC output Logic LOW
–
–
–
0.45
V
Revision 4
54
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 78 • LPDDR-LVCMOS 1.8 V Maximum AC Switching Speeds (Applicable to DDRIO I/O Bank Only)
Symbols
Dmax
Parameters
Maximum Data Rate
(for DDRIO I/O Bank)
Conditions
Min
Typ
Max
Units
AC Loading: 17pF Load, 8mA
Drive and Above/All Slew
–
–
360
Mbps
Table 79 • LPDDR-LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications (Applicable to
DDRIO I/O Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
75, 60, 50,
33, 25, 20
–

LPDDR - LVCMOS 1.8 V Calibrated Impedance Option
Rodt_cal
Supported
Output
Driver
Calibrated Impedance (for DDRIO
I/O Bank)
–
LPDDR- LVCMOS 1.8 V AC Test Parameters Specifications
Vtrip
Measuring/Trip Point for Data Path
–
–
0.9
–
V
Rent
Resistance for Enable Path (tZH,
tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive Loading for Enable
Path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Cload
Capacitive Loading for Data Path
(tDP)
–
–
5
–
pF
Table 80 • LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification (Applicable to DDRIO I/O
Bank Only)
Output Drive
Selection
VOH (V)
Min
VOL (V)
Max
IOH (at VOH)
mA
IOL (at VOL)
mA
Notes
2 mA
VDDI – 0.45
0.45
2
2
–
4 mA
VDDI – 0.45
0.45
4
4
–
6 mA
VDDI – 0.45
0.45
6
6
–
8 mA
VDDI – 0.45
0.45
8
8
–
10 mA
VDDI – 0.45
0.45
10
10
–
12 mA
VDDI – 0.45
0.45
12
12
–
16 mA
VDDI – 0.45
0.45
16
16
*
Note: * 16mA Drive Strengths, All Slews, meet LPDDR JEDEC electrical compliance
8.7.6.4 AC Switching Characteristics
Table 81 • LPPDR - LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
ODT (On Die
Termination)
LPDDR-LVCMOS 1.8 mode
(for DDRIO I/O Bank with Fixed Codes)
None
Revision 4
Speed Grade
–1
tPY
tPYS
Units
2.071
2.213
ns
55
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
AC Switching Characteristics for Transmitter (Output and Tristate Buffers
Table 82 • LPDDR - LVCMOS 1.8 V AC Switching Characteristics for Transmitter DDRIO I/O Bank (Output and
Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 1.71 V
Output Drive
Selection
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
slow
4.681
4.017
4.69
5.388
4.852
ns
medium
4.211
3.599
4.219
5.058
4.488
ns
medium_fast
3.978
3.392
3.986
4.874
4.327
ns
fast
3.953
3.373
3.961
4.858
4.316
ns
slow
4.355
3.657
4.346
5.967
5.399
ns
medium
3.886
3.246
3.879
5.628
5.01
ns
medium_fast
3.656
3.05
3.647
5.461
4.845
ns
fast
3.635
3.033
3.626
5.447
4.838
ns
slow
4.105
3.422
4.092
6.221
5.599
ns
medium
3.68
3.05
3.668
5.9
5.257
ns
medium_fast
3.477
2.867
3.463
5.739
5.118
ns
fast
3.451
2.849
3.437
5.72
5.104
ns
slow
4.015
3.32
3.998
6.458
5.808
ns
medium
3.59
2.947
3.574
6.129
5.449
ns
medium_fast
3.383
2.761
3.366
5.963
5.304
ns
fast
3.357
2.746
3.34
5.954
5.289
ns
slow
3.888
3.18
3.864
6.739
6.045
ns
medium
3.485
2.822
3.467
6.422
5.7
ns
medium_fast
3.281
2.642
3.26
6.277
5.553
ns
fast
3.258
2.627
3.238
6.27
5.546
ns
slow
3.795
3.096
3.773
6.773
6.067
ns
medium
3.408
2.764
3.389
6.47
5.743
ns
medium_fast
3.215
2.599
3.194
6.346
5.61
ns
fast
3.196
2.584
3.175
6.335
5.604
ns
slow
3.744
3.035
3.719
6.944
6.207
ns
medium
3.358
2.712
3.339
6.657
5.868
ns
medium_fast
3.175
2.546
3.153
6.547
5.751
ns
fast
3.156
2.531
3.133
6.541
5.747
ns
Revision 4
56
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8. Differential I/O Standards
Configuration of the I/O modules as a differential pair is handled by Microsemi SoC Products Group Libero® Systemon-Chip (SoC) software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be
used in conjunction with the embedded Input register (InReg), Output register (OutReg), Enable register (EnReg), and
Double Data Rate registers (DDR).
8.8.1 LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard.
8.8.1.1 Minimum and Maximum Input and Output Levels
Table 83 • LVDS DC Voltage Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
2.5 V range
2.375
2.5
2.625
V
VDDI
Supply voltage
3.3 V range
3.15
3.3
3.45
V
LVDS DC Input Voltage Specification
VI
DC Input voltage
2.5 V range
0
–
2.925
V
VI
DC input voltage
3.3 V range
0
–
3.45
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
LVDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
250
350
450
mV
LVDS Differential Voltage Specification
VOD
Differential output voltage swing
VOCM
Output common mode voltage
1.125
1.25
1.375
V
VICM
Input common mode voltage
0.05
1.25
2.35
V
VID
Input differential voltage
100
350
600
mV
Table 84 • LVDS AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
480
Mbps
–
–
480
Mbps
–
100
–

LVDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading:
differential load
12 pF / 100 
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading:
differential load
10 pF / 100 
LVDS Impedance Specification
Rt
Termination resistance
–
LVDS AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
Cross point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Revision 4
57
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8.1.2 LVDS25 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 85 • LVDS25 Receiver Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
On-Die Termination (ODT)
tPY
Units
None
3.061
ns
100
3.057
ns
None
2.792
ns
100
2.787
ns
LVDS (for MSIO I/O Bank)
LVDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 86 • LVDS25 Transmitter Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
2.299
2.602
2.589
2.305
2.32
ns
No pre-emphasis
1.656
1.845
1.838
1.992
1.969
ns
Min pre-emphasis
1.583
1.868
1.866
2.018
1.998
ns
Med pre-emphasis
1.559
1.893
1.886
2.045
2.021
ns
LVDS (for MSIO I/O Bank)
LVDS (for MSIOD I/O Bank)
8.8.1.3 LVDS33 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 87 • LVDS33 Receiver Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
On Die Termination (ODT)
tPY
Units
None
2.763
ns
100
2.76
ns
LVDS33 (for MSIO I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 88 • LVDS33 Transmitter Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
LVDS33 (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.069
2.112
2.106
2.078
2.09
ns
Revision 4
58
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8.2 B-LVDS
Bus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications.
Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers.
8.8.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 89 • B-LVDS DC Voltage Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
Bus-LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
Bus-LVDS DC Input Voltage Specification
VI
DC input voltage
0
–
2.925
V
IIH (DC)
Input current High
–
–
10
µA
IIL (DC)
Input current Low
–
–
10
µA
Bus-LVDS DC Output Voltage Specification (for MSIO I/O Bank only)
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
Bus-LVDS Differential Voltage Specification
VOD
Differential output voltage swing (for MSIO I/O Bank only)
65
–
460
mV
VOCM
Output common mode voltage (for MSIO I/O Bank only)
1.1
–
1.5
V
VICM
Input common mode voltage
0.05
–
2.4
V
VID
Input differential voltage
0.1
–
VDDI
V
Min
Typ
Max
Units
–
–
450
Mbps
–
27
–

Table 90 • B-LVDS AC Specifications
Symbols
Parameters
Conditions
Bus-LVDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC
loading:
differential load
2 pF / 100 
Bus-LVDS Impedance Specifications
Rt
Termination resistance
Bus-LVDS AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Revision 4
59
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8.2.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 91 • B-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
On-Die Termination (ODT)
tPY
Units
None
3.011
ns
100
3.006
ns
None
2.722
ns
100
2.725
ns
Bus-LVDS (for MSIO I/O Bank)
Bus-LVDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 92 • B-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
Bus-LVDS (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.78
2.632
2.617
2.448
2.436
ns
8.8.3 M-LVDS
M-LVDS specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop
and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers.
8.8.3.1 Minimum and Maximum Input and Output Levels
Table 93 • M-LVDS DC Voltage Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
M-LVDS Recommended DC Operating Conditions
VDDI
Notes
Supply voltage
2.375
2.5
2.625
V
*
–
M-LVDS DC Input Voltage Specification
VI
DC input voltage
0
–
2.925
V
–
IIH (DC)
Input current High
–
–
10
µA
–
IIL (DC)
Input current Low
–
–
10
µA
–
–
M-LVDS DC Output Voltage Specification (for MSIO I/O Bank Only)
VOH
DC output logic High
1.25
1.425
1.6
V
–
VOL
DC output logic Low
0.9
1.075
1.25
V
–
–
M-LVDS Differential Voltage Specification
VOD
Differential output voltage Swing (for MSIO I/O Bank only)
300
–
650
mV
–
VOCM
Output common mode voltage (for MSIO I/O Bank only)
0.3
–
2.1
V
–
VICM
Input common mode voltage
0.3
–
1.2
V
–
Revision 4
60
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 93 • M-LVDS DC Voltage Specification (continued)
Symbols
VID
Parameters
Conditions
Min
Typ
Max
Units
Notes
50
–
2400
mV
–
Input differential voltage
Note: *Only M-LVDS TYPE I is supported
Table 94 • M-LVDS AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
450
Mbps
–
50
–

M-LVDS Maximum AC Switching Speeds
Dmax
Maximum data rate
(for MSIO I/O Bank)
2 pF / 100 
AC
loading:
differential load
M-LVDS Impedance Specification
Rt
Termination resistance
–
M-LVDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
8.8.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 95 • M-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
On-Die Termination (ODT)
tPY
Units
None
3.011
ns
100
3.006
ns
None
2.722
ns
100
2.725
ns
M-LVDS (for MSIO I/O Bank)
M-LVDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 96 • M-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
M-LVDS (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.78
2.632
2.616
2.447
2.436
ns
Revision 4
61
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8.4 Mini-LVDS
Mini-LVDS is an unidirectional interface from the timing controller to the column drivers and is designed to the Texas
Instruments Standard SLDA007A.
8.8.4.1 Mini-LVDS Minimum and Maximum Input and Output Levels
Table 97 • Mini-LVDS DC Voltage Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.925
V
Recommended DC Operating Conditions
VDDI
Supply voltage
Mini-LVDS DC Input Voltage Specification
VI
DC Input voltage
Mini-LVDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
300
–
600
mV
1
–
1.4
V
Mini-LVDS Differential Voltage Specification
VOD
Differential output voltage swing
VOCM
Output common mode voltage
VICM
Input common mode voltage
0.3
–
1.2
V
VID
Input differential voltage
100
–
600
mV
Min
Typ
Max
Units
–
–
460
Mbps
–
–
480
Mbps
–
100
–

Table 98 • Mini-LVDS AC Specifications
Symbols
Parameters
Conditions
Mini-LVDS Maximum AC Switching Speed
AC loading:
differential load
2 pF / 100 
Dmax
Maximum data rate (MSIO I/O Bank)
Dmax
Maximum data rate (MSIOD I/O AC loading: 10 pF / 100 
Bank)
differential load
Mini-LVDS Impedance Specification
Rt
Termination resistance
Mini-LVDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Revision 4
62
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8.4.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 99 • Mini-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
On-Die Termination (ODT)
tPY
Units
None
3.112
ns
100
2.995
ns
None
2.612
ns
100
2.612
ns
Mini-LVDS (for MSIO I/O Bank)
Mini-LVDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 100 • Mini-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military Conditions: TJ = 125°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
2.3
2.602
2.59
2.306
2.32
ns
No pre-emphasis
1.652
1.84
1.833
1.988
1.965
ns
Min pre-emphasis
1.652
1.84
1.833
1.988
1.965
ns
Med pre-emphasis
1.577
1.868
1.86
2.02
1.994
ns
Max pre-emphasis
1.555
1.894
1.883
2.048
2.019
ns
Mini-LVDS (for MSIO I/O Bank)
Mini-LVDS (for MSIOD I/O Bank)
Revision 4
63
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8.5 RSDS
Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using differential signaling.
RSDS has a similar implementation to LVDS devices and is only intended for point-to-point applications.
8.8.5.1 Minimum and Maximum Input and Output Levels
Table 101 • RSDS DC Voltage Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.925
V
Recommended DC Operating Conditions
VDDI
Supply voltage
RSDS DC Input Voltage Specification
VI
DC input voltage
RSDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
RSDS Differential Voltage Specification
VOD
Differential output voltage swing
100
–
600
mV
VOCM
Output common mode voltage
0.5
–
1.5
V
VICM
Input common mode voltage
0.3
–
1.5
V
VID
Input differential voltage
100
–
600
mV
Min
Typ
Max
Units
–
–
460
Mbps
–
–
480
Mbps
–
100
–

Table 102 • RSDS AC Specifications
Symbols
Parameters
Conditions
RSDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC
loading:
differential load
2 pF / 100 
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC
loading:
differential load
10 pF / 100 
RSDS Impedance Specification
Rt
Termination resistance
RSDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
Cross
point
–
V
Rent
Resistance for enable path (tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)
–
5
–
pF
Revision 4
64
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.8.5.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 103 • RSDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
On-Die Termination (ODT)
tPY
Units
None
3.112
ns
100
3.108
ns
None
2.832
ns
100
2.821
ns
RSDS (for MSIO I/O Bank)
RSDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 104 • RSDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 2.375 V
Units
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
2.256
2.484
2.472
2.111
2.096
ns
No pre-emphasis
1.661
1.648
1.645
1.675
1.665
ns
Min pre-emphasis
1.651
1.84
1.833
1.988
1.964
ns
Med pre-emphasis
1.577
1.868
1.859
2.019
1.993
ns
Max pre-emphasis
1.555
1.894
1.883
2.047
2.018
ns
RSDS (for MSIO I/O Bank)
RSDS (for MSIOD I/O Bank)
8.8.6 LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit
be carried through two signal lines. Similar to LVDS, two pins are needed. It also requires external resistor termination.
IGLOO2 and SmartFusion2 SoC FPGAs support only LVPECL receivers and do not support LVPECL transmitters.
8.8.6.1 Minimum and Maximum Input and Output Levels
Table 105 • LVPECL DC Voltage Specification (Applicable to MSIO I/O Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
3.15
3.3
3.45
V
0
–
3.45
V
2.8
V
1,000
mV
Recommended DC Operating Conditions
VDDI
Supply voltage
LVPECL DC Input Voltage Specification
VI
DC input voltage
LVPECL Differential Voltage Specification
VICM
Input common mode voltage
0.3
VIDIFF
Input differential voltage
100
Revision 4
300
65
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 106 • LVPECL Maximum AC Switching Speeds (Applicable to MSIO I/O Banks Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
810
Mbps
LVPECL AC Specifications
Fmax
Maximum data rate (for MSIO I/O Bank)
8.8.6.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 107 • LVPECL Receiver Characteristics
Worst-case Military conditions: TJ = 125°C, VDD = 1.14 V, VDDI = 3.15 V
tPY
On-Die Termination (ODT)
Speed Grade
–1
Units
None
2.71
ns
100
2.71
ns
LVPECL (for MSIO I/O Bank)
8.9 I/O Register Specifications
8.9.1 Input Register
D
EN
Input I/O Buffer
ALn
F
D
B
EN
C
D
Q
SLn
SLE
SD
SD
LAT
CLK
Q
ALn
ADn
ADn
SLn
G
A
LAT
E
CLK
Figure 5 • Timing Model for Input Register
Revision 4
66
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
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Figure 6 • I/O Register Input Timing Diagram
Table 108 • Input Data Register Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Measuring
Nodes
(from, to)*
Speed
Grade
–1
Units
tIBYP
Bypass Delay of the Input Register
F,G
0.364
ns
tICLKQ
Clock-to-Q of the Input Register
E,G
0.165
ns
tISUD
Data Setup Time for the Input Register
A,E
0.369
ns
tIHD
Data Hold Time for the Input Register
A,E
0
ns
tISUE
Enable Setup Time for the Input Register
B,E
0.475
ns
tIHE
Enable Hold Time for the Input Register
B,E
0
ns
tISUSL
Synchronous Load Setup Time for the Input Register
D,E
0.475
ns
tIHSL
Synchronous Load Hold Time for the Input Register
D,E
0
ns
Asynchronous Clear-to-Q of the Input Register (ADn=1)
C,G
0.648
ns
Asynchronous Preset-to-Q of the Input Register (ADn=0)
C,G
0.606
ns
tIALn2Q
Revision 4
67
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 108 • Input Data Register Propagation Delays (continued)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Description
Measuring
Nodes
(from, to)*
Speed
Grade
–1
Units
Asynchronous Load Removal Time for the Input Register
C,E
0
ns
Parameter
tIREMALn
tIRECALn
Asynchronous Load Recovery Time for the Input Register
C,E
0.076
ns
tIWALn
Asynchronous Load Minimum Pulse Width for the Input Register
C,C
0.313
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Register
E,E
0.078
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Register
E,E
0.164
ns
8.9.2 Output/Enable Register
A
D
EN
ALn
F
D
B
EN
C
ADn
D
SLn
LAT
LAT
D2
SLE
SD
SD
CLK
Q
ALn
ADn
SLn
G
E
J
CLK
H
I
D
Q
EN
ALn
ADn
SLn
Output I/O Buffer
with Enable Control
SLE
SD
LAT
CLK
Output/Enable Registers
Figure 7 • Timing Model for Output/Enable Register
Revision 4
68
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
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Figure 8 • I/O Register Output Timing Diagram
Table 109 • Output/Enable Data Register Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Measuring
Nodes
(from, to)*
Speed
Grade
–1
Units
tOBYP
Bypass Delay of the Output/Enable Register
F,G or H,I
0.364
ns
tOCLKQ
Clock-to-Q of the Output/Enable Register
E,G or E,I
0.272
ns
tOSUD
Data Setup Time for the Output/Enable Register
A,E or J,E
0.196
ns
tOHD
Data Hold Time for the Output/Enable Register
A,E or J,E
0
ns
tOSUE
Enable Setup Time for the Output/Enable Register
B,E
0.433
ns
tOHE
Enable Hold Time for the Output/Enable Register
B,E
0
ns
tOSUSL
Synchronous Load Setup Time for the Output/Enable Register
D,E
0.203
ns
tOHSL
Synchronous Load Hold Time for the Output/Enable Register
D,E
0
ns
C,G or C,I
0.523
ns
Asynchronous Preset-to-Q of the Output/Enable Register
(ADn=0)
C,G or C,I
0.545
ns
Asynchronous Load Removal Time for the Output/Enable
Register
C,E
0
ns
tOALn2Q
tOREMALn
Asynchronous
(ADn=1)
Clear-to-Q
of
the
Output/Enable
Revision 4
Register
69
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 109 • Output/Enable Data Register Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Measuring
Nodes
(from, to)*
Speed
Grade
–1
Units
Parameter
Description
tORECALn
Asynchronous Load Recovery Time for the Output/Enable
Register
C,E
0.035
ns
tOWALn
Asynchronous Load Minimum Pulse Width for the Output/Enable
Register
C,C
0.266
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output/Enable Register
E,E
0.065
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output/Enable Register
E,E
0.139
ns
8.10 DDR Module Specification
8.10.1 Input DDR Module
D
EN
ALn
A
D
E
EN
F
ADn
G
SLn
SLE
SD
SD
LAT
LAT
CLK
QR
ALn
ADn
SLn
C
Q
B
CLK
D
ALn
ADn
Q
D
D
Q
EN
Latch
QF
ALn
ADn
SLn
CLK
SLE
SD
LAT
CLK
DDR_IN
Figure 9 • Input DDR Module
Revision 4
70
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.10.2 Input DDR Timing Diagram
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Figure 10 • Input DDR Timing Diagram
Revision 4
71
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.10.3 Timing Characteristics
Table 110 • Input DDR Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD=1.14 V
Parameter
Description
Measuring Nodes
(from, to)
Speed Grade
–1
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
B,C
0.165
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
B,D
0.172
ns
tDDRISUD
Data Setup for Input DDR
A,B
0.372
ns
tDDRIHD
Data Hold for Input DDR
A,B
0
ns
tDDRISUE
Enable Setup for Input DDR
E,B
0.475
ns
tDDRIHE
Enable Hold for Input DDR
E,B
0
ns
tDDRISUSLn
Synchronous Load Setup for Input DDR
G,B
0.475
ns
tDDRIHSLn
Synchronous Load Hold for Input DDR
G,B
0
ns
tDDRIAL2Q1
Asynchronous Load-to-Out QR for Input DDR
F,C
0.606
ns
tDDRIAL2Q2
Asynchronous Load-to-Out QF for Input DDR
F,D
0.558
ns
tDDRIREMAL
Asynchronous Load Removal time for Input
DDR
F,B
0
ns
tDDRIRECAL
Asynchronous Load Recovery time for Input
DDR
F,B
0.076
ns
tDDRIWAL
Asynchronous Load Minimum Pulse Width for
Input DDR
F,F
0.313
ns
tDDRICKMPWH
Clock Minimum Pulse Width High for Input
DDR
B,B
0.078
ns
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR
B,B
0.164
ns
Revision 4
72
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.10.4 Output DDR Module
A
DR
EN
ALn
D
B
C
ADn
D
SLn
SD
SD
LAT
LAT
CLK
DF
QR
ALn
ADn
SLn
Q
EN
E
SLE
1
G
Q
CLK
F
D
Q
EN
QF
ALn
ADn
SLn
SLE
SD
0
LAT
CLK
DDR_ OUT
Figure 11 • Output DDR Module
Revision 4
73
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
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Figure 12 • Output DDR Timing Diagram
Revision 4
74
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
8.10.5 Timing Characteristics
Table 111 • Output DDR Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Measuring Nodes
(from, to)
Speed Grade
–1
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
E,G
0.272
ns
tDDROSUDF
DF Data Setup for Output DDR
F,E
0.148
ns
tDDROSUDR
DR Data Setup for Output DDR
A,E
0.196
ns
tDDROHDF
DF Data Hold for Output DDR
F,E
0
ns
tDDROHDR
DR Data Hold for Output DDR
A,E
0
ns
tDDROSUE
Enable Setup for Output DDR
B,E
0.433
ns
tDDROHE
Enable Hold for Output DDR
B,E
0
ns
tDDROSUSLn
Synchronous Load Setup for Output DDR
D,E
0.203
ns
tDDROHSLn
Synchronous Load Hold for Output DDR
D,E
0
ns
tDDROAL2Q
Asynchronous Load-to-Out for Output DDR
C,G
0.545
ns
tDDROREMAL
Asynchronous Load Removal time for Output
DDR
C,E
0
ns
tDDRORECAL
Asynchronous Load Recovery time for Output
DDR
C,E
0.035
ns
tDDROWAL
Asynchronous Load Minimum Pulse Width for
Output DDR
C,C
0.266
ns
tDDROCKMPWH
Clock Minimum Pulse Width High for the
Output DDR
E,E
0.065
ns
tDDROCKMPWL
Clock Minimum Pulse Width Low for the Output
DDR
E,E
0.139
ns
Revision 4
75
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
9. Logic Element Specifications
9.1 4-input LUT (LUT-4)
The IGLOO2 and SmartFusion2 SoC FPGAs offer a fully permutable 4-input LUT. In this section, timing characteristics
are presented for a sample of the library. For more details, refer to the SmartFusion2 and IGLOO2 Macro Library
Guide.
tPD
A
PAD
B
PAD
AND4 OR
Any
Combinational
Logic
C
PAD
PAD
D/S (where
applicable)
PAD
VDD
A, B, C, D, S
Y
50%
tPD = Max(tPD(RR), tPD(RF), tPD(FF), tPD(FR))
50%
where edges are applicable for the particular
combinatorial cell
GND
VDD
50%
50%
OUT
tPD
tPD
(RR)
(FF)
GND
VDD
tPD
OUT
50%
tPD
(RF)
(FR)
50%
GND
Figure 13 • LUT-4
Timing Characteristics
Table 112 • Combinatorial Cell Propagation Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Combinatorial Cell
Equation
Parameter
Speed
Grade
–1
Units
INV
Y = !A
tPD
0.106
ns
AND2
Y=A·B
tPD
0.17
ns
NAND2
Y = !(A · B)
tPD
0.157
ns
OR2
Y=A+B
tPD
0.17
ns
NOR2
Y = !(A + B)
tPD
0.157
ns
XOR2
Y=AB
tPD
0.17
ns
XOR3
Y=ABC
tPD
0.236
ns
AND3
Y=A·B·C
tPD
0.217
ns
AND4
Y=A·B·C·D
tPD
0.384
ns
Revision 4
76
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
9.2 Sequential Module
IGLOO2 and SmartFusion2 SoC FPGAs offer a separate flip-flop which can be used independently from the LUT. The
flip-flop can be configured as a register or a latch and has a data input and optional enable, synchronous load (clear or
preset), and asynchronous load (clear or preset).
D
Q
EN
ALn
ADn
SLn
SLE
SD
LAT
CLK
Figure 14 • Sequential Module
Figure 15 shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous clear) for a flip-flop
(LAT = 0).
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Figure 15 • Sequential Module Timing Diagram
Revision 4
77
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
9.2.1 Timing Characteristics
Table 113 • Register Delays
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Speed Grade
–1
Units
tCLKQ
Clock-to-Q of the Core Register
0.112
ns
tSUD
Data Setup Time for the Core Register
0.262
ns
tHD
Data Hold Time for the Core Register
0
ns
tSUE
Enable Setup Time for the Core Register
0.346
ns
tHE
Enable Hold Time for the Core Register
0
ns
tSUSL
Synchronous Load Setup Time for the Core Register
0.346
ns
tHSL
Synchronous Load Hold Time for the Core Register
0
ns
Asynchronous Clear-to-Q of the Core Register (ADn=1)
0.49
ns
Asynchronous Preset-to-Q of the Core Register (ADn=0)
0.466
ns
tREMALn
Asynchronous Load Removal Time for the Core Register
0
ns
tRECALn
Asynchronous Load Recovery Time for the Core Register
0.364
ns
tWALn
Asynchronous Load Minimum Pulse Width for the Core Register
0.266
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.065
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.139
ns
tALn2Q
10. Global Resource Characteristics
The IGLOO2 and SmartFusion2 SoC FPGA devices offer a powerful, low skew global routing network which provides
an effective clock distribution throughout the FPGA fabric. Refer to the UG0445: IGLOO2 FPGA and SmartFusion2
SoC FPGA Fabric User Guide for the positions of various global routing resources.
.
Table 114 • M2S150T Device Global Resource
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.788
0.868
ns
tRCKH
Input High Delay for Global Clock
1.46
1.594
ns
tRCKSW
Maximum Skew for Global Clock
–
0.134
ns
Table 115 • M2S090T Device Global Resource
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Revision 4
Min
Max
Units
0.793
0.847
ns
78
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 115 • M2S090T Device Global Resource (continued)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKH
Input High Delay for Global Clock
1.412
1.498
ns
tRCKSW
Maximum Skew for Global Clock
–
0.086
ns
Table 116 • M2S050T Device Global Resource
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.793
0.861
ns
tRCKH
Input High Delay for Global Clock
1.436
1.55
ns
tRCKSW
Maximum Skew for Global Clock
–
0.114
ns
Table 117 • M2S025T Device Global Resource
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.713
0.762
ns
tRCKH
Input High Delay for Global Clock
1.306
1.391
ns
tRCKSW
Maximum Skew for Global Clock
–
0.085
ns
Table 118 • M2S010T Device Global Resource
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.598
0.639
ns
tRCKH
Input High Delay for Global Clock
1.116
1.192
ns
tRCKSW
Maximum Skew for Global Clock
–
0.076
ns
Revision 4
79
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
11. FPGA Fabric SRAM
Refer to the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for more information.
11.1 FPGA Fabric Large SRAM (LSRAM)
Table 119 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tcy
Clock Period
tclkmpwh
Clock Minimum Pulse Width High
1.5
–
ns
tclkmpwl
Clock Minimum pulse Width Low
1.5
–
ns
tplcy
Pipelined Clock Period
3.333
–
ns
tplclkmpwh
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tplclkmpwl
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.346
ns
Read Access Time without Pipeline Register
–
2.346
ns
Access Time with Feed-Through Write Timing
–
1.578
ns
tclk2q
taddrsu
Address Setup Time
0.455
–
ns
taddrhd
Address Hold Time
0.282
–
ns
tdsu
Data Setup Time
0.352
–
ns
tdhd
Data Hold Time
0.11
–
ns
tblksu
Block Select Setup Time
0.214
–
ns
tblkhd
Block Select Hold Time
0.223
–
ns
tblk2q
Block Select to Out Disable Time (when Pipe-Lined Registered is
Disabled)
–
1.578
ns
tblkmpw
Block Select Minimum Pulse Width
0.218
–
ns
trdesu
Read Enable Setup Time
0.463
–
ns
trdehd
Read Enable Hold Time
0.173
–
ns
trdplesu
Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN)
0.256
–
ns
trdplehd
Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN)
0.106
–
ns
tr2q
Asynchronous Reset to Output Propagation Delay
–
1.561
ns
trstrem
Asynchronous Reset Removal Time
0.522
–
ns
trstrec
Asynchronous Reset Recovery Time
0.005
–
ns
trstmpw
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tplrstrem
Pipelined Register Asynchronous Reset Removal Time
-0.288
–
ns
tplrstrec
Pipelined Register Asynchronous Reset Recovery Time
0.338
–
ns
tplrstmpw
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
Revision 4
80
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 119 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tsrstsu
Synchronous Reset Setup Time
0.233
–
ns
tsrsthd
Synchronous Reset Hold Time
0.037
–
ns
twesu
Write Enable Setup Time
0.402
–
ns
twehd
Write Enable Hold Time
0.25
–
ns
Fmax
Maximum Frequency
–
300
MHz
Table 120 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2Kx9
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tcy
Clock Period
tclkmpwh
Clock Minimum Pulse Width High
1.5
–
ns
tclkmpwl
Clock Minimum pulse Width Low
1.5
–
ns
tplcy
Pipelined Clock Period
3.333
–
ns
tplclkmpwh
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tplclkmpwl
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.346
ns
Read Access Time without Pipeline Register
–
2.346
ns
Access Time with Feed-Through Write Timing
–
1.578
ns
tclk2q
taddrsu
Address Setup Time
0.49
–
ns
taddrhd
Address Hold Time
0.282
–
ns
tdsu
Data Setup Time
0.346
–
ns
tdhd
Data Hold Time
0.084
–
ns
tblksu
Block Select Setup Time
0.214
–
ns
tblkhd
Block Select Hold Time
0.223
–
ns
tblk2q
Block Select to Out Disable Time (when Pipe-Lined Registered
is Disabled)
–
1.578
ns
tblkmpw
Block Select Minimum Pulse Width
0.218
–
ns
trdesu
Read Enable Setup Time
0.5
–
ns
trdehd
Read Enable Hold Time
0.073
–
ns
trdplesu
Pipelined Read
B_DOUT_EN)
Enable
Setup
Time
(A_DOUT_EN,
0.256
–
ns
trdplehd
Pipelined Read
B_DOUT_EN)
Enable
Hold
Time
(A_DOUT_EN,
0.106
–
ns
tr2q
Asynchronous Reset to Output Propagation Delay
1.569
ns
Revision 4
–
81
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 120 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2Kx9
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
trstrem
Asynchronous Reset Removal Time
0.522
–
ns
trstrec
Asynchronous Reset Recovery Time
0.005
–
ns
trstmpw
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tplrstrem
Pipelined Register Asynchronous Reset Removal Time
-0.288
–
ns
tplrstrec
Pipelined Register Asynchronous Reset Recovery Time
0.338
–
ns
tplrstmpw
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tsrstsu
Synchronous Reset Setup Time
0.233
–
ns
tsrsthd
Synchronous Reset Hold Time
0.037
–
ns
twesu
Write Enable Setup Time
0.428
–
ns
twehd
Write Enable Hold Time
0.05
–
ns
Fmax
Maximum Frequency
–
300
MHz
Table 121 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4Kx4
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tcy
Clock Period
tclkmpwh
Clock Minimum Pulse Width High
1.5
–
ns
tclkmpwl
Clock Minimum pulse Width Low
1.5
–
ns
tplcy
Pipelined Clock Period
3.333
–
ns
tplclkmpwh
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tplclkmpwl
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.334
ns
Read Access Time without Pipeline Register
–
2.346
ns
Access Time with Feed-Through Write Timing
–
1.56
ns
tclk2q
taddrsu
Address Setup Time
0.56
–
ns
taddrhd
Address Hold Time
0.282
–
ns
tdsu
Data Setup Time
0.345
–
ns
tdhd
Data Hold Time
0.084
–
ns
tblksu
Block Select Setup Time
0.214
–
ns
tblkhd
Block Select Hold Time
0.223
–
ns
tblk2q
Block Select to Out Disable Time (when Pipe-Lined Registered
is Disabled)
–
1.56
ns
tblkmpw
Block Select Minimum Pulse Width
0.218
–
ns
Revision 4
82
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 121 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4Kx4
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
trdesu
Read Enable Setup Time
0.532
–
ns
trdehd
Read Enable Hold Time
0.073
–
ns
trdplesu
Pipelined Read
B_DOUT_EN)
Enable
Setup
Time
(A_DOUT_EN,
0.256
–
ns
trdplehd
Pipelined Read
B_DOUT_EN)
Enable
Hold
Time
(A_DOUT_EN,
0.106
–
ns
tr2q
Asynchronous Reset to Output Propagation Delay
–
1.562
ns
trstrem
Asynchronous Reset Removal Time
0.522
–
ns
trstrec
Asynchronous Reset Recovery Time
0.005
–
ns
trstmpw
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tplrstrem
Pipelined Register Asynchronous Reset Removal Time
-0.288
–
ns
tplrstrec
Pipelined Register Asynchronous Reset Recovery Time
0.338
–
ns
tplrstmpw
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tsrstsu
Synchronous Reset Setup Time
0.233
–
ns
tsrsthd
Synchronous Reset Hold Time
0.037
–
ns
twesu
Write Enable Setup Time
0.473
–
ns
twehd
Write Enable Hold Time
0.05
–
ns
Fmax
Maximum Frequency
–
300
MHz
Table 122 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8Kx2
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Speed Grade
–1
Description
Min
Max
Units
3.333
–
ns
tcy
Clock Period
tclkmpwh
Clock Minimum Pulse Width High
1.5
–
ns
tclkmpwl
Clock Minimum pulse Width Low
1.5
–
ns
tplcy
Pipelined Clock Period
3.333
–
ns
tplclkmpwh
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tplclkmpwl
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.332
ns
Read Access Time without Pipeline Register
–
2.346
ns
Access Time with Feed-Through Write Timing
–
1.56
ns
tclk2q
taddrsu
Address Setup Time
0.631
–
ns
taddrhd
Address Hold Time
0.282
–
ns
Revision 4
83
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 122 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8Kx2
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Parameter
Speed Grade
–1
Description
Min
Max
Units
tdsu
Data Setup Time
0.34
–
ns
tdhd
Data Hold Time
0.084
–
ns
tblksu
Block Select Setup Time
0.214
–
ns
tblkhd
Block Select Hold Time
0.223
–
ns
tblk2q
Block Select to Out Disable Time (when Pipe-Lined Registered
is Disabled)
–
1.56
ns
tblkmpw
Block Select Minimum Pulse Width
0.218
–
ns
trdesu
Read Enable Setup Time
0.546
–
ns
trdehd
Read Enable Hold Time
0.073
–
ns
trdplesu
Pipelined Read
B_DOUT_EN)
Enable
Setup
Time
(A_DOUT_EN,
0.256
–
ns
trdplehd
Pipelined Read
B_DOUT_EN)
Enable
Hold
Time
(A_DOUT_EN,
0.106
–
ns
tr2q
Asynchronous Reset to Output Propagation Delay
–
1.583
ns
trstrem
Asynchronous Reset Removal Time
0.522
–
ns
trstrec
Asynchronous Reset Recovery Time
0.005
–
ns
trstmpw
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tplrstrem
Pipelined Register Asynchronous Reset Removal Time
-0.288
–
ns
tplrstrec
Pipelined Register Asynchronous Reset Recovery Time
0.338
–
ns
tplrstmpw
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tsrstsu
Synchronous Reset Setup Time
0.233
–
ns
tsrsthd
Synchronous Reset Hold Time
0.037
–
ns
twesu
Write Enable Setup Time
0.504
–
ns
twehd
Write Enable Hold Time
0.05
–
ns
Fmax
Maximum Frequency
–
300
MHz
Table 123 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16Kx1
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tcy
Clock Period
tclkmpwh
Clock Minimum Pulse Width High
1.5
–
ns
tclkmpwl
Clock Minimum pulse Width Low
1.5
–
ns
tplcy
Pipelined Clock Period
3.333
–
ns
tplclkmpwh
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
Revision 4
84
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 123 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16Kx1
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
tplclkmpwl
tclk2q
Description
Min
Max
Units
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.332
ns
Read Access Time without Pipeline Register
–
2.342
ns
Access Time with Feed-Through Write Timing
–
1.559
ns
taddrsu
Address Setup Time
0.646
–
ns
taddrhd
Address Hold Time
0.282
–
ns
tdsu
Data Setup Time
0.332
–
ns
tdhd
Data Hold Time
0.084
–
ns
tblksu
Block Select Setup Time
0.214
–
ns
tblkhd
Block Select Hold Time
0.223
–
ns
tblk2q
Block Select to Out Disable Time (when Pipe-Lined Registered is
Disabled)
–
1.559
ns
tblkmpw
Block Select Minimum Pulse Width
0.218
–
ns
trdesu
Read Enable Setup Time
0.547
–
ns
trdehd
Read Enable Hold Time
0.073
–
ns
trdplesu
Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN)
0.256
–
ns
trdplehd
Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN)
0.106
–
ns
tr2q
Asynchronous Reset to Output Propagation Delay
1.603
ns
trstrem
Asynchronous Reset Removal Time
0.522
–
ns
trstrec
Asynchronous Reset Recovery Time
0.005
–
ns
trstmpw
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tplrstrem
Pipelined Register Asynchronous Reset Removal Time
-0.288
–
ns
tplrstrec
Pipelined Register Asynchronous Reset Recovery Time
0.338
–
ns
tplrstmpw
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tsrstsu
Synchronous Reset Setup Time
0.233
–
ns
tsrsthd
Synchronous Reset Hold Time
0.037
–
ns
twesu
Write Enable Setup Time
0.468
–
ns
twehd
Write Enable Hold Time
0.05
–
ns
Fmax
Maximum Frequency
–
300
MHz
Revision 4
85
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 124 • RAM1K18 – Two-Port Mode for Depth × Width Configuration 512x36
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tcy
Clock Period
tclkmpwh
Clock Minimum Pulse Width High
1.5
–
ns
tclkmpwl
Clock Minimum pulse Width Low
1.5
–
ns
tplcy
Pipelined Clock Period
3.333
–
ns
tplclkmpwh
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tplclkmpwl
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.346
ns
Read Access Time without Pipeline Register
–
2.322
ns
tclk2q
taddrsu
Address Setup Time
0.323
–
ns
taddrhd
Address Hold Time
0.282
–
ns
tdsu
Data Setup Time
0.348
–
ns
tdhd
Data Hold Time
0.114
–
ns
tblksu
Block Select Setup Time
0.214
–
ns
tblkhd
Block Select Hold Time
0.208
–
ns
tblk2q
Block Select to Out Disable Time (when Pipe-Lined Registered
is Disabled)
–
2.322
ns
tblkmpw
Block Select Minimum Pulse Width
0.218
–
ns
trdesu
Read Enable Setup Time
0.463
–
ns
trdehd
Read Enable Hold Time
0.173
–
ns
trdplesu
Pipelined Read
B_DOUT_EN)
Enable
Setup
Time
(A_DOUT_EN,
0.256
–
ns
trdplehd
Pipelined
Read
B_DOUT_EN)
Enable
Hold
Time
(A_DOUT_EN,
0.106
–
ns
tr2q
Asynchronous Reset to Output Propagation Delay
–
1.561
ns
trstrem
Asynchronous Reset Removal Time
0.522
–
ns
trstrec
Asynchronous Reset Recovery Time
0.005
–
ns
trstmpw
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tplrstrem
Pipelined Register Asynchronous Reset Removal Time
-0.288
–
ns
tplrstrec
Pipelined Register Asynchronous Reset Recovery Time
0.338
–
ns
tplrstmpw
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tsrstsu
Synchronous Reset Setup Time
0.233
–
ns
tsrsthd
Synchronous Reset Hold Time
0.037
–
ns
twesu
Write Enable Setup Time
0.402
–
ns
Revision 4
86
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 124 • RAM1K18 – Two-Port Mode for Depth × Width Configuration 512x36
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
twehd
Write Enable Hold Time
Fmax
Maximum Frequency
Min
Max
Units
0.25
–
ns
–
300
MHz
11.2 FPGA Fabric Micro SRAM (uSRAM)
Table 125 • uSRAM (RAM64x18) in 64x18 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tcy
Read Clock Period
tclkmpwh
Read Clock Minimum Pulse Width High
1.8
–
ns
tclkmpwl
Read Clock Minimum pulse Width Low
1.8
–
ns
tplcy
Read Pipe-line clock period
4
–
ns
tplclkmpwh
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tplclkmpwl
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.276
ns
Read Access Time without Pipeline Register
–
1.738
ns
Read Address Setup Time in Synchronous Mode
0.311
–
ns
Read Address Setup Time in Asynchronous Mode
1.916
–
ns
Read Address Hold Time in Synchronous Mode
0.094
–
ns
Read Address Hold Time in Asynchronous Mode
-0.803
–
ns
trdensu
Read Enable Setup Time
0.287
–
ns
trdenhd
Read Enable Hold Time
0.059
–
ns
tblksu
Read Block Select Setup Time
1.898
–
ns
tblkhd
Read Block Select Hold Time
-0.671
–
ns
tblk2q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.102
ns
-0.15
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
0.047
Clock)
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.524
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
0.244
Clock)
–
ns
0.869
ns
tclk2q
taddrsu
taddrhd
Read Asynchronous Reset Removal Time (Pipelined Clock)
trstrem
trstrec
tr2q
Read Asynchronous Reset to Output Propagation Delay (with
Pipe-Line Register Enabled)
Revision 4
–
87
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 125 • uSRAM (RAM64x18) in 64x18 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tsrstsu
Read Synchronous Reset Setup Time
0.279
–
ns
tsrsthd
Read Synchronous Reset Hold Time
0.062
–
ns
tccy
Write Clock Period
4
–
ns
tcclkmpwh
Write Clock Minimum Pulse Width High
1.8
–
ns
tcclkmpwl
Write Clock Minimum Pulse Width Low
1.8
–
ns
tblkcsu
Write Block Setup Time
0.417
–
ns
tblkchd
Write Block Hold Time
0.007
–
ns
tdincsu
Write Input Data setup Time
0.119
–
ns
tdinchd
Write Input Data hold Time
0.155
–
ns
taddrcsu
Write Address Setup Time
0.091
–
ns
taddrchd
Write Address Hold Time
0.132
–
ns
twecsu
Write Enable Setup Time
0.41
–
ns
twechd
Write Enable Hold Time
-0.027
–
ns
fmax
Maximum Frequency
–
250
MHz
Table 126 • uSRAM (RAM64x16) in 64x16 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tcy
Read Clock Period
tclkmpwh
Read Clock Minimum Pulse Width High
1.8
–
ns
tclkmpwl
Read Clock Minimum pulse Width Low
1.8
–
ns
tplcy
Read Pipe-line clock period
4
–
ns
tplclkmpwh
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tplclkmpwl
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.276
ns
Read Access Time without Pipeline Register
–
1.738
ns
Read Address Setup Time in Synchronous Mode
0.311
–
ns
Read Address Setup Time in Asynchronous Mode
1.916
–
ns
Read Address Hold Time in Synchronous Mode
0.094
–
ns
Read Address Hold Time in Asynchronous Mode
-0.803
–
ns
Read Enable Setup Time
0.287
–
ns
tclk2q
taddrsu
taddrhd
trdensu
Revision 4
88
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 126 • uSRAM (RAM64x16) in 64x16 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
trdenhd
Read Enable Hold Time
0.059
–
ns
tblksu
Read Block Select Setup Time
1.898
–
ns
tblkhd
Read Block Select Hold Time
-0.671
–
ns
tblk2q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.102
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
-0.15
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
Clock)
0.047
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.524
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
Clock)
0.244
–
ns
tr2q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
–
0.866
ns
tsrstsu
Read Synchronous Reset Setup Time
0.279
–
ns
tsrsthd
Read Synchronous Reset Hold Time
0.062
tccy
Write Clock Period
tcclkmpwh
trstrem
trstrec
ns
4
–
ns
Write Clock Minimum Pulse Width High
1.8
–
ns
tcclkmpwl
Write Clock Minimum Pulse Width Low
1.8
–
ns
tblkcsu
Write Block Setup Time
0.417
–
ns
tblkchd
Write Block Hold Time
0.007
–
ns
tdincsu
Write Input Data setup Time
0.119
–
ns
tdinchd
Write Input Data hold Time
0.155
–
ns
taddrcsu
Write Address Setup Time
0.091
–
ns
taddrchd
Write Address Hold Time
0.132
–
ns
twecsu
Write Enable Setup Time
0.41
–
ns
twechd
Write Enable Hold Time
-0.027
–
ns
fmax
Maximum Frequency
–
250
MHz
Table 127 • uSRAM (RAM128x9) in 128x9 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
tcy
Read Clock Period
tclkmpwh
Read Clock Minimum Pulse Width High
Revision 4
Min
Max
Units
4
–
ns
1.8
–
ns
89
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 127 • uSRAM (RAM128x9) in 128x9 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
1.8
–
ns
4
–
ns
tclkmpwl
Read Clock Minimum pulse Width Low
tplcy
Read Pipe-line clock period
tplclkmpwh
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tplclkmpwl
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.276
ns
Read Access Time without Pipeline Register
–
1.776
ns
Read Address Setup Time in Synchronous Mode
0.311
–
ns
Read Address Setup Time in Asynchronous Mode
1.959
–
ns
Read Address Hold Time in Synchronous Mode
0.125
–
ns
Read Address Hold Time in Asynchronous Mode
-0.704
–
ns
trdensu
Read Enable Setup Time
0.287
–
ns
trdenhd
Read Enable Hold Time
0.059
–
ns
tblksu
Read Block Select Setup Time
1.898
–
ns
tblkhd
Read Block Select Hold Time
-0.671
–
ns
tblk2q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.14
ns
-0.15
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
0.047
Clock)
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.524
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
0.244
Clock)
–
ns
–
0.865
ns
tclk2q
taddrsu
taddrhd
Read Asynchronous Reset Removal Time (Pipelined Clock)
trstrem
trstrec
tr2q
Read Asynchronous Reset to Output Propagation Delay (with
Pipe-Line Register Enabled)
tsrstsu
Read Synchronous Reset Setup Time
0.279
–
ns
tsrsthd
Read Synchronous Reset Hold Time
0.062
–
ns
tccy
Write Clock Period
4
–
ns
tcclkmpwh
Write Clock Minimum Pulse Width High
1.8
–
ns
tcclkmpwl
Write Clock Minimum Pulse Width Low
1.8
–
ns
tblkcsu
Write Block Setup Time
0.417
–
ns
tblkchd
Write Block Hold Time
0.007
–
ns
tdincsu
Write Input Data setup Time
0.104
–
ns
tdinchd
Write Input Data hold Time
0.142
–
ns
taddrcsu
Write Address Setup Time
0.091
–
ns
Revision 4
90
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 127 • uSRAM (RAM128x9) in 128x9 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
taddrchd
Write Address Hold Time
0.24
–
ns
twecsu
Write Enable Setup Time
0.41
–
ns
twechd
Write Enable Hold Time
-0.027
–
ns
fmax
Maximum Frequency
–
250
MHz
Table 128 • uSRAM (RAM128x8) in 128x8 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tcy
Read Clock Period
tclkmpwh
Read Clock Minimum Pulse Width High
1.8
–
ns
tclkmpwl
Read Clock Minimum pulse Width Low
1.8
–
ns
tplcy
Read Pipe-line clock period
4
–
ns
tplclkmpwh
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tplclkmpwl
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.276
ns
Read Access Time without Pipeline Register
–
1.776
ns
Read Address Setup Time in Synchronous Mode
0.311
–
ns
Read Address Setup Time in Asynchronous Mode
1.959
–
ns
Read Address Hold Time in Synchronous Mode
0.125
–
ns
Read Address Hold Time in Asynchronous Mode
-0.704
–
ns
trdensu
Read Enable Setup Time
0.287
–
ns
trdenhd
Read Enable Hold Time
0.059
–
ns
tblksu
Read Block Select Setup Time
1.898
–
ns
tblkhd
Read Block Select Hold Time
-0.671
–
ns
tblk2q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.14
ns
-0.15
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
0.047
Clock)
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.524
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
0.244
Clock)
–
ns
tclk2q
taddrsu
taddrhd
Read Asynchronous Reset Removal Time (Pipelined Clock)
trstrem
trstrec
Revision 4
91
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 128 • uSRAM (RAM128x8) in 128x8 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tr2q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
–
0.865
ns
tsrstsu
Read Synchronous Reset Setup Time
0.279
–
ns
tsrsthd
Read Synchronous Reset Hold Time
0.062
–
ns
tccy
Write Clock Period
4
–
ns
tcclkmpwh
Write Clock Minimum Pulse Width High
1.8
–
ns
tcclkmpwl
Write Clock Minimum Pulse Width Low
1.8
–
ns
tblkcsu
Write Block Setup Time
0.417
–
ns
tblkchd
Write Block Hold Time
0.007
–
ns
tdincsu
Write Input Data setup Time
0.104
–
ns
tdinchd
Write Input Data hold Time
0.142
–
ns
taddrcsu
Write Address Setup Time
0.091
–
ns
taddrchd
Write Address Hold Time
0.24
–
ns
twecsu
Write Enable Setup Time
0.41
–
ns
twechd
Write Enable Hold Time
-0.027
–
ns
fmax
Maximum Frequency
–
250
MHz
Table 129 • uSRAM (RAM256x4) in 256x4 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
4
–
ns
Units
tcy
Read Clock Period
tclkmpwh
Read Clock Minimum Pulse Width High
1.8
–
ns
tclkmpwl
Read Clock Minimum pulse Width Low
1.8
–
ns
tplcy
Read Pipe-line clock period
4
–
ns
tplclkmpwh
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tplclkmpwl
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.276
ns
Read Access Time without Pipeline Register
–
1.812
ns
Read Address Setup Time in Synchronous Mode
0.311
–
ns
Read Address Setup Time in Asynchronous Mode
1.993
–
ns
Read Address Hold Time in Synchronous Mode
0.125
–
ns
Read Address Hold Time in Asynchronous Mode
-0.669
–
ns
Read Enable Setup Time
0.287
–
ns
tclk2q
taddrsu
taddrhd
trdensu
Revision 4
92
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 129 • uSRAM (RAM256x4) in 256x4 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
trdenhd
Read Enable Hold Time
0.059
–
ns
tblksu
Read Block Select Setup Time
1.898
–
ns
tblkhd
Read Block Select Hold Time
-0.671
–
ns
tblk2q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.166
ns
-0.15
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
0.047
Clock)
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.524
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
0.244
Clock)
–
ns
–
0.863
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
trstrem
trstrec
tr2q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
tsrstsu
Read Synchronous Reset Setup Time
0.279
–
ns
tsrsthd
Read Synchronous Reset Hold Time
0.062
–
ns
tccy
Write Clock Period
4
–
ns
tcclkmpwh
Write Clock Minimum Pulse Width High
1.8
–
ns
tcclkmpwl
Write Clock Minimum Pulse Width Low
1.8
–
ns
tblkcsu
Write Block Setup Time
0.417
–
ns
tblkchd
Write Block Hold Time
0.007
–
ns
tdincsu
Write Input Data setup Time
0.104
–
ns
tdinchd
Write Input Data hold Time
0.142
–
ns
taddrcsu
Write Address Setup Time
0.091
–
ns
taddrchd
Write Address Hold Time
0.253
–
ns
twecsu
Write Enable Setup Time
0.41
–
ns
twechd
Write Enable Hold Time
-0.027
–
ns
fmax
Maximum Frequency
–
250
MHz
Table 130 • uSRAM (RAM512x2) in 512x2 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
tcy
Read Clock Period
tclkmpwh
Read Clock Minimum Pulse Width High
Revision 4
Min
Max
Units
4
–
ns
1.8
ns
93
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 130 • uSRAM (RAM512x2) in 512x2 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
1.8
–
ns
4
–
ns
tclkmpwl
Read Clock Minimum pulse Width Low
tplcy
Read Pipe-line clock period
tplclkmpwh
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tplclkmpwl
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.276
ns
Read Access Time without Pipeline Register
–
1.824
ns
Read Address Setup Time in Synchronous Mode
0.311
–
ns
Read Address Setup Time in Asynchronous Mode
2.023
–
ns
Read Address Hold Time in Synchronous Mode
0.141
–
ns
Read Address Hold Time in Asynchronous Mode
-0.599
–
ns
trdensu
Read Enable Setup Time
0.287
–
ns
trdenhd
Read Enable Hold Time
0.059
–
ns
tblksu
Read Block Select Setup Time
1.898
–
ns
tblkhd
Read Block Select Hold Time
-0.671
–
ns
tblk2q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.219
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
-0.15
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
Clock)
0.047
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.524
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
Clock)
0.244
–
ns
tr2q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
–
0.862
ns
tsrstsu
Read Synchronous Reset Setup Time
0.279
–
ns
tsrsthd
Read Synchronous Reset Hold Time
0.062
–
ns
tccy
Write Clock Period
4
–
ns
tcclkmpwh
Write Clock Minimum Pulse Width High
1.8
–
ns
tcclkmpwl
Write Clock Minimum Pulse Width Low
1.8
–
ns
tblkcsu
Write Block Setup Time
0.417
–
ns
tblkchd
Write Block Hold Time
0.007
–
ns
tdincsu
Write Input Data setup Time
0.104
–
ns
tdinchd
Write Input Data hold Time
0.142
–
ns
taddrcsu
Write Address Setup Time
0.091
–
ns
tclk2q
taddrsu
taddrhd
trstrem
trstrec
Revision 4
94
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 130 • uSRAM (RAM512x2) in 512x2 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
taddrchd
Write Address Hold Time
0.255
–
ns
twecsu
Write Enable Setup Time
0.41
–
ns
twechd
Write Enable Hold Time
-0.027
–
ns
fmax
Maximum Frequency
–
250
MHz
Speed Grade
–1
Units
Table 131 • uSRAM (RAM1024x1) in 1024x1 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Max
4
–
tcy
Read Clock Period
tclkmpwh
Read Clock Minimum Pulse Width High
1.8
tclkmpwl
Read Clock Minimum pulse Width Low
1.8
–
ns
tplcy
Read Pipe-line clock period
4
–
ns
tplclkmpwh
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tplclkmpwl
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.274
ns
Read Access Time without Pipeline Register
–
1.839
ns
Read Address Setup Time in Synchronous Mode
0.311
–
ns
Read Address Setup Time in Asynchronous Mode
2.041
–
ns
Read Address Hold Time in Synchronous Mode
0.141
–
ns
Read Address Hold Time in Asynchronous Mode
-0.623
–
ns
trdensu
Read Enable Setup Time
0.287
–
ns
trdenhd
Read Enable Hold Time
0.059
–
ns
tblksu
Read Block Select Setup Time
1.898
–
ns
tblkhd
Read Block Select Hold Time
-0.671
–
ns
tblk2q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.236
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
-0.15
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
Clock)
0.047
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.524
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
Clock)
0.244
–
ns
tclk2q
taddrsu
taddrhd
trstrem
trstrec
Revision 4
ns
ns
95
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 131 • uSRAM (RAM1024x1) in 1024x1 Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Units
Description
Min
Max
tr2q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
–
0.862
ns
tsrstsu
Read Synchronous Reset Setup Time
0.279
–
ns
tsrsthd
Read Synchronous Reset Hold Time
0.062
–
ns
tccy
Write Clock Period
4
–
ns
tcclkmpwh
Write Clock Minimum Pulse Width High
1.8
–
ns
tcclkmpwl
Write Clock Minimum Pulse Width Low
1.8
–
ns
tblkcsu
Write Block Setup Time
0.417
–
ns
tblkchd
Write Block Hold Time
0.007
–
ns
tdincsu
Write Input Data setup Time
0.003
–
ns
tdinchd
Write Input Data hold Time
0.142
–
ns
taddrcsu
Write Address Setup Time
0.091
–
ns
taddrchd
Write Address Hold Time
0.255
–
ns
twecsu
Write Enable Setup Time
0.41
–
ns
twechd
Write Enable Hold Time
-0.027
–
ns
fmax
Maximum Frequency
–
250
MHz
Revision 4
96
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
12. Embedded NVM (eNVM) Characteristics
Table 132 • eNVM Read Performance
Worst-Case Conditions: VDD = 1.14 V, VPPNVM = VPP = 2.375 V
Symbol
Tj
Description
Junction Temperature Range
Speed grade
FMAXREAD
eNVM Maximum Read Frequency
Operating Temperature Range
-55°C to 125°C
-40°C to 100°C
Unit
0°C to 85°C
°C
-1
Std
-1
Std
-1
Std
–
25
25
25
25
25
25
MHz
Table 133 • eNVM Page Programming
Worst-Case Conditions: VDD = 1.14 V, VPPNVM = VPP = 2.375 V
Symbol
Tj
Description
Junction Temperature Range
Speed grade
tPAGEPGM
eNVM Page Programming Time
Operating Temperature Range
-55°C to 125°C
-40°C to 100°C
Unit
0°C to 85°C
°C
-1
Std
-1
Std
-1
Std
–
40
40
40
40
40
40
ms
Revision 4
97
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
13. Crystal Oscillator
Table 134 describes the electrical characteristics of the crystal oscillator in the IGLOO2 FPGA and SmartFusion2 SoC
FPGAs.
Table 134 • Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
FXTAL
Operating frequency
–
20
–
MHz
ACCXTAL
Accuracy
–
–
0.006
%
CYCXTAL
Output duty cycle
–
49-51
47-53
%
JITPERXTAL
Output Period Jitter (peak to peak)
–
200
300
ps
JITCYCXTAL
Output Cycle to Cycle Jitter (peak to
peak)
–
200
550
ps
IDYNXTAL
Operating current
–
1.5
–
mA
VIHXTAL
Input logic level High
0.9 × VPP
–
–
V
VILXTAL
Input logic level Low
–
–
0.1 × VPP
V
SUXTAL
Startup time (with regard to
oscillator output)
–
–
1
ms
stable
Table 135 • Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
FXTAL
Operating frequency
–
2
–
MHz
ACCXTAL
Accuracy
–
–
0.003
%
CYCXTAL
Output duty cycle
–
49–51
47–53
%
JITPERXTAL
Output Period Jitter (peak to peak)
–
1
5
ns
JITCYCXTAL
Output Cycle to Cycle Jitter (peak to
peak)
–
1
5
ns
IDYNXTAL
Operating current
–
0.3
–
mA
VIHXTAL
Input logic level High
0.9 × VPP
–
–
V
VILXTAL
Input logic level Low
–
–
0.1 × VPP
V
SUXTAL
Startup time (with regard to stable
oscillator output)
–
–
4.5
ms
Table 136 • Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
FXTAL
Operating frequency
–
32
–
kHz
ACCXTAL
Accuracy
–
–
0.006
%
CYCXTAL
Output duty cycle
–
49–51
45.5–54.5
%
JITPERXTAL
Output Period Jitter (peak to peak)
–
150
300
ns
JITCYCXTAL
Output Cycle to Cycle Jitter (peak to peak)
–
150
300
ns
Revision 4
98
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 136 • Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz)
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
–
0.044
–
mA
IDYNXTAL
Operating current
VIHXTAL
Input logic level High
0.9 × VPP
–
–
V
VILXTAL
Input logic level Low
–
–
0.1 × VPP
V
SUXTAL
Startup time (with
oscillator output)
–
–
120
ms
regard
to
stable
14. On-Chip Oscillator
Table 137 and Table 138 describe the electrical characteristics of the available on-chip oscillators in the IGLOO2
FPGAs and SmartFusion2 SoC FPGAs.
Table 137 • Electrical Characteristics of the 50 MHz RC Oscillator
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
F50RC
Description
Operating frequency
ACC50RC
Accuracy
CYC50RC
Output duty cycle
JIT50RC
Output jitter (peak to peak)
IDYN50RC
Operating current
Condition
–
Min
–
Typ
50
Max
–
Units
MHz
–
–
1
8
%
–
–
49–51
46–54
%
Period Jitter
–
200
500
ps
Cycle-to-Cycle Jitter
–
320
900
ps
–
–
8.5
–
mA
Table 138 • Electrical Characteristics of the 1 MHz RC Oscillator
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Condition
Min
Typ
Max
Units
F1RC
Operating frequency
–
–
1
–
MHz
ACC1RC
Accuracy
–
–
1
6
%
CYC1RC
Output duty cycle
–
–
49–51
46.5–53.5
%
JIT1RC
Output jitter (peak to peak)
Period Jitter
–
10
36
ps
Cycle-to-Cycle Jitter
–
10
50
ps
IDYN1RC
Operating current
–
–
0.1
–
mA
SU1RC
Startup time
–
–
–
20
µs
Revision 4
99
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
15. Clock Conditioning Circuits (CCC)
Table 139 • IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Specification
Military Worst-Case Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Conditions
Min
Typ
Max
Units Notes
All CCC
1
–
200
MHz
–
32 kHz Capable CCC
0.032
200
MHz
–
Clock conditioning circuitry
output frequency fOUT_CCC
–
0.078
–
400
MHz
1
PLL VCO frequency
–
500
–
1000
MHz
2
Delay
increments
in
programmable delay blocks
–
–
75
100
ps
–
Number of programmable
values in each programmable
delay block
–
–
–
64
–
–
Acquisition time
–
–
70
100
µs
–
1 MHz ≤ fIN_CCC ≤ 25 MHz
10
–
90
%
–
25 MHz ≤ fIN_CCC ≤ 100 MHz
25
–
75
%
–
–
65
%
–
–
55
%
–
Clock conditioning circuitry
input frequency fIN_CCC
Internal Feedback
100 MHz ≤ fIN_CCC ≤ 150 MHz
35
Input Duty Cycle (Reference
45
150 MHz ≤ fIN_CCC ≤ 200 MHz
Clock)
External Feedback (CCC, FPGA, Off-chip)
1 MHz ≤ fIN_CCC ≤ 25 MHz
25
–
75
%
–
25 MHz ≤ fIN_CCC ≤ 35 MHz
35
–
65
%
–
35 MHz ≤ fIN_CCC ≤ 50 MHz
45
–
55
%
–
010, 025, and 050 Devices
46
–
52
%
–
090 and 150 Devices
44
–
52
%
–
Modulation frequency range
–
25
35
50
kHz
–
Modulation depth range
–
0
–
1.5
%
–
Modulation depth control
–
–
0.5
–
%
–
Output duty cycle
Spread Spectrum Characteristics
Notes:
1. The minimum output clock frequency is limited by the PLL. For more information refer to the
UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide.
2. The PLL is used in conjunction with the Clock Conditioning Circuitry. Performance will be limited by the CCC output
frequency.
Revision 4
100
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 140 • IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Jitter Specifications
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Conditions/Package Combinations
Units Notes
CCC Output Peak-to-Peak Period Jitter fOUT_CCC
010,
050
Packages
FG484
0 < SSO
<= 2
SSO = 0
20 MHz to 100 MHz
Max(110, ± 1% x (1/fOUT_CCC))
100 MHz to 400 MHz
120
SSO
<= 4
SSO
<= 8
SSO
<= 16
–
*
Max(150, ± 1% x (1/fOUT_CCC))
ps
–
ps
–
150
025 FG484 Package
170
0 < SSO <=16
*
20 MHz to 74 MHz
± 1% x (1/fOUT_CCC)
ps
–
74 MHz to 400 MHz
210
ps
–
090 FG484 and
FC1152 Packages
150
0 < SSO <=16
*
20 MHz to 100 MHz
± 1% x (1/fOUT_CCC)
ps
–
100 MHz to 400 MHz
150
ps
–
Note: *SSO Data is based on LVCMOS 2.5 V MSIO and/or MSIOD Bank I/Os.
16. JTAG
Table 141 • JTAG 1532
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
-1 Speed Grade
Parameter
Description
010
025
050
090
150
Units
tTCK2Q
Clock to Q (data out)
7.91
7.95
8.15
9.21
8.85
ns
tRSTB2Q
Reset to Q (data out)
6.54
6.27
7.54
7.94
8.99
ns
tDISU
Test Data Input Setup Time
-0.70
-0.70
-0.31
-1.33
-1.02
ns
tDIHD
Test Data Input Hold Time
2.38
2.47
2.13
2.71
2.59
ns
tTMSSU
Test Mode Select Setup Time
-0.86
-1.13
0.26
-1.03
-0.56
ns
tTMDHD
Test Mode Select Hold Time
1.48
1.98
0.21
1.69
1.05
ns
tTRSTREM ResetB Removal Time
-1.1
-1.38
-0.49
-0.8
-1.07
ns
tTRSTREC ResetB Recovery Time
-1.1
-1.38
-0.47
-0.8
-1.07
ns
FTCKMAX
25
25
25
25
25
MHz
TCK Maximum frequency
Revision 4
101
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
17. DEVRST_N Characteristics
Table 142 • DEVRST_N Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
Description
TRAMPDEVRSTN
DEVRST_N ramp rate
Min
Typ
Max
Units
Notes
–
–
10
ns
*
Note: * Slower ramp rates are susceptible to board level noise.
Revision 4
102
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
18. System Controller SPI Characteristics Table 143 • System Controller SPI Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
Description
Conditions
Min
Typ
Max
Units Notes
sp1
SC_SPI_SCK minimum period
–
20
–
–
ns
–
sp2
SC_SPI_SCK
width high
minimum
pulse
–
10
–
–
ns
–
sp3
SC_SPI_SCK
width low
minimum
pulse
–
10
–
–
ns
–
sp4
I/O Configuration: LVTTL
SC_SPI_SCK,
SC_SPI_SDO, 3.3V- 20mA
SC_SPI_SS rise time
AC Loading: 35pF
(10%-90%) 1
Test Conditions: Typical
Voltage, 25C
–
1.239
–
ns
*
sp5
I/O Configuration: LVTTL
SC_SPI_SCK,
SC_SPI_SDO, 3.3V- 20mA
SC_SPI_SS fall time
AC Loading: 35pF
(10%-90%) 1
Test Conditions: Typical
Voltage, 25C
–
1.245
–
ns
*
sp6
Data from master (SC_SPI_SDO)
–
setup time
160
–
–
ns
–
sp7
Data from master (SC_SPI_SDO)
–
hold time
160
–
–
ns
–
sp8
SC_SPI_SDI setup time
–
20
–
–
ns
–
sp9
SC_SPI_SDI hold time
–
20
–
–
ns
–
Note:
*For specific Rise/Fall Times, board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models. Use the supported I/O Configurations
for the System Controller SPI in Table 144.
Table 144 • Supported I/O Configurations for System Controller SPI (for MSIO Bank Only)
Voltage Supply
I/O Drive Configuration
Units
3.3 V
20
mA
2.5 V
16
mA
1.8 V
12
mA
1.5 V
8
mA
1.2 V
4
mA
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
19. Mathblock Timing Characteristics
The fundamental building block in any digital signal processing algorithm is the multiply-accumulate function. Each
IGLOO2 and SmartFusion2 SoC mathblock supports 18x18 signed multiplication, dot product, and built-in addition,
subtraction, and accumulation units to combine multiplication results efficiently.
Table 145 • Mathblocks With All Registers Used
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Mathblock With All Registers Used
Parameter
Description
Min
Max
Units
TMISU
Input, Control Register Setup time
0.149
–
ns
TMIHD
Input, Control Register Hold time
0.08
–
ns
TMOCDINSU
CDIN Input Setup time
1.68
–
ns
TMOCDINHD
CDIN Input Hold time
-0.419
–
ns
TMSRSTENSU
Synchronous Reset/Enable Setup time
0.185
–
ns
TMSRSTENHD
Synchronous Reset/Enable Hold time
0.011
–
ns
TMARSTREM
Asynchronous Reset Removal time
0
–
ns
TMARSTREC
Asynchronous Reset Recovery time
0.088
–
ns
TMOCQ
Output Register Clock to Out delay
–
0.232
ns
TMCLKMP
CLK Minimum period
2.245
–
ns
Table 146 • Mathblock With Input Bypassed and Output Registers Used
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Mathblock With Input Bypassed and Output Registers Used
Speed Grade
–1
Parameter
Description
Min
Max
Units
TMOSU
Output Register Setup time
2.294
–
ns
TMOHD
Output Register Hold time
-0.444
–
ns
TMOCDINSU
CDIN Input Setup time
1.68
–
ns
TMOCDINHD
CDIN Input Hold time
-0.419
–
ns
TMSRSTENSU
Synchronous Reset/Enable Setup time
0.115
–
ns
TMSRSTENHD
Synchronous Reset/Enable Hold time
0.011
–
ns
TMARSTREM
Asynchronous Reset Removal time
0
–
ns
TMARSTREC
Asynchronous Reset Recovery time
0.014
–
ns
TMOCQ
Output Register Clock to Out delay
–
0.232
ns
TMCLKMP
CLK Minimum period
2.179
–
ns
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 147 • Mathblock With Input Register Used and Output in Bypass Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Mathblock With Input Register Used and Output in Bypass Mode
Speed Grade
–1
Parameter
Min
Max
Units
Description
TMISU
Input Register Setup time
0.149
–
ns
TMIHD
Input Register Hold time
0.08
–
ns
TMSRSTENSU
Synchronous Reset/Enable Setup time
0.185
–
ns
TMSRSTENHD
Synchronous Reset/Enable Hold time
-0.012
–
ns
TMARSTREM
Asynchronous Reset Removal time
-0.005
–
ns
TMARSTREC
Asynchronous Reset Recovery time
0.088
–
ns
TMICQ
Input Register Clock to Output delay
–
2.52
ns
TMCDIN2Q
CDIN to Output delay
–
1.951
ns
Table 148 • Mathblock With Input and Output in Bypass Mode
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Mathblock With Input and Output in Bypass Mode
Parameter
Description
Min
Max
Units
TMIQ
Input to Output delay
–
2.568
ns
TMCDIN2Q
CDIN to Output delay
–
1.951
ns
20. Flash*Freeze Timing Characteristics
Table 149 • Flash*Freeze Entry and Exit Times
Military Worst-Case conditions: TJ = 125°C, VDD = 1.14 V
Symbols
Parameters
TFF_ENTRY Entry time
Entry/Exit
Timing
Units
Notes
eNVM and MSS/HPMS PLL = ON
160
μs
1
eNVM and MSS/HPMS PLL = OFF
215
μs
1
Conditions
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 149 • Flash*Freeze Entry and Exit Times (continued)
Military Worst-Case conditions: TJ = 125°C, VDD = 1.14 V
eNVM and MSS/HPMS PLL = ON during F*F
eNVM=ON and MSS/HPMS PLL =OFF
during F*F and MSS/HPMS PLL turned back
Exit Time with on at exit
respect to MSS
eNVM and MSS PLL=OFF during F*F and
PLL Lock
both are turned back on at exit
TFF_EXIT
eNVM=OFF and MSS PLL = ON during F*F
and eNVM turned back on at exit
Exit Time with eNVM and MSS/HPMS PLL = ON during F*F
respect to Fabric eNVM and MSS PLL=OFF during F*F and
PLL Lock
both are turned back on at exit
Exit Time with eNVM and MSS/HPMS PLL = ON during F*F
respect to Fabric eNVM and MSS PLL=OFF during F*F and
buffer output
both are turned back on at exit
100
μs
1
136
μs
1
200
μs
1
200
μs
1
1.5
ms
1,2
1.5
ms
1,2
21
μs
1,2
65
μs
1
Notes:
1. F*F entry and exit times were measured with FCLK = 100 MHz
2. PLL Lock Delay set to 1024 cycles (default)
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
21. DDR Memory Interface Characteristics
Table 150 • DDR Memory Interface Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Supported Data Rate
Standard
Min
Typ
Max
Unit
DDR3
667
Mbps
DDR2
667
Mbps
LPDDR
50
–
Revision 4
400
Mbps
107
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
22. SFP Transceiver Characteristics
IGLOO2 and SmartFusion2 SERDES complies with small form-factor pluggable (SFP) requirements as specified in
SFP INF-80741. Table 151 provides the electrical characteristics.
Table 151 • SFP Transceiver Electrical Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Differential Peak-Peak Voltage
Pin
Direction
Min
Typ
Max
Unit
Note
RD+/-
Output
1600
–
2400
mV
1
TD+/-
Input
350
–
2400
mV
2
Notes:
1. Based on default SERDES transmitter settings for PCIe Gen1. Lower amplitudes are available through programming
changes to TX_AMP setting.
2. Based on Input Voltage Common-Mode (VICM) = 0 V. Requires AC Coupling.
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
23. PCIe Electrical and Timing AC and DC Characteristics
PCIe® is a high speed, packet-based, point-to-point, low pin count, serial interconnect bus. The IGLOO2 and
SmartFusion2 SoC FPGAs has up to four hard high-speed serial interface blocks. Each SERDES block contains a
PCIe system block. The PCIe system is connected to the SERDES block.
Table 152 • Transmitter Parameters
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
0.8
–
1.2
V
–
–
20
mV
0.125
–
–
UI
VTX-DIFF-PP
Differential swing PCIe Gen1
VTX-CM-AC-P
Output common mode voltage PCIe Gen1
VTX-RISE-FALL
Rise and fall time (20% to 80%) PCIe Gen1
ZTX-DIFF-DC
Output impedance – differential
80
–
120

LTX-SKEW
Lane-to-lane TX skew within a SERDES block
PCIe Gen1
–
–
500 ps
+ 2 UI
ps
RLTX-DIFF
Return loss differential mode PCIe Gen1
–10
–
–
dB
RLTX-CM
Return loss common mode PCIe Gen1
–6
–
–
dB
TX-LOCK-RST
Transmit PLL lock time from reset
–
–
10
µs
Min
Typ
Max
Units
0.175
–
1.2
V
NA
NA
NA
–
–
–
150
mV
0.175
–
–
mV
Table 153 • Receiver Parameters
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
VRX-DIFF-PP-CC
Input levels PCIe Gen1
Input common mode range (DC coupled)
VRX-CM-DC-P
Note: PCIe standard mandates AC coupling
VRX-CM-AC-P
Input common mode range (AC coupled)
VRX-DIFF-PP-CC
Differential input sensitivity Gen1
ZRX-DIFF-DC
Differential input termination
80
100
120

REXT
External calibration resistor
1,188
1,200
1,212

CDR-LOCK-RST
CDR relock time from reset
–
–
15
µs
RLRX-DIFF
Return loss differential mode PCIe Gen1
–10
–
–
dB
RLRX-CM
Return loss common mode PCIe Gen1
–6
–
–
dB
CID limit (set by 8B/10B coding, not the receiver
PLL)
–
–
4
UI
Signal detect limit
65
–
175
mV
VRX-IDLE-DET-DIFF-PP
Table 154 • SERDES Reference Clock AC Specifications
Worst-Case Military Conditions: TJ = 125°C, Worst-Case VDD = 1.14V
Symbols
Description
Min
Typ
Max
Units
FREFCLK
Reference Clock Frequency
100
–
160
MHz
TRISE
Reference Clock Rise Time
0.6
–
4
V/ns
TFALL
Reference Clock Fall Time
0.6
–
4
V/ns
TCYC
Reference Clock Duty Cycle
40
–
60
%
Mmrefclk
Reference Clock Mismatch
-300
–
300
ppm
SSCref
Reference Spread Spectrum Clock
0
–
5000
ppm
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 155 • HCSL Minimum and Maximum DC Input Levels (Applicable to SERDES REFCLK Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
2.375
2.5
2.625
V
–
0
–
2.625
V
Input common mode voltage
–
0.05
–
2.4
V
Input differential voltage
–
100
–
1100
mV
Recommended DC Operating Conditions
VDDI
Supply Voltage
HCSL DC Input Voltage Specification
VI
DC Input voltage
HCSL Differential Voltage Specification
VICM
VIDIFF
Table 156 • HCSL Maximum AC Switching Speeds (Applicable to SERDES REFCLK Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
–
350
Mbps
–
–
100
–

HCSL AC Specifications
Fmax
Maximum Data Rate (for MSIO
IO Bank)
HCSL Impedance Specifications
Rt
Termination Resistance
24. SmartFusion2 Specifications
24.1 MSS Clock Frequency
Table 157 • Maximum Frequency for MSS Main Clock
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Symbol
M3_CLK
Description
Speed Grade
–1
Units
133
MHz
Maximum frequency for the MSS Main Clock (FCLK)
24.2 SmartFusion2 Inter-Integrated Circuit (I2C) Characteristics
This section describes the DC and switching of the IC interface. Unless otherwise noted, all output characteristics
given are for a 100 pF load on the pins. For timing parameter definitions, refer to Figure 16 on page 112.
Table 158 • I2C Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
VIL
VIH
Definition
Conditions
Typ
Max
Input low voltage
Refer to the "Single-Ended I/O Standards"
section on page 27 for more information. I/O
–0.3
standard used for illustration:
MSIO bank– LVTTL 8 mA low drive.
–
0.8
V
–
Input high voltage
Refer to the "Single-Ended I/O Standards"
section on page 27 for more information. I/O
standard used for illustration:
MSIO bank – LVTTL 8 mA low drive.
–
3.45
V
–
Revision 4
Min
2
Units Notes
110
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 158 • I2C Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
Parameter
Definition
Conditions
Min
Typ
Max
Units Notes
–
–
V
–
VHYS
Hysteresis of Schmitt
Refer to Table 20 on page 27 for more 0.05 x
triggered inputs for
information.
VDDI
VDDI > 2 V
IIL
Input current high
Refer to the "Single-Ended I/O Standards"
section on page 27 for more information.
–
–
10
µA
–
IIH
Input current low
Refer to the "Single-Ended I/O Standards"
section on page 27 for more information.
–
–
10
µA
–
Tir
Input rise time
Standard Mode
–
–
1000
ns
–
–
–
Fast Mode
–
–
300
ns
–
Tif
Input fall time
Standard Mode
–
–
300
ns
–
–
–
Fast Mode
–
–
300
ns
–
VOL
Maximum
output
voltage
low
(open
drain) at 3 mA sink
current for VDDI > 2 V
Refer to the "Single-Ended I/O Standards"
section on page 27 for more information. I/O
standard used for illustration:
MSIO bank – LVTTL 8 mA low drive.
–
–
0.4
V
–
Cin
Pin capacitance
VIN = 0, f = 1.0 MHz
–
–
10
pF
–
tOF
Output fall time from VIHmin to VILMax, Cload = 400 pF
VIHMin to VILMax
VIHmin to VILMax, Cload = 100 pF
–
21.04
–
ns
1
–
5.556
–
ns
tOR
Output rise time from VILMax to VIHmin, Cload = 400pF
VILMax to VIHMin
VILMax to VIHmin, Cload = 100pF
–
19.887
–
ns
–
5.218
–
ns
Rpull-up
Output
maximum
resistance
buffer
pull-down –
–
–
50

2, 3
Rpulldown
Output
maximum
resistance
buffer
pull-up –
–
–
131.25

2, 4
Dmax
Maximum data rate
Fast mode
–
–
400
Kbps
–
Standard mode
–
–
100
Kbps
–
tFILT
Pulse width of spikes
which
must
be
Fast mode
suppressed by the
input filter
–
50
–
ns
–
1
Notes:
1. These values are provided for MSIO Bank - LVTTL 8 mA Low Drive at 25°C, typical conditions. For Board Design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products
Group website: http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
2. These maximum values are provided for information only. Minimum output buffer resistance values depend on VDDIx,
drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located on the SoC Products Group website:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
3. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
4. R(PULL-UP-MAX) = (VDDImax – VOHspec) / IOHspec
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 159 • I2C Switching Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Definition
Conditions
Min
Max
Units
tLOW
Low period of I2C_x_SCL
–
1
–
pclk cycles
tHIGH
High period of I2C_x_SCL
–
1
–
pclk cycles
tHD;STA
START hold time
–
1
–
pclk cycles
tSU;STA
START setup time
–
1
–
pclk cycles
tHD;DAT
DATA hold time
–
1
–
pclk cycles
tSU;DAT
DATA setup time
–
1
–
pclk cycles
tSU;STO
STOP setup time
–
1
–
pclk cycles
SDA
TRISE
SCL
tLOW
tSU;STA
S
tHD;STA
TFALL
tHIGH
tHD;DAT
tSU;STO
tSU;DAT
P
Figure 16 • I2C Timing Parameter Definition
Revision 4
112
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
24.3 Serial Peripheral Interface (SPI) Characteristics
This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics
given are for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_x_CLK. For timing
parameter definitions, refer to Figure 17 on page 115.
Table 160 • SPI Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
Description
Conditions
Min
Typ Max Unit Notes
SPI_[0|1]_CLK minimum period
sp1
SPI_[0|1]_CLK = PCLK/2
–
12
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
–
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
–
48.2
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
–
0.1
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
–
0.19
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
–
0.39
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
–
0.77
–
–
µs
–
SPI_[0|1]_CLK minimum pulse width high
sp2
SPI_[0|1]_CLK = PCLK/2
–
6
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
–
12.05
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
–
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
–
0.05
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
–
0.095
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
–
0.195
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
–
0.385
–
–
µs
–
SPI_[0|1]_CLK minimum pulse width low
sp3
SPI_[0|1]_CLK = PCLK/2
–
6
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
–
12.05
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
–
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
–
0.05
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
–
0.095
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
–
0.195
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128 –
0.385
–
–
µs
–
Notes:
1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding
IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the UG0331:
SmartFusion2 Microcontroller Subsystem User Guide.
Revision 4
113
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 160 • SPI Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
All Devices/Speed Grades
Symbol
sp4
sp5
Description
Conditions
Min
Typ Max Unit Notes
SPI_[0|1]_CLK,
SPI_[0|1]_DO,
SPI_[0|1]_SS rise
(10%-90%)
IO Configuration:
LVCMOS 2.5 V
- 8mA
AC Loading: 35pF
time
Test Conditions:
Typical Voltage,
25°C
–
2.77
–
ns
1
SPI_[0|1]_CLK,
SPI_[0|1]_DO,
SPI_[0|1]_SS
fall
(10%-90%)
IO Configuration:
LVCMOS 2.5 V
- 8mA
AC Loading: 35pF
time
Test Conditions:
Typical Voltage,
25°C
–
2.90
6
–
ns
1
SPI Master Configuration
sp6m
SPI_[0|1]_DO setup time
–
(SPI_x_CLK_period/2) – 3.0
–
–
ns
2
sp7m
SPI_[0|1]_DO hold time
–
(SPI_x_CLK_period/2) – 2.5
–
–
ns
2
sp8m
SPI_[0|1]_DI setup time
–
8
–
–
ns
2
sp9m
SPI_[0|1]_DI hold time
–
2.5
–
–
ns
2
SPI Slave Configuration
sp6s
SPI_[0|1]_DO setup time
–
(SPI_x_CLK_period/2) – 12.0
–
–
ns
2
sp7s
SPI_[0|1]_DO hold time
–
(SPI_x_CLK_period/2) + 3.0
–
–
ns
2
sp8s
SPI_[0|1]_DI setup time
–
2
–
–
ns
2
sp9s
SPI_[0|1]_DI hold time
–
3
–
–
ns
2
Notes:
1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding
IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the UG0331:
SmartFusion2 Microcontroller Subsystem User Guide.
Revision 4
114
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
SP1
SP4
SP2
50% 50%
SPI_0_CLK
SPO = 0
SP5
SP3
90%
50%
10%
10%
SPI_0_CLK
SPO = 1
90%
90%
SPI_0_SS
10%
1 0%
SP4
SP5
SP6
SPI_0_DO
5 0%
MSB
90%
9 0%
5 0%
10%
SP8
SPI_0_DI
SP7
50%
SP9
MSB
SP5
10%
SP4
50%
Figure 17 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)
Revision 4
115
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
25. CAN Controller Characteristics
Table 161 • CAN Controller Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units Notes
FCANREFCLK
Internally Sourced CAN Reference Clock Frequency
–
–
128
MHz
*
BAUDCAN
CAN Performance Baud Rate
0.05
–
1
Mbps
–
Note: PCLK to CAN controller must be a multiple of 8 MHz.
Revision 4
116
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
26. USB Characteristics
Table 162 • USB Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
FUSBREFCLK Internally Sourced USB Reference Clock Frequency
–
–
133
MHz
TUSBCLK
USB Clock Period
–
–
16.66
ns
TUSBPD
Clock to USB Data Propagation Delay
–
–
9.0
ns
TUSBSU
Setup Time for USB Data
–
–
6.0
ns
TUSBHD
Hold Time for USB Data
0
–
–
ns
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
27. IGLOO2 Specifications
27.1 HPMS Clock Frequency
Table 163 • Maximum Frequency for HPMS Main Clock
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
Symbol
Description
HPMS_CLK
Maximum Frequency for the HPMS Main Clock (FCLK)
Speed Grade
–1
Units
133
MHz
27.2 IGLOO2 Serial Peripheral Interface (SPI) Characteristics
This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics
given are for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_0_CLK. For timing
parameter definitions, refer to Figure 18 on page 120.
Table 164 • SPI Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
Description
Conditions
Min
Typ
Ma
x
Uni
t
Note
s
SPI_[0|1]_CLK minimum period
sp1
SPI_[0|1]_CLK = PCLK/2
–
12
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
–
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
–
48.2
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
–
0.1
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
–
0.19
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
–
0.39
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
–
0.77
–
–
µs
–
SPI_[0|1]_CLK minimum pulse width high
sp2
SPI_[0|1]_CLK = PCLK/2
–
6
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
–
12.05
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
–
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
–
0.05
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
–
0.095
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
–
0.195
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
–
0.385
–
–
µs
–
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 164 • SPI Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
All Devices/Speed Grades
Symbol
Description
Conditions
Min
Typ
Ma
x
Uni
t
Note
s
SPI_[0|1]_CLK minimum pulse width low
SPI_[0|1]_CLK = PCLK/2
–
6
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
–
12.05
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
–
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
–
0.05
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
–
0.095
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
–
0.195
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
–
0.385
–
–
µs
–
sp4
I/O
Configuration:
LVCMOS 2.5 V8mA
SPI_[0|1]_CLK,
SPI_[0|1]_DO, SPI_[0|1]_SS
AC Loading:
rise time (10%-90%)
35pF
Test Conditions:
Typical Voltage,
25°C
–
2.77
–
ns
1
sp5
I/O
Configuration:
LVCMOS 2.5 V8mA
SPI_[0|1]_CLK,
SPI_[0|1]_DO, SPI_[0|1]_SS
AC Loading:
fall time (10%-90%)
35pF
Test Conditions:
Typical Voltage,
25°C
–
2.90
6
–
ns
1
sp3
SPI Master Configuration
sp6m
SPI_[0|1]_DO setup time
–
(SPI_x_CLK_period/2) – 3.0
–
–
ns
2
sp7m
SPI_[0|1]_DO hold time
–
(SPI_x_CLK_period/2) – 2.5
–
–
ns
2
sp8m
SPI_[0|1]_DI setup time
–
8
–
–
ns
2
sp9m
SPI_[0|1]_DI hold time
–
2.5
–
–
ns
2
SPI Slave Configuration
sp6s
SPI_[0|1]_DO setup time
–
(SPI_x_CLK_period/2) – 12.0
–
–
ns
2
sp7s
SPI_[0|1]_DO hold time
–
(SPI_x_CLK_period/2) + 3.0
–
–
ns
2
sp8s
SPI_[0|1]_DI setup time
–
2
–
–
ns
2
Revision 4
119
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 164 • SPI Characteristics
Worst-Case Military Conditions: TJ = 125°C, VDD = 1.14 V (continued)
All Devices/Speed Grades
Symbol
sp9s
Description
Conditions
Min
Typ
Ma
x
Uni
t
Note
s
–
3
–
–
ns
2
SPI_[0|1]_DI hold time
Notes:
1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding
IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the UG0331:
SmartFusion2 Microcontroller Subsystem User Guide.
SP1
SP4
SP2
50% 50%
SPI_0_CLK
SPO = 0
SP5
SP3
90%
50%
10%
10%
SPI_0_CLK
SPO = 1
90%
90%
SPI_0_SS
10%
1 0%
SP4
SP5
SP6
SPI_0_DO
5 0%
MSB
90%
9 0%
5 0%
10%
SP8
SPI_0_DI
SP7
50%
SP9
MSB
SP5
10%
SP4
50%
Figure 18 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)
Revision 4
120
Datasheet Information
List of Changes
The following table shows important changes made in this document for each revision.
Revision
Changes
Page
Updated Table 9: "SmartFusion2 and IGLOO2 Quiescent Supply Current – Typical
Process" for typical process values (SAR 69218).
17
Updated Table 10: "SmartFusion2 and IGLOO2 Quiescent Supply Current – WorstCase Process" for worst process values (SAR 69218).
18
Updated Table 140: "IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Jitter
Specifications" for FG484 package (SAR 69804).
101
Revision 3
(June 2015)
Updated Table 1: "IGLOO2 FPGA and SmartFusion2 SoC FPGA Device Status"
(SAR 68620).
10
Revision 2
(June 2015)
Updated Table 1: "IGLOO2 FPGA and SmartFusion2 SoC FPGA Device Status"
10
Updated Table 3: "Recommended Operating Conditions"
12
Updated Table 4: "FPGA Operating Limits" (SAR 63109).
14
Updated Table 7: "Package Thermal Resistance"
15
Revision 4
(September 2015)
Updated Table 65: "DDR2/SSTL18 AC Specifications (Applicable to DDRIO Bank
Only)" and Table 69: "DDR3/SSTL15 AC Specifications" (SAR 67210).
Added "Embedded NVM (eNVM) Characteristics" (SAR 52509).
Updated Table 139: "IGLOO2 and SmartFusion2 SoC
Specification" (SAR 65958, SAR 62012, and SAR 56666).
49, 51
97
FPGAs
CCC/PLL
100
Updated Table 141: "JTAG 1532"
101
Added "DEVRST_N Characteristics " (SAR 64100).
102
Added "DDR Memory Interface Characteristics" (SAR 66223).
107
Added "SFP Transceiver Characteristics" (SAR 63105).
108
Added "CAN Controller Characteristics" (SAR 50424).
116
Added "USB Characteristics" (SAR 50424).
117
Updated Table 157: "Maximum Frequency for MSS Main Clock" and
110, 118
Table 163: "Maximum Frequency for HPMS Main Clock" (SAR 66314).
Revision 1
(December 2014)
Initial release.
NA
Revision 4
121
Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in Table 1 on page 10 is designated as either "Product Brief," "Advance," "Preliminary," or
“Production.” The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be
used when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Revision 4
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Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA
Safety Critical, Life Support, and High-Reliability Applications
Policy
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Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
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For more information covering all of the SoC Products Group’s products refer to the Reliability Report.
Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures.
Contact your local Sales office for additional reliability information.
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Revision 4
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