Display Controller UG0649 User Guide Table of Contents Introduction ....................................................................................................3 Hardware Implementation .............................................................................4 Inputs and Outputs ..................................................................................................................... 5 Configuration Parameters .......................................................................................................... 7 Timing Diagrams ........................................................................................................................ 8 Resource Utilization ................................................................................................................... 9 List of Changes ............................................................................................ 10 Product Support .......................................................................................... 11 Customer Service..................................................................................................................... 11 Customer Technical Support Center ........................................................................................ 11 Technical Support .................................................................................................................... 11 Website .................................................................................................................................... 11 Contacting the Customer Technical Support Center ............................................................... 11 ITAR Technical Support ........................................................................................................... 12 2 UG0651: Display Controller User Guide Introduction The display controller generates the display synchronization signals based on the display resolution. The synchronization signals are horizontal sync, vertical sync, and data enable. The input video RGB data is also synchronized with these sync signals. The sync signals along with video data can be fed to a DVI, HDMI, or VGA card that interfaces with the display monitor. Horizontal Sync Horizontal Front Porch Horizontal Active Video Horizontal Back porch Figure 1 shows the sync signal waveforms. Data Enable Vertical Back Porch Active Video Active Video Vertical Front Porch Vertical Sync Figure 1 · Sync Signal Waveforms 3 UG0651: Display Controller User Guide Hardware Implementation Figure 2 shows the Display Controller block diagram. Display Controller Top SYS_CLOCK_I VIDEO_CLOCK_I RESET_N_I DDR Read Controller display_control_enable_i tot_horz_pixels_i tot_vert_lines_i video_resolution_i 32 back_porch_width_i 32 front_porch_width_i 32 hactive_o vactive_o 24 hsync_width_i rgb_out_o data_enable_o vsync_width_i horz_sync_o frame_buff_addr_i frame_ddr_addr_valid_i Video FIFO video_datain_i vert_sync_o Video Timing Generator frame_buff_und_disp_o disp_cont_busy_o data_valid_i disp_cont_done_o read_ack_i read_req_o 32 read_done_i start_read_addr_o 16 bytes_to_read_o Figure 2 · Block Diagram 4 UG0651: Display Controller User Guide Inputs and Outputs Inputs and Outputs Table 1 shows the description of input and output ports. Table 1 · Inputs and Outputs of Display Controller Signal Name Direction RESET_N_I Input Width – – SYS_CLOCK_I Input VIDEO_CLOCK_I Input display_control_enable_i Input tot_horz_pixels_i Input tot_vert_lines_i Input – – [(g_INPUT_X_W_RES_WIDTH -1) :0] [(g_INPUT_Y_H_RES_WIDTH -1) :0] Description Active low asynchronous reset signal to design The DDR-SDRAM interface input/output signals are synchronized with the clock input (SYS_CLOCK_I). Clock Input on which the video data and sync outputs are synchronized Enable input to the module to start the display Total width of one horizontal line Total number of vertical lines Video resolution video_resolution_i Input [31:0] [15:0] horizontal resolution [31:16] Vertical resolution Back Porch width back_porch_width_i Input [31:0] [15:0] horizontal back porch [31:16] Vertical back porch Front Porch width front_porch_width_i Input [31:0] [15:0] horizontal front porch [31:16] Vertical front porch hsync_width_i Input [(g_INPUT_X_W_RES_WIDTH -1):0] Horizontal SYNC (HSYNC) pulse width vsync_width_i Input [(g_INPUT_Y_H_RES_WIDTH -1):0] Vertical SYNC (VSYNC) pulse width frame_buff_addr_i Input [(g_DDR_AXI_AWIDTH -1):0] Base address of display frame buffer frame_ddr_addr_valid_i Input – Valid input for base address of display frame buffer frame_buff_und_disp_o Output [(g_DDR_AXI_AWIDTH -1):0] Base address of the current display frame buffer read_req_o Output read_ack_i Input UG0649: Display Controller User Guide – Read request to external memory controller – Acknowledgment from external memory controller for the read request 5 Inputs and Outputs Signal Name Direction read_done_i Input Width – Description Read completion from external memory controller start_read_addr_o Output [31:0] Frame buffer memory address from where read must be started bytes_to_read_o Output [15:0] Bytes to be read out from the frame buffer memory [(g_VIDEO_WIDTH – 1):0] Video data input from frame buffer memory video_datain_i Input data_valid_i Input – Read data valid from frame buffer memory disp_cont_busy_o Output – Display controller busy status signal disp_cont_done_o Output – Display controller done status signal rgb_out_o Output [23:0] RGB output data_enable_o Output – Video data enable output horz_sync_o Output – Horizontal sync signal vert_sync_o Output – Vertical sync signal hactive_o Output – Display horizontal active video vactive_o Output – Display vertical active video The display controller • Reads the video data from the specified display frame buffers located in data-double rate synchronous dynamic random access memory (DDR-SDRAM) and buffers the data in the internal first-in first-out (FIFO) • Generates the timing required for the specified display resolution. o Synchronizes the input video data according to the video timing o Generates the output (the synchronized video data along with the required sync pulses). The display controller takes the required video resolution parameters from an external controller as inputs. These parameters are the width and height, active video width and height, horizontal and vertical back and front porch, and horizontal and vertical sync pulse widths. For reading the video data from the frame buffer, the display controller requires the base address of the frame buffer. An external controller must provide the base address on the frame_buff_addr_i signal and validate it with an active high pulse on the frame_ddr_addr_valid_i signal. The display_control_enable_i signal enables the display controller. Before enabling the display controller, all the video resolution inputs must be provided to the respective inputs. After enabling the signal, the display controller samples the video resolution input values and update the internal counters terminal values. It has two counters running on the VIDEO_CLOCK_I—horizontal pixel counter and vertical line counter. The display controller requests for video data from the external memory controller and stores in an internal FIFO. To request data, the display controller provides the starting address on start_read_addr_o output and data bytes to read on bytes_to_read_o output to the external memory controller. It sends a High signal on read_req_o output. It holds the high state on read_req_o till the external memory controller acknowledges it by toggling read_ack_i. The input data video_datain_i signal is stored into the internal FIFO using the input data valid signal data_valid_i. It waits for the completion of the read process by monitoring the read_done_i input from the external memory controller. The video data read interface is synchronized using SYS_CLOCK_I signal. The internal FIFO acts as an internal buffer and takes care of clock domain crossing between SYS_CLOCK_I and VIDEO_CLOCK_I signals. 6 UG0651: Display Controller User Guide Configuration Parameters When a read process is started on a new frame buffer, display controller fills the internal buffer with multiple horizontal lines of video data, which the g_INITIAL_LINES_TO_BUFFER global configuration parameter determines. Subsequent read requests are generated based on the half-empty status signal from the internal FIFO. The g_SUBSEQUENT_LINES_TO_BUFFER global configuration parameter determines the number of subsequent horizontal lines to read from frame buffer memory. The display controller has the following two status output signals: • disp_cont_busy_o—indicates the display process in-progress • disp_cont_done_o—indicates the completion of the current display frame buffer When a new frame buffer is read, its base address is output on the frame_buff_und_disp_o, which can be used by the external controller to know that the particular frame buffer is under display. The display controller supports the maximum resolution of 2048 x 1536. The internal FIFO is configured to the maximum depth of 4096, which is configured using the global configurable parameter, g_VIDEO_BUFF_AWIDTH. Configuration Parameters Table 2 shows the description of the configuration parameters used in the hardware implementation of Display Controller. They are the generic parameters and can vary based on the application requirements. Table 2 · Configuration Parameters Name Description g_DDR_AXI_AWIDTH DDR-SDRAM AXI address bus width g_INPUT_X_W_RES_WIDTH Input resolution bit width for frame buffer X location and object width g_INPUT_Y_H_RES_WIDTH Input resolution bit width for frame buffer Y location and object height g_VIDEO_FIFO_AWIDTH Address bus width for the internal FIFO, which stores the video data g_INPUT_VIDEO_DATA_BIT_WIDTH Input video data bit width g_DEPTH_OF_VIDEO_PIXEL_FROM_DDR Number of bytes used to represent each pixel g_HORZ_SYNC_PULSE_POLARITY Polarity of the HSYNC g_VERT_SYNC_PULSE_POLARITY Polarity of the VSYNC g_MAX_HORIZOANTAL_RESOLUTION Maximum horizontal video resolution g_INITIAL_LINES_TO_BUFFER Number of display horizontal lines that are buffered for the first read from frame buffer memory g_SUBSEQUENT_LINES_TO_BUFFER Number of display horizontal lines that are buffered in subsequent reads from frame buffer memory g_HALF_EMPTY_THRESHOLD Half empty threshold of the internal video FIFO. This threshold determines the DDR read transactions UG0649: Display Controller User Guide 7 Timing Diagrams Timing Diagrams Figure 3 shows the read request, starting memory address, bytes to read, read acknowledgement, and read done from external memory controller in the timing diagram. SYS_CLOCK_I start_read_addr_o bytes_to_read_o ADDR0 ADDR1 Bytes0 Bytes1 read_req_o read_ack_i read_done_i Figure 3 · Timing Diagram (start_read_addr_o, bytes_to_read_o, read_req_o, read-ack_i, and read_done_i) Figure 4 shows the video data input from the external memory controller with the valid data in the timing diagram. SYS_CLOCK_I video_datain_i DATA0 DATA1 DATA2 DATA3 DATA4 DATAn-1 DATAn data_valid_i Figure 4 · Video Data Input Relationship Timing Diagram for the video_datain_i and data_valid_i 8 UG0651: Display Controller User Guide Resource Utilization Resource Utilization ® Table 3 shows the resource utilization of the Display Controller implemented in the SmartFusion 2 system-on-chip (SoC) field programmable gate array (FPGA) device. Table 3 · Resource Utilization for Display Controller Resource Usage DFFs 620 4-input LUTs 1140 MACC 0 RAM1Kx18 6, for maximum horizontal resolution of 2048 RAM64x18 0 UG0649: Display Controller User Guide 9 List of Changes The following table shows important changes made in this document for each revision Revision Changes Page Revision 2 (February 2016) Updated the SAR (76065). NA Revision 1 (August 2015) Initial release NA 10 UG0651: Display Controller User Guide Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world 408.643.6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. 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